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The document contains 5 problems related to Verilog code and testbenches. Problem 1 provides Verilog code for a module with 3 inputs and 1 output, and a testbench that simulates it by iterating all input combinations. Problem 2 provides code for a Moore machine to convert NRZ to Manchester encoding, and a testbench. Problem 3 provides a set of logic operations to perform on variables. Problem 4 provides code for a module that compares two numbers and indicates if they are equal, greater than, or less than, with a testbench. Problem 5 analyzes the logic behind the output of a code snippet based on the values of inputs a, b, and c.

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Aarushi Gupta
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60 views8 pages

ADD hw4

The document contains 5 problems related to Verilog code and testbenches. Problem 1 provides Verilog code for a module with 3 inputs and 1 output, and a testbench that simulates it by iterating all input combinations. Problem 2 provides code for a Moore machine to convert NRZ to Manchester encoding, and a testbench. Problem 3 provides a set of logic operations to perform on variables. Problem 4 provides code for a module that compares two numbers and indicates if they are equal, greater than, or less than, with a testbench. Problem 5 analyzes the logic behind the output of a code snippet based on the values of inputs a, b, and c.

Uploaded by

Aarushi Gupta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Problem 1: ADD HW #4 – AARUSHI GUPTA

Verilog code-

module prog1(input wire a,b,c, output reg out);

always @(a or b or c)

begin

out = (a^b)|((~b)&c);

end

endmodule

Verilog testbench-

module testprog1();

reg a,b,c;

wire out;

prog1 p1(.a(a),.b(b),.c(c),.out(out));

integer i;

initial

begin

for (i=0;i<8;i=i+1)

#5{a,b,c}=i;

end

endmodule
Simulation waveform-

Problem 2:

Verilog code-

module NRZtoManchesterMooremachine (input in, clk, reset, output reg out);

reg [1: 0] state, nextstate;

parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3;

always @ (negedge clk or negedge reset)

if (reset == 0) state <= S0; else state <= nextstate;

always @ (state or in )

begin

out = 0;

case (state) //From the state diagram in the textbook, we can make the following cases-

S0: begin
if (in == 0) nextstate = S1;

else nextstate = S3;

end

S1: begin nextstate = S2;

end

S2: begin out = 1;

if (in == 0) nextstate = S1;

else nextstate = S3;

end

S3: begin out = 1; nextstate = S0;

end

endcase

end

endmodule

Verilog testbench-

module testmanchester();

reg in, clk, reset;

wire out;

reg [1: 0] state, nextstate;

NRZtoManchesterMooremachine NMM(.in(in),.clk(clk),.reset(reset),.out(out));

initial

begin

repeat (20)

begin
forever begin

clk = 0;

#10 clk = ~clk;

end

reset = 1;

in=$random;

#10;

end

end

endmodule

Problem 3:

If A=4’b1010, B=3’b010, C=3’b10x, D=4’b0101, E=2’b00, F=1’b1determine the following:

a. ~D = 4’b1010 (bitwise negation)

b. A&B = 3’b010 (bitwise and)

c. C|D = 4’b010x (bitwise or)

d. C&D = 3’b10x (bitwise and)

e. A^D = 4’b1111 (bitwise xor)

f. A~^B = 3’b111 (bitwise xnor)

g. &D = 1’b0 (Reduction and)

h. ~&B = 1’b1 (Reduction nand)

i. |A = 1’b1 (Reduction or)

j.~|D = 1’b0 (Reduction nor)

k. ^E = 1’b0 (Reduction xor)


l. A>>2 = 4’b0010 (Right shift by 2 bits)

m. E<<1 = 2’b00 (Left shift by 1 bit)

n. B*E = 2*0 = 0 = 1’b0 (Arithmetic multiplication)

o. D/B = 5/2 = 2 = 4’b0010 (Arithmetic division)

p. A+B = 10 + 2 = 12 = 4’b1100 (Arithmetic addition)

q. A-D = 10 – 5 = 5 = 4’b0101 (Arithmetic subtraction)

r. D%B = 5 % 2 = 1 = 4’b0001 (Arithmetic modulus)

s. !A = !(1010) = !(10) = !(logic 1) = 1’b0 (Logical negation)

t. !F = !(1) = !(logic 1) = 1’b0 = (Logical negation)

u. F && C = 3’b10x (Logical and)

v. A || B = 1’b1 (Logical or)

w. D>A = 5 > 10 = False = 1’b0 (Greater than)

x. B<A = 2 < 10 = True = 1’b1 (Less than)

y. B>=A = 2 >= 10 = False = 1’b0 (Greater than or equal to)

z. B<=A = 2 <= 10 = True = 1’b1 (Less than or equal to)

aa. {F,E} = 3’b100 (Concatenation)

bb. {3{B}} = 9’b010010010 (Concatenation)

cc. F ? A: B = 4’b1010 (Condition; value if true since F = 1)

dd. B==D 1’b0 (Equality)

ee. D!=E = 1’b1 (Inequality)

ff. C===D = 1’b0 (Case equality)

Problem 4:

Verilog code-
module comp (A,B,a_gt_b,a_lt_b,a_eq_b);

input [7:0] A,B;

output reg a_gt_b,a_lt_b,a_eq_b;

always @(A,B)

begin

a_eq_b = (A==B)?1'b1:1'b0; //conditional statement for equality

a_gt_b = (A>B)?1'b1:1'b0; //conditional statement for greater than

a_lt_b = (A<B)?1'b1:1'b0; //conditional statement for less than

end

endmodule

Verilog testbench-

module test_comp();

reg [7:0] A,B; //vector for 7 random input values

wire a_gt_b,a_lt_b,a_eq_b;

comp c1 (.A(A),.B(B),.a_gt_b(a_gt_b),.a_lt_b(a_lt_b),.a_eq_b(a_eq_b));

initial

begin

repeat(15)

begin

A=$random; //generate a random binary sequence

B=$random;

#10;

end

end
endmodule

Simulation waveform-

The simulation proved the equality, greater than and less than.

Problem 5:

We can infer from the code that,

If a = 1, => d = a+ c ------- (1) [‘+’ meaning or]

If b = 1, => d = b .c --------(2) [‘.’ Meaning and]

Else, d = 0
Explanation of the last output pattern in the figure,

1. a=1 => d = a+ c = 1 + 1 = 1 [since (1)]


2. a = 0, b = 0 => d = 0 [since (3)]
3. a = 0, b = 1 => d = b . c = 1 . 1 = 1 [since (2)]
4. a = 0, b = 1 => d = b. c = 1 . 0 = 0 [since (2)]
5. a = 0, b = 1 => d = b . c = 1 . 1 = 1 [since (2)]
6. a=1 => d = a + c = 1 + 1 = 1 [since (1)]
7. a=1 => d = a + c = 1 + 0 = 1 [since (1)]
8. a=1 => d = a + c = 1 + 1 = 1 [since (1)]
9. a = 0, b = 1 => d = b . c = 1 . 1 = 1 [since (2)]
10. a = 0, b = 0 => d = 0 [since (3)]

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