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R6551 Asynchronous Communication Interface Adapter DataSheet Jan1981

Rockwell 6551 ACIA datasheet

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214 views5 pages

R6551 Asynchronous Communication Interface Adapter DataSheet Jan1981

Rockwell 6551 ACIA datasheet

Uploaded by

weirdocolector
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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CO) ie PART NUMBER R6551 R6500 Microcomputer System DATA SHEET Asynchronous Communication Interface Adapter (ACIA) ‘The S51 Atynctvonout Communication Interface Adgoter IACIA) provides a programcontrolled interface be Wim ots on-chip baud cate generator, the RSET is capable of wansmittig at 15. cifferent progamssectoble rates between 50 baud and 18,200 baud, and receiving et either the transmit fate or at 16 times an external clock rate. The RESST har pro frammable word lengths of 8,6, 7, of B bits: even, odd oF no parity: 1, 1-172 oF 2stop bis Win the RESET, a crystal i the onty required external support component — eliminating the multple-component support that In adation, the A551 imum programmed register permit the CPU, modes and check dat, esigned for Ordering Information Order Package ‘Temperature Number Type Frequaney Range Resse Pane vas 0c 10 +70% RGSSIAP Platte «2M 0°C 19 +70%C AGSSIC Ceramic TMH 0°C 10 +70%C RESSIAC — Cerame == 2M 0°C 10 +70°C FEATURES © Compatible with Bit microprocessors 1 Full duplex or half plex operation with bitfered receiver nd tranamiter le Grud Rates (50 to 19.200) fe word lengths, number of 0p bits, and parity and detection Program sblectabie seri! echo mode Twa chip selacte 2 MH or 1 ME clock ate Single +5 45% power supoly 28-pi patie or ceramic OIF Full TTL compatioity v007 } ene contrat | [* biel INTERRUPT po RO <+— | tocie REGISTERS —|— [ee] [72 eae ae osm See | Pee me 2 Steno PS, a [eee RES ——wy | Locic ‘COMMAND: orn = aay Ea ROSSI Interface Diagram ‘Document Na, 28000 083 Rew. Jenuery 1989 (wD) 4exdepy eoejsezu) uonedUNWIWOD snouosyoUASY INTERNAL ORGANIZATION Control Register ‘The Control Register selects the desired boud rat, frequency source, word length, and the numberof stop bit. Seelen =a 6551 Block Diagram ‘Teansmitter/Recsiver Bis 03 of tne Control Register select the divisor used to generate the Co ‘Transmitter/Recsiver Clock Circuits ‘Transmit and Receive Data Registers These registers ae used as temporary data storage forthe 6551 Trans: iit and Receive cveults. The Transmit Data Register i charcterzed 1 10 is te leading bit to be transmited, 1 Unuied dota bits are the high-order bite and ar ‘The Receive Dato Register Ie characterizedin a similar fashion: © 812 0:6 the leading bit ceived (© Unused dats bits ave the high-order bits and are “O" for the 1 Parity bis are not contained inthe Receive Data Register, but Sf Mrippediott alter being used for external parity checking. ‘and all unused high-order bite are "0" RESEI Control Register Command Register ‘The Command Register controls specie modes and functions. R6551 Command Register Status Register ‘The Status Register reports the status of various SSI funetions dace RG5S1 Status Register INTERFACE SIGNAL DESCRIPTION During system initialization & low on the HES input wl caus internal ‘egisers to be cleared (2 (input Clock) ‘The input clock isthe system 02 clock and is used to synchronize all ata transfers between the system microprocesior and the RES, IW (Resaywrited ‘The FI is gonerated by the microprocesior and is used to control the diection of data transfers. A high on the RUW pin allows the proc: for to read the data supplied by the FG5SI. A low on the RI pin Sllows awrite to the RGSS TRG Unterrupe Request) ‘The TF pin is an intétrupt output from the interrupt contol loge is an open desin output, permitting several devices to be connected to the common TAO microprocessor input. Normally 2 high level TRG goes tow when an interrupt occurs 00.07 (Date Bus ‘The 00.07 pins ore the eight data lines used to transfer data Between tne procestor and the RGSEI. There lines are Dicirectional and are normally highimpedonce, exeept during Reed cycles when the RGSS} Feselectes €50, E54 (Chip Salcts) ‘The two chip slect inputs are normally connected to the procesor ‘address ines either directly or through decoders The RGSBI it welected when C50 is high ang CST i fom, ‘ASO, RSI (Register Salects) registers. The following table indicates the internal register select coaing Ast SO. Weiee Reed ° ° “Transmit Data Receiver Data Register Regeter ° 1 Programmed ‘Status Regier ove (Data ‘Don't Cove"? 1 ° Commend Register 1 1 Contr! Ragiater Note that only the Command and Control registers are readwrite ‘The Programmed Reset operstion does not cause any data transfer, but if used to clear Bis 0 through 4 inthe Command Register and Bit 2 In the Status Register. The Programmed Reset i sightlyeilferent from the Hardware Reset ES); these siferencs are described inthe individual epster definitions. ACIA/Modem Interface Signal Description XTLI,XTLO (Crystal Pins) ‘These pins are normally directly connected to the external crystal (1.8432 MMe} uted to derive the various baud rates, Alternatively, an externally generated clock may be used to drive the XTLI pin, lich ease the XTLO pin must fost. XTLI i the input pin for the transmit clock, ‘TxD (Transit Data) ‘The TxD output line it used to transter serial NAZ (non-return: zero) data to the modem. The LSB (iss significant bit) ofthe Trans mit Data Register isthe frst data bit tansmitted and the rate of date transmission is determined by the baud rate selected, or under control fof an external clack (as seleted by the Control Register AD (Receive Data) “The RxD input line is used to tranter serial NAZ data into the ACIA from the modem, LSB first, The receiver data rate iether the pe ‘rammed baud rate or the rate of an externally generated receiver lock (as selected by the Conteo! Register). xc (Receive Clock! The RxC is 2 bictvections pin which serves ab either the reciver 16x clock input or the racewer 16x clock output. The latter mode results ‘tne internal baud rate generator is elected for receiver data clocking ‘ATS (Request to Send) ‘The ATS outout pin is uted to conta! the macem trom the procesior. ‘The state of the ATS pin is determined by the contents of the Com EFS (clear to Send) ‘The ETS input pin is sed to control ine wrankmutter operation. The enable state ie wth CTS low. The transmitter is automatically ds bled t CTS han {BBR (Data Set Ready) ‘The OBR input pin i used to incheate to the RESS the statue of ‘modern. A low indicates the “ready state and a high, “not ready™ [O5R is» highmpedance input, end must be connected. It unuied, shouldbe driven high or low, But mot switched (EB (Data Currier Detsct) ‘The OED input pin it wad to inceate tothe RESS the satu of the

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