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Timing Check Tasks

Timing check tasks verify timing properties of designs by checking for timing violations like setup violations and hold violations. They record the occurrence times of critical events, compare the elapsed time to a specified limit, and report any violations. Common timing checks include $setup, $hold, $setuphold, $recovery, $removal, $recrem, $skew, $period, $width, and $random.

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Shivaksh Sharma
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100 views26 pages

Timing Check Tasks

Timing check tasks verify timing properties of designs by checking for timing violations like setup violations and hold violations. They record the occurrence times of critical events, compare the elapsed time to a specified limit, and report any violations. Common timing checks include $setup, $hold, $setuphold, $recovery, $removal, $recrem, $skew, $period, $width, and $random.

Uploaded by

Shivaksh Sharma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Timing check tasks

Outline
❑What are timing check tasks?

❑Importance and uses

❑timing check tasks

❑$random
Timing check statements
• Verilog has certain constructs to perform common
timing checks.

• Timing Check Tasks are for verification of timing


properties of designs and for reporting timing
violations.
Example: setup violation , hold violation etc.

• System timing checks only be used in specify blocks.


• All timing check begins with $ sign they are not
categorized as system tasks.

• No system task is allowed inside specify block.

• Timing check performs the following operations.

• Records occurrence time of a data or reference event.

• Waits for occurrence second data or reference event.

• Compares the elapsed time to the specified limit.

• Reports violation in design if any.


Timing check tasks are invoked every time critical events occur
within given time limits. See the table below with descriptions of
all arguments:

Argument Description Type


Reference_event The transition at a Module input or inout
control signal that that is scalar or vector
establishes the reference net
time for tracking timing
violations on the
data_event
Data_event The signal change that Module input or inout
initiates the timing check that is scalar or vector net
and is monitored for
violations.
Limit A time limit used to detect Constant expression or
timing violations on the specparam
data_event
Verilog supports following timing checks:

$setup $recovery
$hold $removal
$setuphold $recrem

$skew
$width
$timeskew
$period
$fullskew
$nochange
$setup
• $setup checks setup time violations.
• Syntax:
$setup (data_event, reference_event, limit);

(time of reference event) - (time of data event) < limit

• Data event is a data signal.


• Reference event is a clock signal.
• Limit is setup time.
module setup (din, clk, q);
input din, clk;
output q;

always @ (posedge clk)


q<=din;

specify
specparam tsetup = 7, delay = 10 ;
(data1 => q) = delay ;
$setup(din, posedge clk, tsetup);
endspecify

endmodule
$hold
• $hold checks hold time violations.
• Syntax:
$hold (reference_event, data_event, limit );
(time of data event) - (time of reference event) < limit

• Data event is a data signal.


• Reference event is a clock signal.
• Limit is hold time.
module hold1 (din, clk, q);
input din, clk;
output q;

always @ (posedge clk)


q<=din;

specify
specparam thold = 7, delay = 10 ;
(din => q) = delay ;
$hold(posedge clk, din, thold);
endspecify

endmodule
$setuphold
Syntax:
$setuphold (reference_event, data_event, setup_limit, hold_limit );

module hold1 (din, clk, q);


input din, clk;
output q;

always @ (posedge clk)


q<=din;

specify
specparam tsetup=6, thold = 7, delay = 10 ;
(din => q) = delay ;
$setuphold(posedge clk, din,tsetup, thold);
endspecify

endmodule
$recovery
• $recovery checks the violations for control signals
like clear, reset, set etc.

• Syntax:
$recovery(reference_event, data_event, limit);

– Reference event is a control signal like clear, reset, or


set.
– data event is a usually a clock signal
module recovery (in1, out1);
input in1 ;
output out1 ;

assign out1 = in1 ? 1'b1 : 1'bz ;

specify
specparam trecovery = 10;
$recovery ( posedge in1, out1, trecovery);
endspecify

endmodule
rst

CLK

$recovery ( posedge clear, posedge clk, 3);


$removal
• $removal checks the violations for control signals like
clear, reset, set etc.

Syntax:
$removal (reference_event, data_event, limit);

– Reference event is a control signal like clear, reset,


or set.
– data event is a usually a clock signal
module dff (din, clr, dout, clk);
input din, clk, clr;
output reg dout;

always @ (posedge clk, posdege clr)


if (clr) dout<=0 else dout<=din;

specify
$removal (negdge clr, posedge clk, 3)
endspecify

endmodule
CLK

rst

$removal (posedge clear, posedge clk, 3);


$recrem
Syntax:
$recrem (reference_event, data_event, recovery_limit, removal_limit);

module dff (din, clr, dout, clk);


input din, clk, clr;
output reg dout;

always @ (posedge clk, posdege clr)


if (clr) dout<=0 else dout<=din;

specify
$recrem(posedge clr, posedge clk , 2,3);
endspecify
endmodule
$skew
• Skew is the time delta between the actual and
expected arrival time of a signal.

• It checks that skew is not more than the specified limit


with respect to a signal.

Syntax:
$skew(reference_event, data_event, limit);
CLK

CLK
$period
• It checks whether reference signal time period
less than timing check limit.

Syntax:
$period (reference_event , limit);

– reference event is edge triggered event on a signal

– limit is time period of the signal.


$period (posedge clk, 10);

12 8 10 11
$width
• It checks whether reference signal has width less than
the specified timing check limit.

Syntax:
$width (reference_event, limit);

– reference event is edge triggered event on a signal.

– limit is pulse width value.


$width (posedge clk, 5);

5 3 5 4
Random Number Generator
• Random numbers are used for providing random test inputs
which helps in finding hidden bugs in the design.

• $random system task is used to generate random numbers


Syntax :
$random[(seed_value)];

• Seed value is used to ensure that same random number


sequence is generated each time it runs. Seed parameter can
be a reg, integer, or time.

• $random returns 32 bit signed integer.


Module abc;
integer seq1, seq2, seq3, seq4, seq5, s1, s2;
always
begin
seq1=$random;
seq2=$unsigned($random);
seq3=$random % 50;
seq4=$unsigned($random) % 100;
seq5={$random} % 35;
#10;
End
endmodule

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