Datapath subsystems

P Narashimaraja
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R.V.C.E

September, 2018

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Table of Contents

1. Review

2. Introduction

3. Addition
Single-bit addition
N-bit Adder
Carry-Ripple Adder
Manchester Carry Chain Adder
Carry-Skip Adder
Carry-Lookahead Adder
Carry-Select Adder

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Review

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Review of last session

Circuit Families:
Static CMOS
Ratioed logic
Cascode Voltage Switch logic (CVSL)
Dynamic logic
Pass transistor logic

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Introduction

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Introduction
Chip functions generally can be divided into the following categories:
Datapath operators
Memory elements
Control structures
Special-purpose cells
I/O
Power distribution
Clock generation and distribution
Analog and RF

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Addition

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Addition
Single-bit addition

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Single-bit addition

Half adder
Full adder

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Single-bit addition: Half Adder

Inputs Outputs
A B Cout S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

Table: Truth table for Half Adder

From the truth table, the half adder logic is

A`B
S
Cout  A  B
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Single-bit addition: Full Adder

Inputs Int. sig. Outputs

A B Cin G P K Cout S
0 0 0
0 0 0 0 1
1 0 1

0 1
0
0 1 0
0 1 S AB C ABC A BC ABC
1 1 0  pA ` B q ` C  P ` C
0 0 1 Cout  AB AC BC
1 0 0 1 0
1 1 0  MAJpA, B, C q
0 1 0
1 1 1 0 0
1 1 1
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Single-bit addition: Full Adder

Implementation from boolean expression:
A A B B C C

A A

B
B B
A
B S
C C C
A B B
S
A C C 32 transistors:
MAJ

C A
B Cout 6 for inverters,
C B Cout
B B 10 for majority gate,
C A
and
16 for XOR3
A B B
A A

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Mirror Adder: S  ABC pA B C qCout

MINORITY

Cout
S
uses only 28
transistors

Cout

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 A

Signals related to Cin

Propagate (P) Cout
S

Kill (K)
Generate (G)

Cout
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Propagate signal
From the table, it is clear that we need a circuit, that propagates Cin to Cout
when A  B.
A A1 A0

B B 0 B 0

C C C
Cout Cout  Cin Cout

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Kill/Generate signal
From truth table, Cout  1 (or) 0 when A  B  1 (or) A  B  0 irrespective
of Cin
A0 A1

B 0 B 1

Cout 1 Cout 0

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PGK
Eg. A  B 0
A0 A0

B 0 B 0

C 1 C 0
Cout 1 Cout 1

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Mirror adder
Inputs Outputs
A B Cin Cout S
0 0 0 0 0
0 0 1 0 1
When any one among 0 1 0 0 1
the 3 i/p.s is odd, 0 1 1 1 0
S  Cout 1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

Table: Truth table for Full Adder

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Mirror adder
When any one among the 3 i/p.s is odd, S  Cout
Let get the idea gained from the Propagate signal (Which allowed to propagate
when there is an odd among the 2 i/p.s)

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 A  0, B C1 AB C1
A A0 A1

B B 1 B 1

C C 1 C 1

Cout Cout Cout

Cout S Cout S Cout S
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XOR gate
A brilliant XOR structure that combines Transmission gate and Pass transistors
B B 1 B 0
0
A A0 A0

P P 1 1
P 0 0

0 1 0

B 0 B 1
1
A1 A1

P 1 0
P 0 1

0 0

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Full adder using XORs and 2:1 MUXs

First let’s derive the Boolean expressions for S and Cout
Considering the inverted form of S and Cout

S  pA ` B ` C q  pP ` C q  P C PC

pC C q1
hkkkkkkkikkkkkkkj
Cout  looooooomooooooon
ABC ABC looooooomooooooon
ABC ABC
 AB pAB AB qC
 pAB AB qA pAB AB qC
 PA PC

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Full adder using XORs

A B C
A B
C

S P

P
0
S
1
P
0
Cout
Cout
1

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 B

CPL full adder A

B C
B C

B C
Cout
B C
S

A B C
B C

A B C
Cout
B C
S

B
A

B
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Addition
N-bit Adder

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Multi-bit addition
Carry-Propagate addition
PG Carry-Ripple Addition
Manchester Carry Chain Adder
based on Carry Generation
Carry-Skip Adder and Propagation
Carry-Lookahead Adder
Carry-Select Adder

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Carry propagate addition

Cout Cin Cout Cin

0 0 0 0 0 1 1 1 1 1 carries
1 1 1 1 1 1 1 1 A41
0 0 0 0 0 0 0 0 B41
1 1 1 1 0 0 0 0 S41

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For Adders: Carry Generation and Propagation

Based on the theory of P(propagate) and G(generate) signals from the full adder
Generalize a group spanning i    j, inclusive
Group generates a carry - if Cout is independent of Cin
Group propagates a carry - if Cout is dependent of Cin Group generates C if

Thus generalizing for i ¥ k ¡ j

- upper (more significant) or
- lower portion generates &
Gi:j  Gi:k Pi:k  Gk
1:j upper portion propagates that

Pi:j  Pi:k  Pk
1:j C

with the base case Group propagates C

 
Assume C0 Cin & CN
For bit 0:
Cout
Gi:i  Gi  Ai  Bi - if both the upper & lower

- Generate signal G0:0 Cin
Pi:i  Pi  Ai ` Bi portions propagate the C

- Propagate signal P0:0 0

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For Adders: Carry Generation and Propagation

Observation:
Carry into bit i is the carry-out of bit i–1, Ci,in  Ci
1,out
Ci
1  Gi
1:0
Thus sum for bit i based on S  pA ` B q ` C  P `C
Si  Pi ` Gi
1:0
Compute bitwise generate and propagate signals using
Gi:i  Gi  Ai  Bi G0:0  Cin
Pi:i  Pi  Ai ` Bi P0:0  0
Combine PG signals to determine group generates Gi
1:0 for all N ¥i¥1
using G G P Gi:j i:k i:k

k 1:j
 Pi:k  Pk
1:j
Pi:j
Calculate the sum using Si  Pi ` Gi
1:0
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Valency-2/Radix-2 group PG logic

Consider a 1-bit adder block:
G1:1 G1:0 P1  P1:1 G1  G1:1
P1:1
G0:0
p g
P1:1
G1:0 co P G1 ci G0:0
Gi:k Gi:j
Pi:k
Gk
1:j

i¥k ¡ j:
ð G1:0  G1:1 P1:1  G1
1:0
Gi:j  Gi:k Pi:k  Gk
1:j  G1:1 P1:1  G0:0

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Valency-3/Radix-3 group PG logic

G2:2 G2:0
P2:2 P2 G2 P1 G1
G1:1
P1:1
G0:0 p g p g
P2:2
G1:0
Gi:k G2:0 co P G2 ci co P G1 ci G0:0
Gi:j
Pi:k P1:1
Gk
1:l
P2:2  P1:1
Pk
1:l
Gl
1:j

i ¥k ¡ l ¡ j:
G2:0  G2:2 P2:2  G2
1:0
Gi:j  Gi:k Pi:k  Gk
1:m Pi:k  Pk
1:l  Gl
1:j  G2:2 P2:2  G1:1 P2:2  P1:1  G0:0

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Valency-4/Radix-4 group PG logic

P3 G3 P2 G2 P1 G1
Gi:k Gi:j
Pi:k
Gk
1:l p g p g p g
Pk
1:l G1:0
Gl
1:m G3:0 co P G3 ci co P G2 ci co P G1 ci G0:0
Pl
1:m G2:0
Gm
1:j

Gi:j  Gi:k Pi:k  Gk
1:l Pi:k  Pk
1:l  Gl
1:m Pi:k  Pk
1:l  Pl
1:m  Gm
1:j
 Gi:k Pi:k pGk
1:1 Pk
1:l pGl
1:m Pl
1:m  Gm
1:j qq
Pi:j  Pi:k  Pk
1:l  Pl
1:m  Pm
1:j

G3:0  G3:3 P3:3  G2:0

 G3:3 P3:3  G2:2 P3:3  P2:2  G1:1 P3:3  P2:2  P1:1  G0:0

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group PG logic - Review

Valency-2/Radix-2 group PG logic:i ¥ k ¡ j
Gi:j  Gi:k Pi:k  Gk
1:j G1:0  G1:1 P1:1  G1
1:0
Pi:j  Pi:k  Pk
1:j  G1:1 P1:1  G0:0
Higher-valency group logic - uses fewer stages of more complex gates
Let us built Valency-4 group PG logic:
Gi:j  Gi:k Pi:k  Gk
1:1 Pi:k  Pk
1:l  Gl
1:m Pi:k  Pk
1:l  Pl
1:m  Gm
1:j
 Gi:k Pi:k pGk
1:1 Pk
1:l pGl
1:m Pl
1:m  Gm
1:j qq
Pi:j  Pi:k  Pk
1:l  Pl
1:m  Pm
1:j

G3:0  G3:3 P3:3  G2:2 P3:3  P2:2  G1:1 P3:3  P2:2  P1:1  G0:0
G4:1  G4:4 P4:4  G3:3 P4:4  P3:3  G2:2 P4:4  P3:3  P2:2  G1:1
P4:1  P4:4  P3:3  P2:2  P1:1
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For Adders: Carry Generation and Propagation

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PG Carry-Ripple Addition
Implementation of Carry-Ripple adder
Use P & G to simplify the MAJ function into an AND-OR gate:

Ci  AiBi pAi BiqCi
1

 AiBi pAi ` BiqCi
1
 Gi PiCi
1
Since, Ci  Gi:0
Gi:0  Gi Pi Gi
1:0

Note: Group propagate signals are never used and need not be computed.

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4-bit carry-ripple adder using PG logic

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Group PG cells
Black cell Gray cell Buffer
i:k k
1:j i:k k
1:j
i:k

i:j i:j i:j

Gi:k Gi:j
Pi:k
Gk
1:j
Pi:j Pi:j
Gi:k Gi:j
Pi:j Pi:k
Pk
1:j Gk
1:j Gi:j Gi:j

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Radix-4 PG Black cell implementation

i:k k
1:l l
1:m m
1:j Gi:k Gi:j

Pi:k
Gk
1:l
Pk
1:l
Gl
1:m
Pl
1:m
Gm
1:j

Pi:j
i:j Pm
1:j

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Group PG cells

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Qualitative delay analysis: Carry-ripple adder group PG n/w

Bit position

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
The graph shows the delay
caused only by group Generate
logic.
Critical path delay:

tripple  tpg pN
1qtAO txor

where

Delay
tpg is the delay of 1-bit
propagate/generate gates
tAO is the delay of AND-OR
gate in the gray cell
txor is the delay of the final sum
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
XOR
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Manchester Carry Chain Adder

It is a chain of pass-transistors - implement the carry chain.
i.e., it replaces the MAJ circuit as in static CMOS implementation
There are versions: 1. Static version & 2. Dynamic version
Propagate Kill
P
A
K
Cin Cout
B
G
P
C
Cout
Cout

P
φ
Cin Cout
G

Propagate Generate
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Manchester carry chains

The computation of G3:0 can be expressed as

C1  g1 p1 C 0
C2  g2 p2 pg1 p 1 C0 q
C3  g3 p3 pg2 p2 pg1 p1 C0 qq

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Manchester carry chains

Using Dynamic logic:

P1 P2 P3
φ φ φ
C0 C1 C2 C3

G1 G2 G3

P1 P2 P3
φ φ φ φ 3 2 1 0
C3 pG3:0 q
C0 C1 C2

G0 G1 G2 G3

C0 pG0:0 q C1 pG1:0 q C2 pG2:0 q 3:0 2:0 1:0 0:0

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Manchester carry chain: valency-4 group Generate

.

3 2 1 0
Note: Under the assumption that the parasitic delay through
the chain is minimum, one could expect the group generate
signals (G3:0    G0:0 ) are produced simultaneously.
3:0 2:0 1:0 0:0
In reality, the parasitic delay grows in quadratic with the
length of the carry chain - resulting in tG3:0 ¡ tG1:0 .

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Bit position

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Delay
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

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Multiple-Output Domino Logic (MODL)

Using footed Dynamic logic:

φ
C3
φ p3 g3
C2
φ p2 g2 p2 g2
C1
p1 g1 p1 g1 p1 g1

c0 c0 c0

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Multiple-Output Domino Logic (MODL)

φ
C3
p3 g3
C2
p2 g2
C1
p1 g1

c0

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Exercise
(i). Develop equations for the logical effort and parasitic delay with respect to
the C0 input of an n-stage Manchester carry chain computing C1    Cn .
Consider all of the internal diffusion capacitances when deriving the parasitic
delay. Use the transistor widths shown in Figure and assume the Pi and Gi
1
transistors of each stage share a single diffusion contact.
P1 P2 Pn
φ 1 φ 1 φ 1
3 3 3 Cn pGn:0 q
C0 pG0 q 3 G1 3
2 G2 3
2 Gn 3 2
1 1
1
C1 pG1:0 q Cn
1 pGn
1:0 q

Figure: Manchester carry chain

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Solution

P1 P2 Pn
φ 1 φ 1 φ 1
3 3 3 Cn pGn:0 q
C0 pG0 q 3 G1 3
2 G2 3
2 Gn 3 2
1 1
1
C1 pG1:0 q Cn
1 pGn
1:0 q
P1 P2 Pn
Cn pGn:0 q

G0 3C p3 3 p3 3 1 2 1qC p3 3 1 2 1qC
1 2
1qC

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Solution
P1 P2 Pn
Cn pGn:0 q

G0 3C p3 3 p3 3 1 2 1qC p3 3 1 2 1qC
1 2
1qC

We know the normalized delay could be written as

dp gh
Where, h represents fanout. In this case, since each carry chain drives another
identical chain, h  1
p represents the parasitic delay. The output inverter has a parasitic delay of 3/3:
R
p3C q ° pi 1q R p10C q
n

p
3 3 i 1
3
3 3RC
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Solution
R
p3C q ° pi 1q R p10C q
n

p
3 3 i 1
3
3 3RC
From finite geometric series:
npn 1q
1 2 3  n
2
and if there are pn 1q terms, then

1 2 3  n pn 1q 
pn 1qpn 2q
2
Pulling the 1st term from LHS to RHS,
n2 2
2 3    pn 1q 
3n
2
2

1  n 2 3n
° pi 1q 10
n npn 3q 10

1  1
p 1
3 i 1
3 2 3
3 3 3
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Solution

10npn 3q
1 n2
p1 
6 n 4
10 30
3 24 24 3
Now the delay along the chain could be expressed as:

n2
dg p1
n 4
10 30
24 24 3

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Exercise
(ii). What Manchester carry chain length gives the least delay for a long adder?
The delay per bit scales as:
n2
d t u
1 n 7
10 5
n 24 4 3
Taking the derivative of delay w.r.t length of each chain n and setting that equal
to 0, ñ allows us to solve for the best chain length
Bd  10
7  0
B‘n 24 3n2
n  2.36
Because the parasitic capacitance is large, the best delay is achieved with short
carry chains.
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Carry-Skip Adder

The critical path involves the initial PG logic producing a carry out of bit 1, three
AND-OR gates rippling it to bit 4, three multiplexers bypassing it to C12, 3
AND-OR gates rippling through bit 15, and a final XOR to produce S16.
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Qualitative delay analysis: Carry-Skip Adder

Bit position
G1;1
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

critical path delay of group PG n/w

Delay
16:0 15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
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Qualitative delay analysis: Carry-Skip Adder

Let’s understand the delay by making use of 1st 6-bits.
Bit position
The Blue cell is meant for sum
5 4 3 2 1 0 computation.
i.e, for S1  P1:1 ` C0 , where C0 could
be directly feed. But for S2  P2:2 ` C1 ,
so the first blue cell generates
C1  G1:0  G1:1 P1:1  G0:0
Delay
(G0:0  C0 ). Thus the blue cells helps
to generate G1:0  C1 .
Note that the Gray cells are used to
compute G4:1 (which is  G4:0 )
5:0 4:0 3:0 2:0 1:0 0:0
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Qualitative delay analysis: Carry-Skip Adder

Let’s understand the delay by making use of 1st 6-bits.
Bit position

5 4 3 2 1 0 The 2:1 MUX output should produce

G4:0 , so that it acts as Cin p G4:0 q for
G2:1 the next group PG n/w composed b/w
5:8.
G3:1 Now, let’s try to understand...

Delay
G1:0 w.k, G4:0  G4:1 P4:1 G0:0
where, G0:0  Cin and the gray cells
G4:1
G2:0
G3:0 spanning b/w 4:1 provides us G4:1 .
G4:0

5:0 4:0 3:0 2:0 1:0 0:0

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Qualitative delay analysis: Carry-Skip Adder for variable group

size

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Carry-skip adder Manchester stage

A valency-5 chain is used to skip across groups of 4 bits at a time.

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Carry-Lookahead Adder

Similar to the carry-skip adder

Computes both group generate and group propagate signals
- to avoid waiting for a ripple to determine if the first group generates a carry
Using valency-4 black cells to compute 4-bit group PG signals

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Carry-Lookahead Adder
Using valency-4 black cells to compute 4-bit group PG signals

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Carry-Select Adder

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