Spartan-3E Libraries Guide

for HDL Designs

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About This Guide

Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate
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About this Guide

The Spartan™-3E Libraries Guide for HDL Designs is part of the ISE documentation
collection. A separate version of this guide is also available for users who prefer to
work with schematics in their circuit design activities. (See the Spartan™-3E Libraries
Guide for Schematic Designs.)

Guide Contents
This guide contains the following:
• Information about additional resources and conventions used in this guide.
• A general introduction to the Spartan-3E primitives.
• A listing of the primitives and macros that are supported by the Spartan-3E archi-
tecture, organized by functional categories.
• Individual sections for each of the primitive design elements, including VHDL
and Verilog instantiation and inference code examples.
• Referrals to additional sources of information.

Additional Resources
To find additional documentation, see the Xilinx website at:
http://www.xilinx.com/literature.
To search the Answer Database of silicon, software, and IP questions and answers, or
to create a technical support WebCase, see the Xilinx website at:
http://www.xilinx.com/support.

Conventions
This document uses the following conventions. An example illustrates each
convention.

Typographical
The following typographical conventions are used in this document:

Convention Meaning or Use Example

Courier font Messages, prompts, and program speed grade: - 100
files that the system displays
Courier bold Literal commands that you enter in ngdbuild design_name
a syntactical statement

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Convention Meaning or Use Example

Helvetica bold Commands that you select from a File →Open
menu
Keyboard shortcuts Ctrl+C
Italic font Variables in a syntax statement for ngdbuild design_name
which you must supply values
References to other manuals See the Development System
Reference Guide for more
information.
Emphasis in text If a wire is drawn so that it
overlaps the pin of a symbol,
the two nets are not connected.
Square brackets [ ] An optional entry or parameter. ngdbuild [option_name]
However, in bus specifications, design_name
such as bus[7:0], they are
required.
Braces { } A list of items from which you lowpwr ={on|off}
must choose one or more
Vertical bar | Separates items in a list of choices lowpwr ={on|off}
Vertical ellipsis Repetitive material that has been IOB #1: Name = QOUT’
. omitted IOB #2: Name = CLKIN’
. .
. .
.
Horizontal ellipsis . . . Repetitive material that has been allow block block_name loc1
omitted loc2 ... locn;

Online Document
The following conventions are used in this document:

Convention Meaning or Use Example

Blue text Cross-reference link to a location See the section “Additional
in the current document Resources” for details.
Red text Cross-reference link to a location See Figure 2-5 in the Virtex-4
in another document Handbook.
Blue, underlined text Hyperlink to a website (URL) Go to http://www.xilinx.com
for the latest speed files.

Introduction
This version of the Libraries Guide describes the primitive and macro design elements
that make up the Xilinx Unified Libraries and are supported by the Spartan-3E
architecture, and includes examples of instantiation and inference code for each
primitive.
Xilinx maintains software libraries with hundreds of functional design elements
(primitives and macros) for a variety of device architectures. New functional elements
are assembled with each release of development system software. In addition to a
comprehensive, unified library containing all design elements, beginning in 2004,
Xilinx developed a separate library for each architecture. This Spartan-3E guide is one
in a series of architecture-specific libraries.

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This guide describes the primitive elements available for Xilinx Spartan-3E FPGA
devices. Common logic functions can be implemented with these elements and more
complex functions can be built by combining macros and primitives.

Functional Categories
The functional categories list the available design elements in each category, along
with a brief description of each element that is supported under each Xilinx
architecture.

Attributes and Constraints

The terms attribute and constraint have been used interchangeably by some in the
engineering community, while others ascribe different meanings to these terms. In
addition, language constructs use the terms attribute and directive in similar yet
different senses. For the purpose of clarification, the following distinction can be
drawn between these terms.
An attribute is a property associated with a device architecture primitive that affects
an instantiated primitive’s functionality or implementation. Attributes are typically
conveyed as follows:
• In VHDL, by means of generic maps.
• In Verilog, by means of defparams or inline parameter passing during the
instantiation process.
Constraints impose user-defined parameters on the operation of ISE tools. There are
two types of constraints:
• Synthesis Constraints direct the synthesis tool optimization technique for a
particular design or piece of HDL code. They are either embedded within the
VHDL or Verilog code, or within a separate synthesis constraints file.
• Implementation Constraints are instructions given to the FPGA implementation
tools to direct the mapping, placement, timing, or other guidelines for the
implementation tools to follow while processing an FPGA design.
Implementation constraints are generally placed in the UCF file, but can exist in
the HDL code, or in a synthesis constraints file.
Attributes are identified with the components to which they apply in the libraries
guide for those components. Constraints are documented in the Xilinx Constraints
Guide. Both resources are available from the Xilinx Software Manuals collection.

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Table of Contents
About this Guide
Guide Contents ............................................................................................................................ 3
Additional Resources ................................................................................................................ 3
Conventions .................................................................................................................................. 3
Introduction .................................................................................................................................. 4
Functional Categories ................................................................................................................ 5
Attributes and Constraints ...................................................................................................... 5
Functional Categories
Arithmetic Functions ................................................................................................................. 9
Clock Components ..................................................................................................................... 9
Config/BSCAN Components .................................................................................................. 9
I/O Components .......................................................................................................................... 9
RAM/ROM .................................................................................................................................. 10
Registers & Latches .................................................................................................................. 10
Shift Registers ............................................................................................................................ 10
Slice/CLB Primitives ................................................................................................................ 10
About the Spartan-3E Design Elements
BSCAN_SPARTAN3 ................................................................................................................ 15
BUFG ............................................................................................................................................. 17
BUFGCE ....................................................................................................................................... 19
BUFGCE_1 ................................................................................................................................... 21
BUFGMUX .................................................................................................................................. 23
BUFGMUX_1 .............................................................................................................................. 25
CAPTURE_SPARTAN3 ........................................................................................................... 27
DCM_SP ....................................................................................................................................... 29
FDCPE ........................................................................................................................................... 35
FDRSE ........................................................................................................................................... 37
IBUF ............................................................................................................................................... 39
IBUFDS ......................................................................................................................................... 41
IBUFG ............................................................................................................................................ 43
IBUFGDS ..................................................................................................................................... 45
IDDR2 ........................................................................................................................................... 47
IOBUF ............................................................................................................................................ 49
IOBUFDS ..................................................................................................................................... 51
KEEPER ........................................................................................................................................ 53
LDCPE ........................................................................................................................................... 55
LUT1, 2, 3, 4 ................................................................................................................................. 57
LUT1_D, LUT2_D, LUT3_D, LUT4_D ............................................................................... 63
LUT1_L, LUT2_L, LUT3_L, LUT4_L ................................................................................... 69
MULT_AND ................................................................................................................................ 75
MULT18X18SIO ......................................................................................................................... 77
MUXCY ......................................................................................................................................... 79
MUXCY_D ................................................................................................................................... 81
MUXCY_L .................................................................................................................................... 83
MUXF5 .......................................................................................................................................... 85
MUXF5_D .................................................................................................................................... 87
MUXF5_L ..................................................................................................................................... 89
MUXF6 .......................................................................................................................................... 91
MUXF6_D .................................................................................................................................... 93
MUXF6_L ..................................................................................................................................... 95
MUXF7 .......................................................................................................................................... 97
MUXF7_D .................................................................................................................................... 99

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MUXF7_L ................................................................................................................................... 101

MUXF8 ........................................................................................................................................ 103
MUXF8_D .................................................................................................................................. 105
MUXF8_L ................................................................................................................................... 107
OBUF ........................................................................................................................................... 109
OBUFDS ..................................................................................................................................... 111
OBUFT ........................................................................................................................................ 113
OBUFTDS .................................................................................................................................. 115
ODDR2 ....................................................................................................................................... 117
PULLDOWN ............................................................................................................................. 119
PULLUP ...................................................................................................................................... 121
RAM16X1D ............................................................................................................................... 123
RAM16X1S ................................................................................................................................ 127
RAM32X1D ............................................................................................................................... 129
RAM32X1S ................................................................................................................................ 133
RAM64X1S ................................................................................................................................ 135
RAM128X1S .............................................................................................................................. 137
RAMB16_Sm_Sn ..................................................................................................................... 139
RAMB16_Sn .............................................................................................................................. 151
ROM16X1 ................................................................................................................................... 155
ROM32X1 ................................................................................................................................... 157
ROM64X1 ................................................................................................................................... 159
ROM128X1 ................................................................................................................................. 161
ROM256X1 ................................................................................................................................. 163
SRLC16E ..................................................................................................................................... 165
STARTUP_SPARTAN3E ....................................................................................................... 167
XORCY ........................................................................................................................................ 169
XORCY_D .................................................................................................................................. 171
XORCY_L ................................................................................................................................... 173

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Arithmetic Functions

Functional Categories
This section categorizes, by function, the Spartan-3E design elements described in
detail later in this guide. The elements (primitive and macro implementations) are
listed in alphanumeric order under each of the following functional categories:
Arithmetic Functions I/O Components Shift Registers
Clock Components RAM/ROM Slice/CLB Primitives
Config/BSCAN Components Registers & Latches

Arithmetic Functions
Design Element Description

MULT18X18SIO Primitive: 18x18 Cascadable Signed Multiplier with Optional Input and Output registers, Clock Enable, and Synchronous Reset

Clock Components
Design Element Description

BUFG Primitive : Global Clock Buffer

BUFGCE Primitive : Global Clock with Clock Enable
BUFGCE_1 Primitive : Global Clock Buffer with Clock Enable and Output State 1
BUFGMUX Primitive : Global Clock MUX Buffer
BUFGMUX_1 Primitive : Global Clock MUX Buffer with Output State 1
DCM_SP Primitive: Digital Clock Manager

Config/BSCAN Components
Design Element Description

BSCAN_SPARTAN3 Primitive: Spartan-3 Boundary Scan Logic Control Circuit

CAPTURE_SPARTAN3 Primitive: Spartan-3 Register State Capture for Bitstream Readback
STARTUP_SPARTAN3E Primitive : Spartan-3E User Interface to the GSR, GTS, Configuration Startup Sequence and Multi-Boot Trigger Circuitry

I/O Components
Design Element Description

IBUF Primitive : Single-Ended Input Buffer with Selectable I/O Standard

IBUFDS Primitive : Differential Signaling Input Buffer with Selectable I/O Interface
IBUFG Primitive : Dedicated Input Buffer with Selectable I/O Interface
IBUFGDS Primitive : Dedicated Differential Signaling Input Buffer with Selectable I/O Interface
IDDR2 Primitive: Dual Data Rate Input D Flip-Flop with Optional Data Alignment, Clock Enable and Programmable Synchronous or
Asynchronous Set/Reset

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RAM/ROM

Design Element Description

OBUF Primitive: Single- Ended Output Buffer

ODDR2 Primitive: Dual Data Rate Output D Flip-Flop with Optional Data Alignment, Clock Enable and Programmable Synchronous or
Asynchronous Set/Reset
IOBUF Primitive : bidirectional Buffer with Selectable I/O Interface with Active Low Output Enable
IOBUFDS Primitive : 3-State Differential Signaling I/O Buffer with Active Low Output Enable and with Selectable I/O Interface
KEEPER Primitive : KEEPER Symbol
OBUFDS Primitive : Differential Signaling Output Buffer with Selectable I/O Interface
OBUFT Primitive: 3-State Output Buffer with Active Low Output Enable and with Selectable I/O Interface
OBUFTDS Primitive : 3-State Output Buffer with Differential Signaling, Active-Low Output Enable, and Selectable I/O Interface
PULLDOWN Primitive : Resistor to GND for Input Pads
PULLUP Primitive : Resistor to VCC for Input PADs, Open-Drain, and 3-State Outputs

RAM/ROM
Design Element Description

RAM16X1D Primitive : 16-Deep by 1-Wide Static Dual Port Synchronous RAM

RAM16X1S Primitive : 16-Deep by 1-Wide Static Synchronous RAM
RAM32X1D Primitive : 32-Deep by 1-Wide Static Dual Static Port Synchronous RAM
RAM32X1S Primitive: 32-Deep by 1-Wide Static Synchronous RAM
RAM64X1S Primitive: 64-Deep by 1-Wide Static Synchronous RAM
RAM128X1S Primitive : 128-Deep by 1-Wide Static Synchronous RAM
RAMB16_Sm_Sn Primitive : 16384-Bit Data Memory and 2048-Bit Parity Memory, Dual-Port Synchronous Block RAM with Port Width (m or n)
Configured to 1, 2, 4, 9, 18, or 36 Bits
RAMB16_Sn Primitive : 16384-Bit Data Memory and 2048-Bit Parity Memory, Single-Port Synchronous Block RAM with Port Width (n)
Configured to 1, 2, 4, 9, 18, or 36 Bits
ROM16X1 Primitive: 16-Deep by 1-Wide ROM
ROM32X1 Primitive: 32-Deep by 1-Wide ROM
ROM64X1 Primitive: 64-Deep by 1-Wide ROM
ROM128X1 Primitive: 128-Deep by 1-Wide ROM
ROM256X1 Primitive: 256-Deep by 1-Wide ROM

Registers & Latches

Design Element Description

FDCPE Primitive : D Flip-Flop with Clock Enable and Asynchronous Preset and Clear
FDRSE Primitive : D Flip-Flop with Synchronous Reset and Set and Clock Enable
LDCPE Primitive : Transparent Data Latch with Asynchronous Clear and Preset and Gate Enable

Shift Registers
Design Element Description

SRLC16E Primitive : 16-Bit Shift Register Look-Up-Table (LUT) with Carry and Clock Enable

Slice/CLB Primitives
Design Element Description

LUT1 Primitive : 1-Bit Look-Up-Table with General Output

LUT2 Primitive : 2-Bit Look-Up-Table with General Output

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Slice/CLB Primitives

Design Element Description

LUT3 Primitive : 3-Bit Look-Up-Table with General Output

LUT4 Primitive : 4-Bit Look-Up-Table with General Output
LUT1_D Primitive : 1-Bit Look-Up-Table with Dual Output
LUT2_D Primitive : 2-Bit Look-Up-Table with Dual Output
LUT3_D Primitive : 3-Bit Look-Up-Table with Dual Output
LUT4_D Primitive : 4-Bit Look-Up-Table with Dual Output
LUT1_L Primitive : 1-Bit Look-Up-Table with Local Output
LUT2_L Primitive : 2-Bit Look-Up-Table with Local Output
LUT3_L Primitive : 3-Bit Look-Up-Table with Local Output
LUT4_L Primitive : 4-Bit Look-Up-Table with Local Output
MULT_AND Primitive : Fast Multiplier AND
MUXCY Primitive : 2-to-1 Multiplexer for Carry Logic with General Output
MUXCY_D Primitive : 2-to-1 Multiplexer for Carry Logic with Dual Output
MUXCY_L Primitive : 2-to-1 Multiplexer for Carry Logic with Local Output
MUXF5 Primitive : 2-to-1 Look-Up Table Multiplexer with General Output
MUXF5_D Primitive : 2-to-1 Look-Up Table Multiplexer with Dual Output
MUXF5_L Primitive : 2-to-1 Look-Up Table Multiplexer with Local Output
MUXF6 Primitive : 2-to-1 Look-Up Table Multiplexer with General Output
MUXF6_D Primitive : 2-to-1 Look-Up Table Multiplexer with Dual Output
MUXF6_L Primitive : 2-to-1 Look-Up Table Multiplexer with Local Output
MUXF7 Primitive : 2-to-1 Look-Up Table Multiplexer with General Output
MUXF7_D Primitive : 2-to-1 Look-Up Table Multiplexer with Dual Output
MUXF7_L Primitive : 2-to-1 Look-Up Table Multiplexer with Local Output
MUXF8 Primitive : 2-to-1 Look-Up Table Multiplexer with General Output
MUXF8_D Primitive : 2-to-1 Look-Up Table Multiplexer with Dual Output
MUXF8_L Primitive : 2-to-1 Look-Up Table Multiplexer with Local Output
XORCY Primitive : XOR for Carry Logic with General Output
XORCY_D Primitive : XOR for Carry Logic with Dual Output
XORCY_L Primitive : XOR for Carry Logic with Local Output

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Slice/CLB Primitives

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About the Spartan-3E Design Elements

The remaining sections in this guide describe each primitive design element that can
be used under the Spartan-3E architecture.
The design elements are organized in alphanumeric order, with all numeric suffixes in
ascending order. For example, FDCPE precedes FDRSE, and IBUF precedes IBUFDS.
The following information is provided for each library element, where applicable:
• Name of each element.
• Description of each element, including truth tables, where applicable.
• A description of the attributes associated with each design element, where
appropriate.
• Examples of VHDL and Verilog instantiation and inference code, where
applicable.
• Referrals to additional sources of information.
Designers who prefer to work with schematics are encouraged to consult the Spartan-
3E Libraries Guide for Schematic Designs.

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BSCAN_SPARTAN3

BSCAN_SPARTAN3
Primitive: Spartan-3 Boundary Scan Logic Control Circuit

BSCAN_SPARTAN3 provides access to the BSCAN sites on a Spartan-3E device. It

BSCAN_SPARTAN3 creates internal boundary scan chains. The 4-pin JTAG interface (TDI, TDO, TCK, and
UPDATE TMS) consists of dedicated pins in Spartan-3E devices. To use normal JTAG for
SHIFT
RESET
boundary scan purposes, hook up the JTAG pins to the port and go. The pins on the
TDI
BSCAN_SPARTAN3 symbol do not need to be connected, unless those special
SEL1
DRCK1 functions are needed to drive an internal scan chain.
TDO1 SEL2
TDO2 DRCK2 A signal on the TDO1 input is passed to the external TDO output when the USER1
CAPTURE
instruction is executed; the SEL1 output goes High to indicate that the USER1
X10183
instruction is active.The DRCK1 output provides USER1 access to the data register
clock (generated by the TAP controller). The TDO2 and SEL2 pins perform a similar
function for the USER2 instruction and the DRCK2 output provides USER2 access to
the data register clock (generated by the TAP controller). The RESET, UPDATE,
SHIFT, and CAPTURE pins represent the decoding of the corresponding state of the
boundary scan internal state machine. The TDI pin provides access to the TDI signal
of the JTAG port in order to shift data into an internal scan chain.

Usage
This design element is instantiated, rather than inferred.

VHDL Instantiation Template

-- BSCAN_SPARTAN3 : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (BSCAN_SPARTAN3_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : connect this function to the design. Delete or comment
-- : out inputs/outs that are not necessary.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- BSCAN_SPARTAN3: Boundary Scan primitive for connecting internal logic to

-- JTAG interface. Spartan-3
-- Xilinx HDL Libraries Guide version 8.1i

BSCAN_SPARTAN3_inst : BSCAN_SPARTAN3
port map (
CAPTURE => CAPTURE, -- CAPTURE output from TAP controller
DRCK1 => DRCK1, -- Data register output for USER1 functions
DRCK2 => DRCK2, -- Data register output for USER2 functions
RESET => RESET, -- Reset output from TAP controller
SEL1 => SEL1, -- USER1 active output
SEL2 => SEL2, -- USER2 active output
SHIFT => SHIFT, -- SHIFT output from TAP controller
TDI => TDI, -- TDI output from TAP controller
UPDATE => UPDATE, -- UPDATE output from TAP controller
TDO1 => TDO1, -- Data input for USER1 function

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BSCAN_SPARTAN3

TDO2 => TDO2 -- Data input for USER2 function

);

-- End of BSCAN_SPARTAN3_inst instantiation

Verilog Instantiation Template

// BSCAN_SPARTAN3 : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (BSCAN_SPARTAN3_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. Delete or comment
// : out inputs/outs that are not necessary.

// <-----Cut code below this line---->

// BSCAN_SPARTAN3: Boundary Scan primitive for connecting internal logic to

// JTAG interface. Spartan-3/3E
// Xilinx HDL Libraries Guide Version 8.1i

BSCAN_SPARTAN3 BSCAN_SPARTAN3_inst (
.CAPTURE(CAPTURE), // CAPTURE output from TAP controller
.DRCK1(DRCK1), // Data register output for USER1 functions
.DRCK2(DRCK2), // Data register output for USER2 functions
.RESET(RESET), // Reset output from TAP controller
.SEL1(SEL1), // USER1 active output
.SEL2(SEL2), // USER2 active output
.SHIFT(SHIFT), // SHIFT output from TAP controller
.TDI(TDI), // TDI output from TAP controller
.UPDATE(UPDATE), // UPDATE output from TAP controller
.TDO1(TDO1), // Data input for USER1 function
.TDO2(TDO2) // Data input for USER2 function
);

// End of BSCAN_SPARTAN3_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

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BUFG

BUFG
Primitive: Global Clock Buffer

BUFG distributes high fan-out clock signals throughout a PLD device.

I O
In general, the BUFG component is inferred by the synthesis tool by selecting the
highest fanout clocks in the design and appropriately inserting a BUFG until all global
clocks have been exhausted. If you desire control over BUFG insertion, this can
X9428
generally be done using synthesis directives. You can also instantiate a BUFG in the
case of either controlling the insertion of the buffer or in the cases of defining more
complex clocking networks using DCMs or other more advanced components. To
instantiate this component, use the instantiation template within the ISE Language
Template or use the code below and connect the BUFG to the appropriate clock source
and destinations in the design.
BUFG is a clock buffer with one clock input and one clock output.

Usage
To use a specific type of buffer, instantiate it manually. This design element is
supported for schematics and instantiation. Synthesis tools usually infer a BUFG on
any clock net. If there are more clock nets than BUFGs, the synthesis tool usually
instantiates BUFGs for the clocks that are most used. The BUFG contains both a BUFG
and an IBUFG.

VHDL Instantiation Template

-- BUFG : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (BUFG_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- BUFG: Global Clock Buffer (source by an internal signal)

-- Xilinx HDL Libraries Guide Version 8.1i

BUFG_inst : BUFG
port map (
O => O, -- Clock buffer output
I => I -- Clock buffer input
);

-- End of BUFG_inst instantiation

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BUFG

Verilog Instantiation Template

// BUFG : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (BUFG_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connect.

// <-----Cut code below this line---->

// BUFG: Global Clock Buffer (source by an internal signal)

// Xilinx HDL Libraries Guide Version 8.1i

BUFG BUFG_inst (
.O(O), // Clock buffer output
.I(I) // Clock buffer input
);

// End of BUFG_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

18 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

ISE 8.2i
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BUFGCE

BUFGCE

Primitive: Global Clock Buffer with Clock Enable

BUFGCE is a clock buffer with one clock input, one clock output, and a clock enable
CE line. Its O output is "0" when clock enable (CE) is Low (inactive). When clock enable
(CE) is High, the I input is transferred to the O output.
I O
Inputs Outputs
BUFGCE
I CE O
X9384
X 0 0
I 1 I

Usage
This design element is supported for instantiations but not for inference.

VHDL Instantiation Template

-- BUFGCE : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (BUFGCE_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- BUFGCE: Global Clock Buffer with Clock Enable (active high)

-- FPGA
-- Xilinx HDL Libraries Guide Version 8.1i

BUFGCE_inst : BUFGCE
port map (
O => O, -- Clock buffer ouptput
CE => CE, -- Clock enable input
I => I -- Clock buffer input
);

-- End of BUFGCE_inst instantiation

Verilog Instantiation Template

// BUFGCE : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (BUFGCE_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connect.

Spartan-3E Libraries Guide for HDL Designs www.xilinx.com 19

ISE 8.2i
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BUFGCE

// <-----Cut code below this line---->

// BUFGCE: Global Clock Buffer with Clock Enable (active high)

// FPGA
// Xilinx HDL Libraries Guide Version 8.1i

BUFGCE BUFGCE_inst (
.O(O), // Clock buffer output
.CE(CE), // Clock enable input
.I(I) // Clock buffer input
);

// End of BUFGCE_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

20 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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BUFGCE_1

BUFGCE_1

Primitive: Global Clock Buffer with Clock Enable and Output

State 1

BUFGCE is a clock buffer with one clock input, one clock output, and a clock enable
CE line. Its O output is High (1) when clock enable (CE) is Low (inactive). When clock
I O enable (CE) is High, the I input is transferred to the O output.

Inputs Outputs
BUFGCE_1
I CE O
X9385
X 0 1
I 1 I

Usage
This design element is supported for schematics and instantiations, but not for
inference.

VHDL Instantiation Template

-- BUFGCE_1 : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (BUFGCE_1_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- BUFGCE_1: Global Clock Buffer with Clock Enable (active low)

-- FPGA
-- Xilinx HDL Libraries Guide Version 8.1i

BUFGCE_1_inst : BUFGCE_1
port map (
O => O, -- Clock buffer ouptput
CE => CE, -- Clock enable input
I => I -- Clock buffer input
);

-- End of BUFGCE_1_inst instantiation

Verilog Instantiation Template

// BUFGCE_1 : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name

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BUFGCE_1

// declaration : (BUFGCE_1_inst) and/or the port declarations within the

// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connect.

// <-----Cut code below this line---->

// BUFGCE_1: Global Clock Buffer with Clock Enable (active low)

// FPGA
// Xilinx HDL Libraries Guide Version 8.1i

BUFGCE_1 BUFGCE_1_inst (
.O(O), // Clock buffer output
.CE(CE), // Clock enable input
.I(I) // Clock buffer input
);

// End of BUFGCE_1_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

22 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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BUFGMUX

BUFGMUX

Primitive: Global Clock MUX Buffer

BUFGMUX is a multiplexed global clock buffer that can select between two input
BUFGMUX clocks: I0 and I1. When the select input (S) is Low, the signal on I0 is selected for
I0
output (O). When the select input (S) is High, the signal on I1 is selected for output.
O
I1 BUFGMUX and BUFGMUX_1 are distinguished by the state the output assumes
S when that output switches between clocks in response to a change in input.
BUGFMUX assumes output state 0 and BUFGMUX_1 assumes output state 1.
X9251
Note: BUFGMUX guarantees that when S is toggled, the output remains in the inactive state
until the next active clock edge (either I0 or I1) occurs.

Inputs Outputs

I0 I1 S O
I0 X 0 I0
X I1 1 I1
X X ↑ 0
X X ↓ 0

Usage
This design element is supported for schematics and instantiations but not for
inference.

VHDL Instantiation Template

-- BUFGMUX : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (BUFGMUX_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- BUFGMUX: Global Clock Buffer 2-to-1 MUX

-- FPGA
-- Xilinx HDL Libraries Guide Version 8.1i

BUFGMUX_inst : BUFGMUX
port map (
O => O, -- Clock MUX output
I0 => I0, -- Clock0 input
I1 => I1, -- Clock1 input
S => S -- Clock select input

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BUFGMUX

);

-- End of BUFGMUX_inst instantiation

Verilog Instantiation Template

// BUFGMUX : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (BUFGMUX_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connect.

// <-----Cut code below this line---->

// BUFGMUX: Global Clock Buffer 2-to-1 MUX

// FPGA
// Xilinx HDL Libraries Guide Version 8.1i

BUFGMUX BUFGMUX_inst (
.O(O), // Clock MUX output
.I0(I0), // Clock0 input
.I1(I1), // Clock1 input
.S(S) // Clock select input
);

// End of BUFGMUX_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

24 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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BUFGMUX_1

BUFGMUX_1

Primitive: Global Clock MUX Buffer with Output State 1

BUFGMUX_1 is a multiplexed global clock buffer that can select between two input
BUFGMUX_1 clocks I0 and I1. When the select input (S) is Low, the signal on I0 is selected for
output (O). When the select input (S) is High, the signal on I1 is selected for output.
I0
O BUFGMUX and BUFGMUX_1 are distinguished by the state the output assumes
I1 when that output switches between clocks in response to a change in input.
BUFGMUX assumes output state 0 and BUFGMUX_1 assumes output state 1.
S
Inputs Outputs
X9252 I0 I1 S O
I0 X 0 I0
X I1 1 I1
X X ↑ 1
X X ↓ 1

Usage
This design element is supported for schematics and instantiations but not for
inference.

VHDL Instantiation Template

-- BUFGMUX_1 : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (BUFGMUX_1_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- BUFGMUX_1: Global Clock Buffer 2-to-1 MUX (inverted select)

-- FPGA
-- Xilinx HDL Libraries Guide Version 8.1i

BUFGMUX_1_inst : BUFGMUX_1
port map (
O => O, -- Clock MUX output
I0 => I0, -- Clock0 input
I1 => I1, -- Clock1 input
S => S -- Clock select input
);

-- End of BUFGMUX_1_inst instantiation

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BUFGMUX_1

Verilog Instantiation Template

// BUFGMUX_1 : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (BUFGMUX_1_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connect.

// <-----Cut code below this line---->

// BUFGMUX_1: Global Clock Buffer 2-to-1 MUX (inverted select)

// FPGA
// Xilinx HDL Libraries Guide Version 8.1i

BUFGMUX_1 BUFGMUX_1_inst (
.O(O), // Clock MUX output
.I0(I0), // Clock0 input
.I1(I1), // Clock1 input
.S(S) // Clock select input
);

// End of BUFGMUX_1_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

26 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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CAPTURE_SPARTAN3

CAPTURE_SPARTAN3
Primitive: Spartan-3 Register State Capture for Bitstream Readback

CAPTURE_SPARTAN3 CAPTURE_SPARTAN3 devices provide user control over when to capture register
(flip-flop and latch) information for readback. Spartan-3E devices provide the
CAP readback function through dedicated configuration port instructions.
The CAPTURE_SPARTAN3 symbol is optional. Without it, readback is still
performed, but the asynchronous capture function it provides for register states is not
CLK
available.
Spartan-3E devices allow users to capture register (flip-flop and latch) states only.
X9931 Although LUT RAM, SRL, and block RAM states are read back, they cannot be
captured. An asserted high CAP signal indicates that the registers in the device are to
be captured at the next Low-to-High clock transition.
By default, data is captured after every trigger (transition on CLK while CAP is
asserted). To limit the readback operation to a single data capture, add the ONESHOT
attribute to CAPTURE_SPARTAN3 devices.

Usage
This design element is instantiated rather than inferred.

VHDL Instantiation Template

-- CAPTURE_SPARTAN3 : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (CAPTURE_SPARTAN3_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : connect this function to the design. Delete or comment
-- : out inputs/outs that are not necessary.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- CAPTURE_SPARTAN3: Register State Capture for Bitstream Readback

-- Spartan-3
-- Xilinx HDL Libraries Guide version 8.1i

CAPTURE_SPARTAN3_inst : CAPTURE_SPARTAN3
port map (
CAP => CAP, -- Capture input
CLK => CLK -- Clock input
);

-- End of CAPTURE_SPARTAN3_inst instantiation

Verilog Instantiation Template

// CAPTURE_SPARTAN3 : In order to incorporate this function into the design,

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CAPTURE_SPARTAN3

// Verilog : the following instance declaration needs to be placed

// instance : in the body of the design code. The instance name
// declaration : (CAPTURE_SPARTAN3_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. Delete or comment
// : out inputs/outs that are not necessary.

// <-----Cut code below this line---->

// CAPTURE_SPARTAN3: Register State Capture for Bitstream Readback

// Spartan-3/3E
// Xilinx HDL Libraries Guide Version 8.1i

CAPTURE_SPARTAN3 CAPTURE_SPARTAN3_inst (
.CAP(CAP), // Capture input
.CLK(CLK) // Clock input
);

// End of CAPTURE_SPARTAN3_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

28 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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DCM_SP

DCM_SP
Primitive: Digital Clock Manager
DCM
CLKIN CLK0
DCM_SP is a digital clock manager that provides multiple functions. It can implement
CLKFB CLK90
a clock delay locked loop, a digital frequency synthesizer, digital phase shifter.
CLK180 Note: All unused inputs must be driven Low, automatically tying the inputs Low if they are
RST CLK270 unused. The DSSEN input pin for the DCM_SP is no longer recommended for use and should
CLK2X remain unconnected in the design.
CLK2X180

CLKDV Clock Delay Locked Loop (DLL)

PSINCDEC
CLKFX
PSEN DCM_SP includes a clock delay locked loop used to minimize clock skew for Spartan-
CLKFX180
PSCLK 3E devices. DCM_SP synchronizes the clock signal at the feedback clock input
LOCKED
(CLKFB) to the clock signal at the input clock (CLKIN). The locked output (LOCKED)
is high when the two signals are in phase. The signals are considered to be in phase
STATUS [7:0] when their rising edges are within a specified time (ps) of each other.
On-chip synchronization is achieved by connecting the CLKFB input to a point on the
PSDONE global clock network driven by a BUFG, a global clock buffer. The BUFG connected to
X10262 the CLKFB input of the DCM_SP must be sourced from either the CLK0 or CLK2X
outputs of the same DCM_SP. The CLKIN input should be connected to the output of
an IBUFG, with the IBUFG input connected to a pad driven by the system clock.
Off-chip synchronization is achieved by connecting the CLKFB input to the output of
an IBUFG, with the IBUFG input connected to a pad. Either the CLK0 or CLK2X
output can be used but not both. The CLK0 or CLK2X must be connected to the input
of OBUF, an output buffer. The CLK_FEEDBACK attribute controls whether the CLK0
output, the default, or the CLK2X output is the source of the CLKFB input.
DCM_SP Clock Delay Lock Loop Outputs

Output Description
CLK0 Clock at 1x CLKIN frequency
CLK180 Clock at 1x CLK0 frequency, shifted 180o with regards to CLK0
CLK270 Clock at 1x CLK0 frequency, shifted 270o with regards to CLK0
CLK2X Clock at 2x CLK0 frequency, in phase with CLK0
CLK2X180 Clock at 2x CLK0 frequency shifted 180o with regards to CLK2X
CLK90 Clock at 1x CLK0 frequency, shifted 90o with regards to CLK0
CLKDV Clock at (1/n) x CLK0 frequency, where n=CLKDV_DIVIDE value.
CLKDV is in phase with CLK0.
LOCKED All enabled DCM_SP features locked.

Digital Frequency Synthesizer (DFS)

The CLKFX and CLKFX180 outputs in conjunction with the CLKFX_MULTIPLY and
CLKFX_DIVIDE attributes provide a frequency synthesizer that can be any multiple
or division of CLKIN. CLKFX and CLKIN are in phase every CLKFX_MULTIPLY
cycles of CLKFX and every CLKFX_DIVIDE cycles of CLKIN when a feedback is
provided to the CLKFB input of the DLL. The frequency of CLKFX is defined by the
following equation.

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DCM_SP

FrequencyCLKFX=
(CLKFX_MULTIPLY_value/CLKFX_DIVIDE_value) * FrequencyCLKIN
Both the CLKFX or CLKFX180 output can be used simultaneously.
CLKFX180 is 1x the CLKFX frequency, shifted 180o with regards to CLKFX. CLKFX
and CLKFX180 always have a 50/50 duty cycle.
The CLK_FEEDBACK attribute set to NONE causes the DCM_SP to be in the Digital
Frequency Synthesizer mode. The CLKFX and CLKFX180 are generated without
phase correction with respect to CLKIN.
The DSSEN input pin for the DCM_SP is no longer recommended for use and should
remain unconnected in the design.

Digital Phase Shifter (DPS)

The phase shift (skew) between the rising edges of CLKIN and CLKFB can be
configured as a fraction of the CLKIN period with the PHASE_SHIFT attribute. This
allows the phase shift to remain constant as ambient conditions change. The
CLKOUT_PHASE_SHIFT attribute controls the use of the PHASE_SHIFT value. By
default, the CLKOUT_PHASE_SHIFT attribute is set to NONE and the
PHASE_SHIFT attribute has no effect.
By creating skew between CLKIN and CLKFB, all DCM_SP output clocks are phase
shifted by the amount of the skew.
When the CLKOUT_PHASE_SHIFT attribute is set to FIXED, the skew set by the
PHASE_SHIFT attribute is used at configuration for the rising edges of CLKIN and
CLKFB. The skew remains constant.
When the CLKOUT_PHASE_SHIFT attribute is set to VARIABLE, the skew set at
configuration is used as a starting point and the skew value can be changed
dynamically during operation using the PS* signals. This digital phase shifter feature
is controlled by a synchronous interface. The inputs PSEN (phase shift enable) and
PSINCDEC (phase shift increment/decrement) are set up to the rising edge of PSCLK
(phase shift clock). The PSDONE (phase shift done) output is clocked with the rising
edge of PSCLK (the phase shift clock). PSDONE must be connected to implement the
complete synchronous interface. The rising-edge skew between CLKIN and CLKFB
can be dynamically adjusted after the LOCKED output goes High.
The PHASE_SHIFT attribute value specifies the initial phase shift amount when the
device is configured. Then the PHASE_SHIFT value is changed one unit when PSEN
is activated for one period of PSCLK. The PHASE_SHIFT value is incremented when
PSINCDEC is High and decremented when PSINCDEC is Low during the period that
PSEN is High. When the DCM_SP completes an increment or decrement operation,
the PSDONE output goes High for a single PSCLK cycle to indicate the operation is
complete. At this point the next change can be made. When RST (reset) is High, the
PHASE_SHIFT attribute value is reset to the skew value set at configuration.
If CLKOUT_PHASE_SHIFT is FIXED or NONE, the PSEN, PSINCDEC, and PSCLK
inputs must be tied to GND. The program automatically ties the inputs to GND if they
are not connected by the user.

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DCM_SP

FACTORY_JF Attribute
The FACTORY_JF attribute affects the DCM_SP's jitter filter characteristic. This
attribute is set the default value of C080 and should not be modified unless otherwise
instructed by Xilinx.

Additional Status Bits

The STATUS output bits return the following information.
DCM_SP Additional Status Bits

Bit Description
0 Phase Shift Overflow*
1 = |PHASE_SHIFT| > 255
1 DLL CLKIN stopped**
1 = CLKIN stopped toggling
2 DLL CLKFX stopped
1 = CLKFX stopped toggling
3 No
4 No
5 No
6 No
7 No

* Phase Shift Overflow also goes high if the end of the phase shift delay line is reached
(see the product data sheet for the value of the maximum shifting delay).
** If only the DFS outputs are used (CLKFX & CLKFX180), this status bit does not go
high if CLKIN stops.

LOCKED
When LOCKED is high, all enabled signals are locked.

RST
The master reset input (RST) resets DCM_SP to its initial (power-on) state. The signal
at the RST input is asynchronous and must be held High for 2 ns.

Usage
This component is instantiated in the code as it cannot be easily inferred in synthesis
tools. Some synthesis tools can allow inference via an attribute. See your synthesis
tool documentation.

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DCM_SP

Available Attributes
Attribute Type Allowed Values Default Description
CLK_ String "NONE", "1X" or "1X” Specifies clock
FEEDBACK "2X” feedback of NONE, 1X
or 2X.
CLKDV_DIVIDE Real 1.5, 2.0, 2.5, 3.0, 3.5, 2.0 Specifies the extent to
4.0, 4.5, 5.0, 5.5, 6.0, which the DCM_SP
6.5, 7.0, 7.5, 8.0, 9.0, clock divider (CLKDV
10.0, 11.0, 12.0, 13.0, output) is to be
14.0, 15.0 or 16.0 frequency divided.
CLKFX_DIVIDE Integer 1 to 32 1 Specifies the frequency
divider value for the
CLKFX output.
CLKFX_MULTI- Integer 1 to 32 4 Specifies the frequency
PLY multiplier value for the
CLKFX output.
CLKIN_ Boolean FALSE, TRUE FALSE Enables CLKIN divide
DIVIDE_ by two features.
BY_2
CLKIN_ Real Any value (in ns) 0 Specifies the input
PERIOD within the period to the DCM_SP
operating CLKIN input in ns).
frequency of the
device.
CLKOUT_ String "NONE", "FIXED" "NONE” Specifies the phase
PHASE_ or "VARIABLE” shift of NONE, FIXED
SHIFT or VARIABLE.
DESKEW_ String "SOURCE_ "SYSTEM_ Sets configuration bits
ADJUST SYNCHRONOUS", SYNCHRO- affecting the clock
"SYSTEM_ NOUS" delay alignment
SYNCHRONOUS" between the DCM_SP
or "0" to "15” output clocks and an
FPGA clock input pin.
FACTORY_JF 16-Bit Any 16-Bit x8080 The FACTORY_JF
Hexidecimal Hexadecimal value attribute affects the
DCMs jitter filter
characteristic. This
attribute is set the
default value of F0F0
and should not be
modified unless
otherwise instructed
by Xilinx.
PHASE_SHIFT Integer -255 to 255 0 Defines the amount of
fixed phase shift from -
255 to 255
STARTUP_ Boolean FALSE, TRUE FALSE Delays configuration
WAIT DONE until DCM_SP
LOCK.

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DCM_SP

VHDL Instantiation Template

-- DCM_SP : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (DCM_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : connect this function to the design. Unused inputs
-- : and outputs can be removed or commented out.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- DCM_SP: Digital Clock Manager Circuit for Spartan-3E

-- Xilinx HDL Libraries Guide Version 8.1i

DCM_inst : DCM_SP
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any Integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 0.0, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an Integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE
port map (
CLK0 => CLK0, -- 0 degree DCM_SP CLK ouptput
CLK180 => CLK180, -- 180 degree DCM_SP CLK output
CLK270 => CLK270, -- 270 degree DCM_SP CLK output
CLK2X => CLK2X, -- 2X DCM_SP CLK output
CLK2X180 => CLK2X180, -- 2X, 180 degree DCM_SP CLK out
CLK90 => CLK90, -- 90 degree DCM_SP CLK output
CLKDV => CLKDV, -- Divided DCM_SP CLK out (CLKDV_DIVIDE)
CLKFX => CLKFX, -- DCM_SP CLK synthesis out (M/D)
CLKFX180 => CLKFX180, -- 180 degree CLK synthesis out
LOCKED => LOCKED, -- DCM_SP LOCK status output
PSDONE => PSDONE, -- Dynamic phase adjust done output
STATUS => STATUS, -- 8-bit DCM_SP status bits output
CLKFB => CLKFB, -- DCM_SP clock feedback
CLKIN => CLKIN, -- Clock input (from IBUFG, BUFG or DCM_SP)
PSCLK => PSCLK, -- Dynamic phase adjust clock input
PSEN => PSEN, -- Dynamic phase adjust enable input
PSINCDEC => PSINCDEC, -- Dynamic phase adjust increment/decrement
RST => RST -- DCM_SP asynchronous reset input
);

-- End of DCM_inst instantiation

Verilog Instantiation Template

// DCM_SP : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (DCM_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. Unused inputs

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DCM_SP

// : and outputs can be removed or commented out.

// <-----Cut code below this line---->

// DCM_SP: Digital Clock Manager Circuit for Spartan-3E

// Xilinx HDL Libraries Guide Version 8.1i

DCM_SP #(
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(1), // Can be any Integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any Integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(0.0), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an Integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'hC080), // FACTORY JF values
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE
) DCM_inst (
.CLK0(CLK0), // 0 degree DCM_SP CLK output
.CLK180(CLK180), // 180 degree DCM_SP CLK output
.CLK270(CLK270), // 270 degree DCM_SP CLK output
.CLK2X(CLK2X), // 2X DCM_SP CLK output
.CLK2X180(CLK2X180), // 2X, 180 degree DCM_SP CLK out
.CLK90(CLK90), // 90 degree DCM_SP CLK output
.CLKDV(CLKDV), // Divided DCM_SP CLK out (CLKDV_DIVIDE)
.CLKFX(CLKFX), // DCM_SP CLK synthesis out (M/D)
.CLKFX180(CLKFX180), // 180 degree CLK synthesis out
.LOCKED(LOCKED), // DCM_SP LOCK status output
.PSDONE(PSDONE), // Dynamic phase adjust done output
.STATUS(STATUS), // 8-bit DCM_SP status bits output
.CLKFB(CLKFB), // DCM_SP clock feedback
.CLKIN(CLKIN), // Clock input (from IBUFG, BUFG or DCM_SP)
.PSCLK(PSCLK), // Dynamic phase adjust clock input
.PSEN(PSEN), // Dynamic phase adjust enable input
.PSINCDEC(PSINCDEC), // Dynamic phase adjust increment/decrement
.RST(RST) // DCM_SP asynchronous reset input
);

// End of DCM_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

34 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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FDCPE

FDCPE
Primitive: D Flip-Flop with Clock Enable and Asynchronous Preset and
Clear
FDCPE is a single D-type flip-flop with data (D), clock enable (CE), asynchronous
preset (PRE), and asynchronous clear (CLR) inputs and data output (Q). The
PRE
asynchronous PRE, when High, sets the Q output High; CLR, when High, resets the
output Low. Data on the D input is loaded into the flip-flop when PRE and CLR are
D FDCPE Low and CE is High on the Low-to-High clock (C) transition. When CE is Low, the
CE Q clock transitions are ignored.
C
The flip-flop is asynchronously cleared, output Low, when power is applied.

CLR
For Spartan-3E devices, the power-on condition can be simulated when global
set/reset (GSR) is active.
X4389
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the Spartan-3E symbol.

Inputs Outputs

CLR PRE CE D C Q
1 X X X X 0
0 1 X X X 1
0 0 0 X X No Change
0 0 1 0 ↑ 0
0 0 1 1 ↑ 1

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

Available Attributes
Allowed
Attribute Type Default Description
Values
INIT 1-Bit 1-Bit Binary 1'b0 Sets the initial value of
Binary Q output after
configuration

VHDL Instantiation Template

-- FDCPE : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (FDCPE_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : connect this function to the design. Delete or comment
-- : out inputs/outs that are not necessary.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx

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ISE 8.2i
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FDCPE

-- primitives : primitives and points to the models that are used

-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- FDCPE: Single Data Rate D Flip-Flop with Asynchronous Clear, Set and
-- Clock Enable (posedge clk). All families.
-- Xilinx HDL Libraries Guide version 8.1i

FDCPE_inst : FDCPE
generic map (
INIT => '0') -- Initial value of register ('0' or '1')
port map (
Q => Q, -- Data output
C => C, -- Clock input
CE => CE, -- Clock enable input
CLR => CLR, -- Asynchronous clear input
D => D, -- Data input
PRE => PRE -- Asynchronous set input
);

-- End of FDCPE_inst instantiation

Verilog Instantiation Template

// FDCPE : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (FDCPE_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. Delete or comment
// : out inputs/outs that are not necessary.

// <-----Cut code below this line---->

// FDCPE: Single Data Rate D Flip-Flop with Asynchronous Clear, Set and
// Clock Enable (posedge clk). All families.
// Xilinx HDL Libraries Guide Version 8.1i

FDCPE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDCPE_inst (
.Q(Q), // Data output
.C(C), // Clock input
.CE(CE), // Clock enable input
.CLR(CLR), // Asynchronous clear input
.D(D), // Data input
.PRE(PRE) // Asynchronous set input
);

// End of FDCPE_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

36 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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FDRSE

FDRSE
Primitive: D Flip-Flop with Synchronous Reset and Set and Clock
Enable

S
FDRSE is a single D-type flip-flop with synchronous reset (R), synchronous set (S),
and clock enable (CE) inputs and data output (Q). The reset (R) input, when High,
overrides all other inputs and resets the Q output Low during the Low-to-High clock
D FDRSE Q
transition. (Reset has precedence over Set.) When the set (S) input is High and R is
CE
Low, the flip-flop is set, output High, during the Low-to-High clock (C) transition.
C
Data on the D input is loaded into the flip-flop when R and S are Low and CE is High
during the Low-to-High clock transition.
R X3732
The flip-flop is asynchronously cleared, output Low, by default, when power is
applied or when GSR is active.

Inputs Outputs

R S CE D C Q
1 X X X ↑ 0
0 1 X X ↑ 1
0 0 0 X X No Change
0 0 1 1 ↑ 1
0 0 1 0 ↑ 0

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

Available Attributes
Allowed
Attribute Type Default Description
Values
INIT Binary 0, 1 0 Sets the initial value of
Q output after
configuration and on
GSR

VHDL Instantiation Template

-- FDRSE : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (FDCRS_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : connect this function to the design. Delete or comment
-- : out inputs/outs that are not necessary.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

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FDRSE

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- FDRSE: Single Data Rate D Flip-Flop with Synchronous Clear, Set and
-- Clock Enable (posedge clk). All families.
-- Xilinx HDL Libraries Guide version 8.1i

FDRSE_inst : FDRSE
generic map (
INIT => '0') -- Initial value of register ('0' or '1')
port map (
Q => Q, -- Data output
C => C, -- Clock input
CE => CE, -- Clock enable input
D => D, -- Data input
R => R, -- Synchronous reset input
S => S -- Synchronous set input
);

-- End of FDRSE_inst instantiation

Verilog Instantiation Template

// FDRSE : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (FDCRS_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. Delete or comment
// : out inputs/outs that are not necessary.

// <-----Cut code below this line---->

// FDRSE: Single Data Rate D Flip-Flop with Synchronous Clear, Set and
// Clock Enable (posedge clk). All families.
// Xilinx HDL Libraries Guide Version 8.1i

FDRSE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRSE_inst (
.Q(Q), // Data output
.C(C), // Clock input
.CE(CE), // Clock enable input
.D(D), // Data input
.R(R), // Synchronous reset input
.S(S) // Synchronous set input
);

// End of FDRSE_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

38 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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IBUF

IBUF
Primitive: Single-Ended Input Buffer with Selectable I/O Standard
Input Buffers are necessary to isolate the internal circuit from the signals coming into
IBUF the FPGA. IBUFs are contained in input/output blocks (IOB). IBUFs allow the
specification of the particular I/O Standard to configure the I/O. In general, an IBUF
I O should be used for all single-ended data input or bidirectional pins.

Inputs (I) Outputs (O)

X9442 0/L 0
1/H 1
U/X/Z X

Usage
IBUFs are automatically inserted (inferred) to any signal directly connected to a top
level input or inout port of the design by the synthesis tool. It is generally
recommended to allow the synthesis tool to infer this buffer however if so desired, the
IBUF can be instantiated into the design. In order to do so, connect the input port, I, of
the component directly to the associated top-level input or in-out port and connect the
output port, O, to the FPGA logic to be sourced by that port. Modify any necessary
generic maps (VHDL) or named parameter value assignment (Verilog) in order to
change the default behavior of the component.

Available Attribute
Attribute Type Allowed Values Default Description
IOSTANDARD String "DEFAULT "DEFAULT” Use to assign an
I/O standard to an
I/O primitive.
IBUF_DELAY_ Integer 0 to 16 0 Specifies the
VALUE amount of
additional delay to
add to the non-
registered path out
of the IOB.
IFD_DELAY_ String "AUTO" or 0 to 8 "AUTO” Specifies the
VALUE amount of
additional delay to
add to the
registered path
within the IOB.

Note: Consult the device user guide or databook for the allowed values and the default value.

VHDL Instantiation Templates

-- IBUF : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (IBUF_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : connect this function to the design. Delete or comment
-- : out inputs/outs that are not necessary.

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ISE 8.2i
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IBUF

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- IBUF: Single-ended Input Buffer

-- All devices
-- Xilinx HDL Libraries Guide version 8.1i

IBUF_inst : IBUF
generic map (
IOSTANDARD => "DEFAULT")
port map (
O => O, -- Buffer output
I => I -- Buffer input (connect directly to top-level port)
);

-- End of IBUF_inst instantiation

Verilog Instantiation Templates

// IBUF : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (IBUF_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. Delete or comment
// : out inputs/outs that are not necessary.

// <-----Cut code below this line---->

// IBUF: Single-ended Input Buffer

// All devices
// Xilinx HDL Libraries Guide 8.1i

IBUF #(
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
)IBUF_inst (
.O(O), // Buffer output
.I(I) // Buffer input (connect directly to top-level port)
);

// End of IBUF_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

40 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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IBUFDS

IBUFDS
Primitive: Differential Signaling Input Buffer with Selectable I/O Interface

IBUFDS is an input buffer that supports low-voltage, differential signaling. In

I
O IBUFDS, a design level interface signal is represented as two distinct ports (I and IB),
IB
one deemed the "master" and the other the "slave." The master and the slave are
opposite phases of the same logical signal (for example, MYNET and MYNETB).
X9255
Inputs Outputs
I IB O
0 0 No Change
0 1 0
1 0 1
1 1 No Change

Usage
This design element is supported for instantiation but not for inference.

Available Attributes
Allowed
Attribute Type Default Description
Values
DIFF_TERM Boolean FALSE, TRUE FALSE Enables the built-in
differential termination
resistor.
IOSTANDARD String "DEFAULT” "DEFAULT” Use to assign an I/O
standard to an I/O
primitive.

VHDL Instantiation Template

-- IBUFDS : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (IBUFDS_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- IBUFDS: Differential Input Buffer

-- FPGA
-- Xilinx HDL Libraries Guide Version 8.1i

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IBUFDS

IBUFDS_inst : IBUFDS
generic map (
IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E
only)
IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8"
(Spartan-3E only)
IOSTANDARD => "DEFAULT")
port map (
O => O, -- Clock buffer output
I => I, -- Diff_p clock buffer input (connect directly to top-level port)
IB => IB -- Diff_n clock buffer input (connect directly to top-level port)
);

-- End of IBUFDS_inst instantiation

Verilog Instantiation Template

// IBUFDS : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (IBUFDS_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connect.

// <-----Cut code below this line---->

// IBUFDS: Differential Input Buffer

// FPGA
// Xilinx HDL Libraries Guide Version 8.1i

IBUFDS #(
.DIFF_TERM("FALSE"), // Differential Termination
.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-
3E only)
.IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8"
(Spartan-3E .IOSTANDARD("DEFAULT") // Specify the input I/O standard
) IBUFDS_inst (
.O(O), // Clock buffer output
.I(I), // Diff_p clock buffer input (connect directly to top-level port)
.IB(IB) // Diff_n clock buffer input (connect directly to top-level port)
);

// End of IBUFDS_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

42 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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IBUFG

IBUFG
Primitive: Dedicated Input Buffer with Selectable I/O Interface
IBUFG is dedicated to input buffers and is used for connecting to the clock buffer
BUFG or DCM_SP. You can attach an IOSTANDARD attribute to an IBUFG instance.
I O
The IBUFG input can only be driven by the global clock pins. The IBUFG output can
drive CLKIN of a DCM_SP, BUFG, or user logic. IBUFG can be routed to user logic
and does not have to be routed to a DCM_SP.
IBUFG
X10181
Attach an IOSTANDARD attribute to an IBUFG and assign the value indicated in the
"IOSTANDARD (Attribute Value)" column to program the input for the I/O standard
associated with that value.

Usage
This design element is supported for schematic and instantiation. Synthesis tools
usually infer a BUFGP on any clock net. If there are more clock nets than BUFGPs, the
synthesis tool usually instantiates BUFGPs for the clocks that are most used. The
BUFGP contains both a BUFG and an IBUFG.

Available Attributes
Attribute Type Allowed Values Default Description
IOSTANDARD String "DEFAULT” "DEFAULT” Use to assign an I/O
standard to an I/O
primitive.

VHDL Instantiation Template

-- IBUFG : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (IBUFG_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- IBUFG: Single-ended global clock input buffer

-- All FPGA
-- Xilinx HDL Libraries Guide Version 8.1i

IBUFG_inst : IBUFG
generic map (
IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E
only)
IOSTANDARD => "DEFAULT")
port map (
O => O, -- Clock buffer output

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IBUFG

I => I -- Clock buffer input (connect directly to top-level port)

);

-- End of IBUFG_inst instantiation

Verilog Instantiation Template

// IBUFG : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (IBUFG_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connect.

// <-----Cut code below this line---->

// IBUFG: Global Clock Buffer (sourced by an external pin)

// All FPGAs
// Xilinx HDL Libraries Guide Version 8.1i

IBUFG #(
.IOSTANDARD("DEFAULT")
) IBUFG_inst (
.O(O), // Clock buffer output
.I(I) // Clock buffer input (connect directly to top-level port)
);

// End of IBUFG_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

44 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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IBUFGDS

IBUFGDS
Primitive: Dedicated Differential Signaling Input Buffer with Selectable
I/O Interface

IBUFGDS is a dedicated differential signaling input buffer for connection to the clock
I buffer (BUFG) or DCM_SP. In IBUFGDS, a design-level interface signal is represented
O
IB as two distinct ports (I and IB), one deemed the "master" and the other the "slave." The
master and the slave are opposite phases of the same logical signal (for example,
MYNET and MYNETB).
X9255
Inputs Outputs

I IB O
0 0 No Change
0 1 0
1 0 1
1 1 No Change

Usage
This design element is supported for instantiation, but not for inference.

Available Attributes
Allowed
Attribute Type Default Description
Values
DIFF_TERM Boolean FALSE, TRUE FALSE Enables the built-in
differential termination
resistor.
IOSTANDARD String "DEFAULT” "DEFAULT” Use to assign an I/O
standard to an I/O
primitive.

VHDL Instantiation Template

-- IBUFGDS : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (IBUFGDS_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

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IBUFGDS

-- IBUFGDS: Differential Global Clock Input Buffer

-- FPGA
-- Xilinx HDL Libraries Guide Version 8.1i

IBUFGDS_inst : IBUFGDS
generic map (
DIFF_TERM => "FALSE", -- Differential Termination
IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E
only)
IOSTANDARD => "DEFAULT")
port map (
O => O, -- Clock buffer output
I => I, -- Diff_p clock buffer input (connect directly to top-level port)
IB => IB -- Diff_n clock buffer input (connect directly to top-level port)
);

-- End of IBUFGDS_inst instantiation

Verilog Instantiation Template

// IBUFGDS : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (IBUFGDS_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connect.

// <-----Cut code below this line---->

// IBUFGDS: Differential Global Clock Buffer (sourced by an external pin)

// FPGA
// Xilinx HDL Libraries Guide Version 8.1i

IBUFGDS #(
.DIFF_TERM("FALSE"),
.IOSTANDARD("DEFAULT")
) IBUFGDS_inst (
.O(O), // Clock buffer output
.I(I), // Diff_p clock buffer input
.IB(IB) // Diff_n clock buffer input
);

// End of IBUFGDS_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

46 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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IDDR2

IDDR2
Primitive: Double Data Rate Input D Flip-Flop with Optional Data
Alignment, Clock Enable and Programmable Synchronous or
Asynchronous Set/Reset
The IDDR2 is an input double data rate (DDR) register useful in capturing double
data-rate signals entering the FPGA. The IDDR2 requires two clocks to be connected
IDDR2
D
to the component, C0 and C1, so that data is captured at the positive edge of both C0
C0 Q0

C1
and C1 clocks. The IDDR2 features an active high clock enable port, CE, which can be
CE used to suspend the operation of the registers and both set and reset ports that can be
Q1
R configured to be synchronous or asynchronous to the respective clocks. The IDDR2
S
has an optional alignment feature, which allows both output data ports to the
component to be aligned to a single clock.
X10237

Usage
The IDDR2 must be instantiated to be incorporated into a design. To change the
default behavior of the IDDR2, attributes can be modified via the generic map
(VHDL) or named parameter value assignment (Verilog) as a part of the instantiated
component. The IDDR2 can be either connected directly to a top-level input port in
the design where an appropriate input buffer can be inferred or to an instantiated
IBUF, IOBUF, IBUFDS or IOBUFDS. All inputs and outputs of this component should
either be connected or properly tied off.

Available Attributes
Allowed
Attribute Type Default Description
Values
DDR_ALIGN- String "NONE", "NONE” Sets output alignment.
MENT "C0" or "C1”
INIT_Q0 Integer 0 or 1 0 Sets initial state of the Q0
output to
0 or 1.
INIT_Q1 Integer 0 or 1 0 Sets initial state of the Q1
output to
0 or 1.
SRTYPE String "SYNC" or "SYNC” Specifies "SYNC" or "ASYNC"
"ASYNC” set/reset.

VHDL Instantiation Template

-- IDDR2 : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (IDDR2_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : connect this function to the design. All inputs
-- : and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

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IDDR2

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- IDDR2: Input Double Data Rate Input Register with Set, Reset
-- and Clock Enable. Spartan-3E
-- Xilinx HDL Libraries Guide version 8.1i

IDDR2_inst : IDDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT_Q0 => '0', -- Sets initial state of the Q0 output to '0' or '1'
INIT_Q1 => '0', -- Sets initial state of the Q1 output to '0' or '1'
SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q0 => Q0, -- 1-bit output captured with C0 clock
Q1 => Q1, -- 1-bit output captured with C1 clock
C0 => C0, -- 1-bit clock input
C1 => C1, -- 1-bit clock input
CE => CE, -- 1-bit clock enable input
D => D, -- 1-bit data input
R => R, -- 1-bit reset input
S => S -- 1-bit set input
);

-- End of IDDR2_inst instantiation

Verilog Instantiation Templae

// IDDR2 : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (IDDR2_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. Delete or comment
// : out inputs/outs that are not necessary.

// <-----Cut code below this line---->

// IDDR2: Input Double Data Rate Input Register with Set, Reset
// and Clock Enable. Spartan-3E
// Xilinx HDL Libraries Guide Version 8.1i

IDDR2 #(
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1'b0 or 1'b1
.INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1'b0 or 1'b1
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
) IDDR2_inst (
.Q0(Q0), // 1-bit output captured with C0 clock
.Q1(Q1), // 1-bit output captured with C1 clock
.C0(C0), // 1-bit clock input
.C1(C1), // 1-bit clock input
.CE(CE), // 1-bit clock enable input
.D(D), // 1-bit DDR data input
.R(R), // 1-bit reset input
.S(S) // 1-bit set input
);

// End of IDDR2_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

48 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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IOBUF

IOBUF
Primitive: bidirectional Buffer with Selectable I/O Interface

For Spartan-3E, IOBUF is a bidirectional buffer whose I/O interface corresponds to an

T
I/O standard. You can attach an IOSTANDARD attribute to an IOBUF instance.
IOBUF components that use the LVTTL, LVCMOS15, LVCMOS18, LVCMOS25,
I IO LVCMOS33 signaling standards have selectable capacitance drive and slew rates
using the capacitance DRIVE and SLEW constraints.
O
IOBUFs are composites of IBUF and OBUFT elements. The O output is X (unknown)
X8406 when I/O (input/output) is Z. IOBUFs can be implemented as interconnections of
their component elements.

Inputs Bidirectional Outputs

T I IO O
1 X Z X
0 1 1 1
0 0 0 0

Usage
These design elements are instantiated and inferred.

Available Attributes
Attribute Type Allowed Values Default Description
IOSTANDARD String "DEFAULT” "DEFAULT” Use to assign an I/O
standard to an I/O
primitive.

VHDL Instantiation Template

-- IOBUF : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (IOBUF_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : connect this function to the design. Delete or comment
-- : out inputs/outs that are not necessary.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- IOBUF: Single-ended bidirectional Buffer

-- All devices

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IOBUF

-- Xilinx HDL Libraries Guide version 8.1i

IOBUF_inst : IOBUF
generic map (
DRIVE => 12,
IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E
only)
IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8"
(Spartan-3E only)
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map (
O => O, -- Buffer output
IO => IO, -- Buffer inout port (connect directly to top-level port)
I => I, -- Buffer input
T => T -- 3-state enable input
);

-- End of IOBUF_inst instantiation

Verilog Instantiation Template

// IOBUF : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (IOBUF_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. Delete or comment
// : out inputs/outs that are not necessary.

// <-----Cut code below this line---->

// IOBUF: Single-ended bidirectional Buffer

// All devices
// Xilinx HDL Libraries Guide Version 8.1i

IOBUF #(
.DRIVE(12), // Specify the output drive strength
.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-
3E only)
.IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8"
(Spartan-3E only)
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
.SLEW("SLOW") // Specify the output slew rate
) IOBUF_inst (
.O(O), // Buffer output
.IO(IO), // Buffer inout port (connect directly to top-level port)
.I(I), // Buffer input
.T(T) // 3-state enable input
);

// End of IOBUF_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

50 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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IOBUFDS

IOBUFDS

Primitive: 3-State Differential Signaling I/O Buffer with Active Low

Output Enable

IOBUFDS is a single 3-state, differential signaling input/output buffer with active

T Low output enable.

I IO Inputs Bidirectional Outputs

IOB
I T IO IOB O
O
X 1 Z Z -*
0 0 0 1 0
X9827
1 0 1 0 1

* The dash (-) means No Change.

Usage
This design element is instantiated rather than inferred.

Available Attibutes
Allowed
Attribute Type Default Description
Values
DRIVE Integer 2, 4, 6, 8, 12, 12 Selects output drive
16, 24 strength (mA) for the
SelectIO buffers that use
the LVTTL, LVCMOS12,
LVCMOS15, LVCMOS18,
LVCMOS25, or LVCMOS33
interface I/O standard.
IOSTANDARD String "DEFAULT” "DEFAULT” Use to assign an I/O
standard to an I/O
primitive.
SLEW String "SLOW" or "SLOW” Sets the output rise and fall
"FAST” time.

VHDL Instantiation Template

-- IOBUFDS : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (IOBUFDS_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : connect this function to the design. Delete or comment
-- : out inputs/outs that are not necessary.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the

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IOBUFDS

-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- IOBUFDS: Differential bidirectional Buffer

-- FPGA
-- Xilinx HDL Libraries Guide version 8.1i

IOBUFDS_inst : IOBUFDS
generic map (
IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E
only)
IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8"
(Spartan-3E only)
IOSTANDARD => "DEFAULT")
port map (
O => O, -- Buffer output
IO => IO, -- Diff_p inout (connect directly to top-level port)
IOB => IOB, -- Diff_n inout (connect directly to top-level port)
I => I, -- Buffer input
T => T -- 3-state enable input
);

-- End of IOBUFDS_inst instantiation

Verilog Instantiation Template

// IOBUFDS : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (IOBUFDS_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. Delete or comment
// : out inputs/outs that are not necessary.

// <-----Cut code below this line---->

// IOBUFDS: Differential bidirectional Buffer

// FPGA
// Xilinx HDL Libraries Guide Version 8.1i

IOBUFDS #(
.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-
3E only)
.IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8"
(Spartan-3E only)
.IOSTANDARD("DEFAULT") // Specify the I/O standard
) IOBUFDS_inst (
.O(O), // Buffer output
.IO(IO), // Diff_p inout (connect directly to top-level port)
.IOB(IOB), // Diff_n inout (connect directly to top-level port)
.I(I), // Buffer input
.T(T) // 3-state enable input
);

// End of IOBUFDS_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

52 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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KEEPER

KEEPER
Primitive: KEEPER Symbol
KEEPER is a weak keeper element used to retain the value of the net connected to its
bidirectional O pin. For example, if a logic 1 is being driven onto the net, KEEPER
drives a weak/resistive 1 onto the net. If the net driver is then 3-stated, KEEPER
continues to drive a weak/resistive 1 onto the net.

Usage
This design element is instantiated rather than inferred.
O
X8718
VHDL Instantiation Template
-- KEEPER : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (KEEPER_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : connect this function to the design. Delete or comment
-- : out inputs/outs that are not necessary.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- KEEPER: I/O Buffer Weak Keeper

-- All FPGA
-- Xilinx HDL Libraries Guide version 8.1i

KEEPER_inst : KEEPER
port map (
O => O -- Keeper output (connect directly to top-level port)
);

-- End of KEEPER_inst instantiation

Verilog Instantiation Template

// KEEPER : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (KEEPER_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. Delete or comment
// : out inputs/outs that are not necessary.

// <-----Cut code below this line---->

// KEEPER: I/O Buffer Weak Keeper

// All FPGA
// Xilinx HDL Libraries Guide Version 8.1i

KEEPER KEEPER_inst (
.O(O), // Keeper output (connect directly to top-level port)
);

// End of KEEPER_inst instantiation

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KEEPER

For More Information

Consult the Spartan-3E Data Sheet.

54 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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LDCPE

LDCPE

Primitive: Transparent Data Latch with Asynchronous Clear and Preset

and Gate Enable

PRE LDCPE is a transparent data latch with data (D), asynchronous clear (CLR),
asynchronous preset (PRE), and gate enable (GE). When CLR is High, it overrides the
D LDCPE other inputs and resets the data (Q) output Low. When PRE is High and CLR is Low, it
GE Q
presets the data (Q) output High. Q reflects the data (D) input while the gate (G) input
G
and gate enable (GE) are High and CLR and PRE are Low. The data on the D input
during the High-to-Low gate transition is stored in the latch. The data on the Q output
CLR
remains unchanged as long as G or GE remains Low.
X8371
The latch is asynchronously cleared, output Low, when power is applied, or when
global reset is active.
For Spartan-3E devices, power-on conditions are simulated when global set/reset
(GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the Spartan-3E symbol.

Inputs Outputs

CLR PRE GE G D Q
1 X X X X 0
0 1 X X X 1
0 0 0 X X No Change
0 0 1 1 0 0
0 0 1 1 1 1
0 0 1 0 X No Change
0 0 1 ↓ D D

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

Available Attributes
Allowed
Attribute Type Default Description
Values
INIT 1-Bit 1 or 0 0 Sets the initial value of
Q output after
configuration

VHDL Instantiation Template

-- LDCPE: Transparent latch with with Asynchronous Reset, Preset and
-- Gate Enable. All families.
-- Xilinx HDL Libraries Guide version 8.1i

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LDCPE

LDCPE_inst : LDCPE
generic map (
INIT => '0') -- Initial value of the latch
port map (
Q => Q, -- Data output
CLR => CLR, -- Asynchronous clear/reset input
D => D, -- Data input
G => G, -- Gate input
GE => GE, -- Gate enable input
);

-- End of LDCPE_inst instantiation

Verilog Instantiation Template

// LDCPE : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (LDCPE_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. Delete or comment
// : out inputs/outs that are not necessary.

// <-----Cut code below this line---->

// LDCPE: Transparent latch with with Asynchronous Reset, Preset and

// Gate Enable. All families.
// Xilinx HDL Libraries Guide Version 8.1i

LDCPE #(
.INIT(1'b0) // Initial value of latch (1'b0 or 1'b1)
) LDCPE_inst (
.Q(Q), // Data output
.CLR(CLR), // Asynchronous clear/reset input
.D(D), // Data input
.G(G), // Gate input
.GE(GE), // Gate enable input
.PRE(PRE) // Asynchronous preset/set input
);

// End of LDCPE_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

56 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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LUT1, 2, 3, 4

LUT1, 2, 3, 4
Primitive: 1-, 2-, 3-, 4-Bit Look-Up-Table with General Output

LUT1, LUT2, LUT3, and LUT4 are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables
LUT1 (LUTs) with general output (O).

O A mandatory INIT attribute, with an appropriate number of hexadecimal digits for

I0 the number of inputs, must be attached to the LUT to specify its function.

X9852
LUT1 provides a look-up-table version of a buffer or inverter.
LUTs are the basic Spartan-3E building blocks. Two LUTs are available in each CLB
I1 LUT2 slice; four LUTs are available in each CLB. The variants, “LUT1_D, LUT2_D, LUT3_D,
O LUT4_D”and “LUT1_L, LUT2_L, LUT3_L, LUT4_L”provide additional types of
I0
outputs that can be used by different timing models for more accurate pre-layout
timing estimation.
X8379 LUT3 Function Table

Inputs Outputs
I2 LUT3
I1 I2 I1 I0 O
I0 O
0 0 0 INIT[0]
X8382 0 0 1 INIT[1]
0 1 0 INIT[2]
0 1 1 INIT[3]
I3 LUT4
1 0 0 INIT[4]
I2
I1
O 1 0 1 INIT[5]
I0 1 1 0 INIT[6]
1 1 1 INIT[7]
X8385
INIT = binary equivalent of the hexadecimal number assigned to the INIT attribute

Usage
LUTs are inferred with the logic portions of the HDL code. Xilinx suggests that you
instantiate LUTs only if you have a need to implicitly specify the logic mapping, or if
you need to manually place or relationally place the logic.

Available Attributes
LUT1

Attribute Type Allowed Values Default Description

INIT 2-Bit 2-Bit Hexadecimal 2'h0 Initializes ROMs,
Hexadeci RAMs, registers, and
mal look-up tables.

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LUT1, 2, 3, 4

LUT2

Attribute Type Allowed Values Default Description

INIT 4-Bit 4-Bit Hexadecimal 4'h0 Initializes ROMs,
Hexadeci RAMs, registers, and
mal look-up tables.

LUT3

Attribute Type Allowed Values Default Description

INIT 8-Bit 8-Bit Hexadecimal 8'h00 Initializes ROMs,
Hexadeci RAMs, registers, and
mal look-up tables.

LUT4

Attribute Type Allowed Values Default Description

INIT 16-Bit 16-Bit Hexadecimal 16'h0000 Initializes ROMs,
Hexadeci RAMs, registers, and
mal look-up tables.

VHDL Instantiation Template for LUT1

-- LUT1 : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (LUT1_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- LUT1: 1-input Look-Up Table with general output

-- Xilinx HDL Libraries Guide Version 8.1i

LUT1_inst : LUT1
generic map (
INIT => "00")
port map (
O => O, -- LUT general output
I0 => I0 -- LUT input
);

-- End of LUT1_inst instantiation

Verilog Instantiation Template For LUT1

// LUT1 : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (LUT1_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

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LUT1, 2, 3, 4

// <-----Cut code below this line---->

// LUT1: 1-input Look-Up Table with general output

// For use with all FPGAs.
// Xilinx HDL Libraries Guide Version 8.1i

LUT1 #(
.INIT(2'b00) // Specify LUT Contents
) LUT1_inst (
.O(O), // LUT general output
.I0(I0) // LUT input
);

// End of LUT1_inst instantiation

VHDL Instantiation Template for LUT2

-- LUT2 : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (LUT2_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- LUT2: 2-input Look-Up Table with general output

-- Xilinx HDL Libraries Guide Version 8.1i

LUT2_inst : LUT2
generic map (
INIT => X"0")
port map (
O => O, -- LUT general output
I0 => I0, -- LUT input
I1 => I1 -- LUT input
);

-- End of LUT2_inst instantiation

Verilog Instantiation Template for LUT2

// LUT2 : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (LUT2_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// LUT2: 2-input Look-Up Table with general output

// For use with all FPGAs.
// Xilinx HDL Libraries Guide Version 8.1i

LUT2 #(
.INIT(4'h0) // Specify LUT Contents
) LUT2_inst (
.O(O), // LUT general output

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LUT1, 2, 3, 4

.I0(I0), // LUT input

.I1(I1) // LUT input
);

// End of LUT2_inst instantiation

VHDL Instantiation Template for LUT3

-- LUT3 : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (LUT3_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- LUT3: 3-input Look-Up Table with general output

-- Xilinx HDL Libraries Guide Version 8.1i

LUT3_inst : LUT3
generic map (
INIT => X"00")
port map (
O => O, -- LUT general output
I0 => I0, -- LUT input
I1 => I1, -- LUT input
I2 => I2 -- LUT input
);

-- End of LUT3_inst instantiation

Verilog Instantiation Template For LUT3

// LUT3 : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (LUT3_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// LUT3: 3-input Look-Up Table with general output

// For use with all FPGAs.
// Xilinx HDL Libraries Guide Version 8.1i

LUT3 #(
.INIT(8'h00) // Specify LUT Contents
) LUT3_inst (
.O(O), // LUT general output
.I0(I0), // LUT input
.I1(I1), // LUT input
.I2(I2) // LUT input
);

// End of LUT3_inst instantiation

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LUT1, 2, 3, 4

VHDL Instantiation Template for LUT4

-- LUT4 : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (LUT4_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- LUT4: 4-input Look-Up Table with general output

-- Xilinx HDL Libraries Guide Version 8.1i

LUT4_inst : LUT4
generic map (
INIT => X"0000")
port map (
O => O, -- LUT general output
I0 => I0, -- LUT input
I1 => I1, -- LUT input
I2 => I2, -- LUT input
I3 => I3 -- LUT input
);

-- End of LUT4_inst instantiation

Verilog Instantiation Template For LUT4

// LUT4 : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (LUT4_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// LUT4: 4-input Look-Up Table with general output

// For use with all FPGAs.
// Xilinx HDL Libraries Guide Version 8.1i

LUT4 #(
.INIT(16'h0000) // Specify LUT Contents
) LUT4_inst (
.O(O), // LUT general output
.I0(I0), // LUT input
.I1(I1), // LUT input
.I2(I2), // LUT input
.I3(I3) // LUT input
);

// End of LUT4_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

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LUT1, 2, 3, 4

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LUT1_L, LUT2_L, LUT3_L, LUT4_L

LUT1_L, LUT2_L, LUT3_L, LUT4_L

Primitive: 1-, 2-, 3-, 4-Bit Look-Up-Table with Local Output

LUT1_L, LUT2_L, LUT3_L, and LUT4_L are, respectively, 1-, 2-, 3-, and 4- bit look-up-
LUT1_L LO
tables (LUTs) with a local output (LO) that connects to another output within the
same CLB slice and to the fast-connect buffer.
I0
A mandatory INIT attribute, with an appropriate number of hexadecimal digits for
X8378
the number of inputs, must be attached to the LUT to specify its function.
LUT1_L provides a look-up-table version of a buffer or inverter.

I1 LUT2_L LO
See also “LUT1, 2, 3, 4”and “LUT1_D, LUT2_D, LUT3_D, LUT4_D”
LUT3_L Function Table
I0

Inputs Outputs
X8381

I2 I1 I0 LO

I2 LUT3_L LO
0 0 0 INIT[0]
I1 0 0 1 INIT[1]
I0 0 1 0 INIT[2]
0 1 1 INIT[3]
X8384
1 0 0 INIT[4]
1 0 1 INIT[5]
I3 LUT4_L
I2
LO
1 1 0 INIT[6]
I1
I0
1 1 1 INIT[7]
INIT = binary equivalent of the hexadecimal number assigned to the INIT attribute
X8387

Usage
LUTs are inferred with the logic portions of the HDL code. Xilinx suggests that you
instantiate LUTs only if you have a need to implicitly specify the logic mapping, or if
you need to manually place or relationally place the logic.

Available Attributes
LUT1_L

Attribute Type Allowed Values Default Description

INIT 2-Bit 2-Bit Hexadecimal 2'h0 Initializes ROMs, RAMs,
Hexadeci registers, and look-up
mal tables.
LUT2_L

Attribute Type Allowed Values Default Description

INIT 4-Bit 4-Bit Hexadecimal 4'h0 Initializes ROMs,
Hexadeci RAMs, registers, and
mal look-up tables.

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LUT1_L, LUT2_L, LUT3_L, LUT4_L

LUT3_L

Attribute Type Allowed Values Default Description

INIT 8-Bit 8-Bit Hexadecimal 8'h00 Initializes ROMs, RAMs,
Hexadeci registers, and look-up tables.
mal
LUT4_L

Attribute Type Allowed Values Default Description

INIT 16-Bit 16-Bit Hexadecimal 16'h0000 Initializes ROMs, RAMs,
Hexadeci registers, and look-up
mal tables.

VHDL Instantiation Template for LUT1_L

-- LUT1_L : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (LUT1_L_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- LUT1_L: 1-input Look-Up Table with local output

-- Xilinx HDL Libraries Guide Version 8.1i

LUT1_L_inst : LUT1_L
generic map (
INIT => "00")
port map (
LO => LO, -- LUT local output
I0 => I0 -- LUT input
);

-- End of LUT1_L_inst instantiation

Verilog Instantiation Template For LUT1_L

// LUT1_L : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (LUT1_L_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// LUT1_L: 1-input Look-Up Table with local output

// For use with all FPGAs.
// Xilinx HDL Libraries Guide Version 8.1i

LUT1_L #(
.INIT(2'b00) // Specify LUT Contents
) LUT1_L_inst (

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LUT1_L, LUT2_L, LUT3_L, LUT4_L

.LO(LO), // LUT local output

.I0(I0) // LUT input
);

// End of LUT1_L_inst instantiation

VHDL Instantiation Template for LUT2_L

-- LUT2_L : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (LUT2_L_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- LUT2_L: 2-input Look-Up Table with local output

-- Xilinx HDL Libraries Guide Version 8.1i

LUT2_L_inst : LUT2_L
generic map (
INIT => X"0")
port map (
LO => LO, -- LUT local output
I0 => I0, -- LUT input
I1 => I1 -- LUT input
);

-- End of LUT2_L_inst instantiation

Verilog Instantiation Template For LUT2_L

// LUT2_L : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (LUT2_L_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// LUT2_L: 2-input Look-Up Table with local output

// For use with all FPGAs.
// Xilinx HDL Libraries Guide Version 8.1i

LUT2_L #(
.INIT(4'h0) // Specify LUT Contents
) LUT2_L_inst (
.LO(LO), // LUT local output
.I0(I0), // LUT input
.I1(I1) // LUT input
);

// End of LUT2_L_inst instantiation

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LUT1_L, LUT2_L, LUT3_L, LUT4_L

VHDL Instantiation Template for LUT3_L

-- LUT3_L : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (LUT3_L_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- LUT3_L: 3-input Look-Up Table with local output

-- Xilinx HDL Libraries Guide Version 8.1i

LUT3_L_inst : LUT3_L
generic map (
INIT => X"00")
port map (
LO => LO, -- LUT local output
I0 => I0, -- LUT input
I1 => I1, -- LUT input
I2 => I2 -- LUT input
);

-- End of LUT3_L_inst instantiation

Verilog Instantiation Template For LUT3_L

// LUT3_L : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (LUT3_L_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// LUT3_L: 3-input Look-Up Table with local output

// For use with all FPGAs.
// Xilinx HDL Libraries Guide Version 8.1i

LUT3_L #(
.INIT(8'h00) // Specify LUT Contents
) LUT3_L_inst (
.LO(LO), // LUT local output
.I0(I0), // LUT input
.I1(I1), // LUT input
.I2(I2) // LUT input
);

// End of LUT3_L_inst instantiation

VHDL Instantiation Template for LUT4_L

-- LUT4_L : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (LUT4_L_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly

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LUT1_L, LUT2_L, LUT3_L, LUT4_L

-- : reference and connect this function to the design.

-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- LUT4_L: 4-input Look-Up Table with local output

-- Xilinx HDL Libraries Guide Version 8.1i

LUT4_L_inst : LUT4_L
generic map (
INIT => X"0000")
port map (
LO => LO, -- LUT local output
I0 => I0, -- LUT input
I1 => I1, -- LUT input
I2 => I2, -- LUT input
I3 => I3 -- LUT input
);

-- End of LUT4_L_inst instantiation

Verilog Instantiation Template For LUT4_L

// LUT4_L : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (LUT4_L_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// LUT4_L: 4-input Look-Up Table with local output

// For use with all FPGAs.
// Xilinx HDL Libraries Guide Version 8.1i

LUT4_L #(
.INIT(16'h0000) // Specify LUT Contents
) LUT4_L_inst (
.LO(LO), // LUT local output
.I0(I0), // LUT input
.I1(I1), // LUT input
.I2(I2), // LUT input
.I3(I3) // LUT input
);

// End of LUT4_L_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

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LUT1_L, LUT2_L, LUT3_L, LUT4_L

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LUT1_D, LUT2_D, LUT3_D, LUT4_D

LUT1_D, LUT2_D, LUT3_D, LUT4_D

Primitive: 1-, 2-, 3-, 4-Bit Look-Up-Table with Dual Output

LUT1_D LO LUT1_D, LUT2_D, LUT3_D, and LUT4_D are, respectively, 1-, 2-, 3-, and 4-bit look-
up-tables (LUTs) with two functionally identical outputs, O and LO. The O output is a
I0 O general interconnect. The LO output is connects to another output within the same
CLB slice and to the fast connect buffer.
X8377
A mandatory INIT attribute, with an appropriate number of hexadecimal digits for
the number of inputs, must be attached to the LUT to specify its function.
I1 LUT2_D LO
LUT1_D provides a look-up-table version of a buffer or inverter.
I0 O See also “LUT1, 2, 3, 4”and“LUT1_L, LUT2_L, LUT3_L, LUT4_L”

X8380
LUT3_D Function Table

Inputs Outputs
I2 LUT3_D LO
I2 I1 I0 O LO
I1
I0 O 0 0 0 INIT[0] INIT[0]
0 0 1 INIT[1] INIT[1]
X8383
0 1 0 INIT[2] INIT[2]
0 1 1 INIT[3] INIT[3]
LUT4_D
I3 1 0 0 INIT[4] INIT[4]
I2 LO
I1 O
1 0 1 INIT[5] INIT[5]
I0 1 1 0 INIT[6] INIT[6]
1 1 1 INIT[7] INIT[7]
X8386
INIT = binary equivalent of the hexadecimal number assigned to the INIT attribute

Usage
LUTs are inferred with the logic portions of the HDL code. Xilinx suggests that you
instantiate LUTs only if you have a need to implicitly specify the logic mapping, or if
you need to manually place or relationally place the logic.

Available Attributes
LUT1_D

Attribute Type Allowed Values Default Description

INIT 2-Bit 2-Bit Hexadecimal 2'h0 Initializes ROMs,
Hexadeci RAMs, registers, and
mal look-up tables.
LUT2_D

Attribute Type Allowed Values Default Description

INIT 4-Bit 4-Bit Hexadecimal 4'h0 Initializes ROMs,
Hexadeci RAMs, registers, and
mal look-up tables.

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LUT1_D, LUT2_D, LUT3_D, LUT4_D

LUT3_D

Attribute Type Allowed Values Default Description

INIT 8-Bit 8-Bit Hexadecimal 8'h00 Initializes ROMs, RAMs,
Hexadeci registers, and look-up
mal tables.
LUT4_D

Attribute Type Allowed Values Default Description

INIT 16-Bit 16-Bit Hexadecimal 16'h0000 Initializes ROMs, RAMs,
Hexadeci registers, and look-up
mal tables.

VHDL Instantiation Template for LUT1_D

-- LUT1_D : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (LUT1_D_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- LUT1_D: 1-input Look-Up Table with general and local outputs

-- Xilinx HDL Libraries Guide Version 8.1i

LUT1_D_inst : LUT1_D
generic map (
INIT => "00")
port map (
LO => LO, -- LUT local output
O => O, -- LUT general output
I0 => I0 -- LUT input
);

-- End of LUT1_D_inst instantiation

Verilog Instantiation Template For LUT1_D

// LUT1_D : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (LUT1_D_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// LUT1_D: 1-input Look-Up Table with general and local outputs

// For use with all FPGAs.
// Xilinx HDL Libraries Guide Version 8.1i

LUT1_D #(
.INIT(2'b00) // Specify LUT Contents

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LUT1_D, LUT2_D, LUT3_D, LUT4_D

) LUT1_D_inst (
.LO(LO), // LUT local output
.O(O), // LUT general output
.I0(I0) // LUT input
);

// End of LUT1_D_inst instantiation

VHDL Instantiation Template for LUT2_D

-- LUT2_D : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (LUT2_D_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- LUT2_D: 2-input Look-Up Table with general and local outputs

-- Xilinx HDL Libraries Guide Version 8.1i

LUT2_D_inst : LUT2_D
generic map (
INIT => X"0")
port map (
LO => LO, -- LUT local output
O => O, -- LUT general output
I0 => I0, -- LUT input
I1 => I1 -- LUT input
);

-- End of LUT2_D_inst instantiation

Verilog Instantiation Template For LUT2_D

// LUT2_D : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (LUT2_D_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// LUT2_D: 2-input Look-Up Table with general and local outputs

// For use with all FPGAs.
// Xilinx HDL Libraries Guide Version 8.1i

LUT2_D #(
.INIT(4'h0) // Specify LUT Contents
) LUT2_D_inst (
.LO(LO), // LUT local output
.O(O), // LUT general output
.I0(I0), // LUT input
.I1(I1) // LUT input
);

// End of LUT2_L_inst instantiation

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LUT1_D, LUT2_D, LUT3_D, LUT4_D

VHDL Instantiation Template for LUT3_D

-- LUT3_D : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (LUT3_D_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- LUT3_D: 3-input Look-Up Table with general and local outputs

-- Xilinx HDL Libraries Guide Version 8.1i

LUT3_D_inst : LUT3_D
generic map (
INIT => X"00")
port map (
LO => LO, -- LUT local output
O => O, -- LUT general output
I0 => I0, -- LUT input
I1 => I1, -- LUT input
I2 => I2 -- LUT input
);

-- End of LUT3_D_inst instantiation

Verillog Instantiation Template for LUT3_D

// LUT3_D : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (LUT3_D_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// LUT3_D: 3-input Look-Up Table with general and local outputs

// For use with all FPGAs.
// Xilinx HDL Libraries Guide Version 8.1i

LUT3_D #(
.INIT(8'h00) // Specify LUT Contents
) LUT3_D_inst (
.LO(LO), // LUT local output
.O(O), // LUT general output
.I0(I0), // LUT input
.I1(I1), // LUT input
.I2(I2) // LUT input
);

// End of LUT3_D_inst instantiation

VHDL Instantiation Template for LUT4_D

-- LUT4_D : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (LUT4_D_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly

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LUT1_D, LUT2_D, LUT3_D, LUT4_D

-- : reference and connect this function to the design.

-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- LUT4_D: 4-input Look-Up Table with general and local outputs

-- Xilinx HDL Libraries Guide Version 8.1i

LUT4_D_inst : LUT4_D
generic map (
INIT => X"0000")
port map (
LO => LO, -- LUT local output
O => O, -- LUT general output
I0 => I0, -- LUT input
I1 => I1, -- LUT input
I2 => I2, -- LUT input
I3 => I3 -- LUT input
);

-- End of LUT4_D_inst instantiation

Verilog Instantiation Template For LUT4_D

// LUT4_D : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (LUT4_D_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// LUT4_D: 4-input Look-Up Table with general and local outputs

// For use with all FPGAs.
// Xilinx HDL Libraries Guide Version 8.1i

LUT4_D #(
.INIT(16'h0000) // Specify LUT Contents
) LUT4_D_inst (
.LO(LO), // LUT local output
.O(O), // LUT general output
.I0(I0), // LUT input
.I1(I1), // LUT input
.I2(I2), // LUT input
.I3(I3) // LUT input
);

// End of LUT4_D_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

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LUT1_D, LUT2_D, LUT3_D, LUT4_D

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MULT_AND

MULT_AND
Primitive: Fast Multiplier AND

MULT_AND is a logical AND gate component that can be used to reduce logic and
improve speed when the user is building soft multipliers within the device fabric. It
can also be used in some carry-chain operations to reduce the needed LUTs to
I1 implement some functions. The I1 and I0 inputs must betconnected to the I1 and I0
LO
I0 inputs of the associated LUT. The LO output must be connected to the DI input of the
associated MUXCY, MUXCY_D, or MUXCY_L.
X8405 Inputs Output

I1 I0 LO
0 0 0
0 1 0
1 0 0
1 1 1

LO MUXCY_L
S
0 1
DI CI
LUT4

B1 I3
A1 I2
LI SUM1
B0 I1 O O
CI
A0 IO
XORCY

I1
LO
I0
MULT_AND

CO
X8733

Example Multiplier Using MULT_AND

Usage
This design element can be instantiated and inferred.

VHDL Instantiation Template

-- MULT_AND : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (MULT_AND_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

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MULT_AND

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- MULT_AND: 2-input AND gate connected to Carry chain

-- All FPGA
-- Xilinx HDL Libraries Guide Version 8.1i

MULT_AND_inst : MULT_AND
port map (
LO => LO, -- MULT_AND output (connect to MUXCY DI)
I0 => I0, -- MULT_AND data[0] input
I1 => I1 -- MULT_AND data[1] input
);

-- End of MULT_AND_inst instantiation

Verilog Instantiation Template

// MULT_AND : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (MULT_AND_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// MULT_AND: 2-input AND gate connected to Carry chain

// For use with All FPGAs
// Xilinx HDL Libraries Guide Version 8.1i

MULT_AND MULT_AND_inst (
.LO(LO), // MULT_AND output (connect to MUXCY DI)
.I0(I0), // MULT_AND data[0] input
.I1(I1) // MULT_AND data[1] input
);

// End of MULT_AND_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

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MULT18X18SIO

MULT18X18SIO
Primitive: 18x18 Cascadable Signed Multiplier with Optional Input and
Output registers, Clock Enable, and Synchronous Reset
The MULT18X18SIO is a 36-bit output, 18x18-bit input dedicated signed multiplier.
This component can perform asynchronous multiplication operations when the
A(17:0) MULT18X18SIO P(35:0)

B(17:0) attributes AREG, BREG and PREG are all set to 0. Alternatively, synchronous
CEA

CEB
multiplication operations of different latency and performance characteristics can be
CEP performed when any combination of those attributes is set to 1. When using the
CLK
RSTA multiplier in synchronous operation, the MULT18X18SIO features active high clock
RSTB
RSTP
enables for each set of register banks in the multiplier, CEA, CEB and CEP, as well as
BCIN(17:0) BCOUT(17:0)
synchronous resets, RSTA, RSTB, and RSTP. Multiple MULT18X18SIOs can be
X10238
cascaded to create larger multiplication functions using the BCIN and BCOUT ports
in combination with the B_INPUT attribute.

Usage
The MULT18X18SIO can be inferred by most synthesis tools using standard VHDL or
Verilog notation for multiplication. Alternatively, Core GeneratorTM System and other
IP can also create multiplication functions using this component. If preferred, the
MULT18X18SIO can be instantiated into the VHDL or Verilog code to give full control
over the implementation of the component. To change the default behavior of the
MULT18X18SIO, attributes can be modified via the generic map (VHDL) or named
parameter value assignment (Verilog) as a part of the instantiated component.

Available Attributes
Allowed
Attribute Type Default Description
Values
AREG Integer 1 or 0 1 Enable the input registers on the A port
(1=on, 0=off).
B_INPUT String "DIRECT" or "DIREC B input from B(17:0) (DIRECT) or from
"CASCADE” T” BCIN (17:0) (CASCADE).
BREG Integer 1 or 0 1 Enable the input registers on the B port
(1=on, 0=off).
PREG Integer 1 or 0 1 Enable the output registers on the P
port (1=on, 0=off).

VHDL Instantiation Template

-- MULT18X18SIO : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (MULT18X18SIO_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the

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MULT18X18SIO

-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- MULT18X18SIO: 18 x 18 cascadable, signed synchronous/asynchronous multiplier

-- Spartan-3E
-- Xilinx HDL Libraries Guide version 8.1i

MULT18X18SIO_inst : MULT18X18SIO
generic map (
AREG => 1, -- Enable the input registers on the A port (1=on, 0=off)
BREG => 1, -- Enable the input registers on the B port (1=on, 0=off)
B_INPUT => "DIRECT", -- B cascade input "DIRECT" or "CASCADE"
PREG => 1) -- Enable the input registers on the P port (1=on, 0=off)
port map (
BCOUT => BCOUT, -- 18-bit cascade output
P => P, -- 36-bit multiplier output
A => A, -- 18-bit multiplier input
B => B, -- 18-bit multiplier input
BCIN => BCIN, -- 18-bit cascade input
CEA => CEA, -- Clock enable input for the A port
CEB => CEB, -- Clock enable input for the B port
CEP => CEP, -- Clock enable input for the P port
CLK => CLK, -- Clock input
RSTA => RSTA, -- Synchronous reset input for the A port
RSTB => RSTB, -- Synchronous reset input for the B port
RSTP => RSTP, -- Synchronous reset input for the P port
);

-- End of MULT18X18SIO_inst instantiation

Verilog Instantiation Template

// MULT18X18SIO : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (MULT18X18SIO_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// MULT18X18SIO: 18 x 18 cascadable, signed synchronous/asynchronous multiplier

// Spartan-3E
// Xilinx HDL Libraries Guide Version 8.1i

MULT18X18SIO #(
.AREG(1), // Enable the input registers on the A port (1=on, 0=off)
.BREG(1), // Enable the input registers on the B port (1=on, 0=off)
.B_INPUT("DIRECT"), // B cascade input "DIRECT" or "CASCADE"
.PREG(1) // Enable the input registers on the P port (1=on, 0=off)
) MULT18X18SIO_inst (
.BCOUT(BCOUT), // 18-bit cascade output
.P(P), // 36-bit multiplier output
.A(A), // 18-bit multiplier input
.B(B), // 18-bit multiplier input
.BCIN(BCIN), // 18-bit cascade input
.CEA(CEA), // Clock enable input for the A port
.CEB(CEB), // Clock enable input for the B port
.CEP(CEP), // Clock enable input for the P port
.CLK(CLK), // Clock input
.RSTA(RSTA), // Synchronous reset input for the A port
.RSTB(RSTB), // Synchronous reset input for the B port
.RSTP(RSTP) // Synchronous reset input for the P port
);

// End of MULT18X18SIO_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

78 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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MUXCY

MUXCY
Primitive: 2-to-1 Multiplexer for Carry Logic with General Output

MUXCY implements a 1-bit high-speed carry propagate function. One such function
O
can be implemented per logic cell (LC), for a total of 8 bits per configurable logic block
S (CLB) for Spartan-3E.
MUXCY
0 1 The direct input (DI) of a slice is connected to the DI input of the MUXCY. The carry in
(CI) input of an LC is connected to the CI input of the MUXCY. The select input (S) of
DI CI the MUXCY is driven by the output of the lookup table (LUT) and configured as a
X8728 MUX function. The carry out (O) of the MUXCY reflects the state of the selected input
and implements the carry out function of each LC. When Low, S selects DI; when set
to High, S selects CI.
The variants, “MUXCY_D”and “MUXCY_L”provide additional types of outputs that
can be used by different timing models for more accurate pre-layout timing
estimation.

Inputs Outputs

S DI CI O
0 1 X 1
0 0 X 0
1 X 1 1
1 X 0 0

Usage
This design element can be instantiated and inferred.

VHDL Instantiation Template

-- MUXCY : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (MUXCY_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- MUXCY: Carry-Chain MUX with general output

-- Xilinx HDL Libraries Guide Version 8.1i

MUXCY_inst : MUXCY
port map (
O => O, -- Carry output signal

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MUXCY

CI => CI, -- Carry input signal

DI => DI, -- Data input signal
S => S -- MUX select, tie to '1' or LUT4 out
);

-- End of MUXCY_inst instantiation

Verilog Instantiation Template

// MUXCY : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (MUXCY_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs and
// : and outputs of this primtive should be connected.

// <-----Cut code below this line---->

// MUXCY: Carry-Chain MUX with general output

// For use with All FPGAs
// Xilinx HDL Libraries Guide Version 8.1i

MUXCY MUXCY_inst (
.O(O), // Carry output signal
.CI(CI), // Carry input signal
.DI(DI), // Data input signal
.S(S) // MUX select, tie to '1' or LUT4 out
);

// End of MUXCY_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

80 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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MUXCY_D

MUXCY_D
Primitive: 2-to-1 Multiplexer for Carry Logic with Dual Output

MUXCY_D implements a 1-bit high-speed carry propagate function. One such

LO O
function can be implemented per logic cell (LC), for a total of 4 bits per configurable
S logic block (CLB). The direct input (DI) of an LC is connected to the DI input of the
MUXCY_D
MUXCY_D. The carry in (CI) input of an LC is connected to the CI input of the
0 1
MUXCY_D. The select input (S) of the MUX is driven by the output of the lookup
table (LUT) and configured as an XOR function. The carry out (O and LO) of the
DI CI
MUXCY_D reflects the state of the selected input and implements the carry out
X8729 function of each LC. When Low, S selects DI; when High, S selects CI.
Outputs O and LO are functionally identical. The O output is a general interconnect.
The LO outputs connect to other inputs within the same slice.
See also “MUXCY”and “MUXCY_L”

Inputs Outputs

S DI CI O LO
0 1 X 1 1
0 0 X 0 0
1 X 1 1 1
1 X 0 0 0

Usage
This design element can only be instantiated. Synthesis tools use the MUXCY
primitive, then MAP uses the MUXCY_D.

VHDL Instantiation Template

-- MUXCY_D : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (MUXCY_D_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- MUXCY_D: Carry-Chain MUX with general and local outputs

-- Xilinx HDL Libraries Guide Version 8.1i

MUXCY_D_inst : MUXCY_D
port map (
LO => LO, -- Carry local output signal

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MUXCY_D

O => O, -- Carry general output signal

CI => CI, -- Carry input signal
DI => DI, -- Data input signal
S => S -- MUX select, tie to '1' or LUT4 out
);

-- End of MUXCY_D_inst instantiation

Verilog Instantiation Template

// MUXCY_D : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (MUXCY_D_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// MUXCY_D: Carry-Chain MUX with general and local outputs

// For use with All FPGAs
// Xilinx HDL Libraries Guide Version 8.1i

MUXCY_D MUXCY_D_inst (
.LO(LO), // Carry local output signal
.O(O), // Carry general output signal
.CI(CI), // Carry input signal
.DI(DI), // Data input signal
.S(S) // MUX select, tie to '1' or LUT4 out
);

// End of MUXCY_D_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

82 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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MUXCY_L

MUXCY_L
Primitive: 2-to-1 Multiplexer for Carry Logic with Local Output

MUXCY_L implements a 1-bit high-speed carry propagate function. One such

LO function can be implemented per slice, for a total of 4 bits per configurable logic block
S (CLB). The direct input (DI) of an LC is connected to the DI input of the MUXCY_L.
MUXCY_L The carry in (CI) input of an LC is connected to the CI input of the MUXCY_L. The
0 1
select input (S) of the MUXCY_L is driven by the output of the lookup table (LUT)
and configured as an XOR function. The carry out (LO) of the MUXCY_L reflects the
DI CI state of the selected input and implements the carry out function of each slice. When
X8730 Low, S selects DI; when High, S selects CI.
See also “MUXCY”and “MUXCY_D”

Inputs Outputs

S DI CI LO
0 1 X 1
0 0 X 0
1 X 1 1
1 X 0 0

Usage
This design element can only be instantiated. Synthesis tools use the MUXCY
primitive, then MAP uses the MUXCY_L.

VHDL Instantiation Template

-- MUXCY_L : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (MUXCY_L_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- MUXCY_L: Carry-Chain MUX with local output

-- Xilinx HDL Libraries Guide Version 8.1i

MUXCY_L_inst : MUXCY_L
port map (
LO => LO, -- Carry local output signal
CI => CI, -- Carry input signal
DI => DI, -- Data input signal
S => S -- MUX select, tie to '1' or LUT4 out
);

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MUXCY_L

-- End of MUXCY_L_inst instantiation

Verilog Instantiation Template

// MUXCY_L : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (MUXCY_L_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// MUXCY_L: Carry-Chain MUX with local output

// For use with All FPGAs
// Xilinx HDL Libraries Guide Version 8.1i

MUXCY_L MUXCY_L_inst (
.LO(LO), // Carry local output signal
.CI(CI), // Carry input signal
.DI(DI), // Data input signal
.S(S) // MUX select, tie to '1' or LUT4 out
);

// End of MUXCY_L_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

84 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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MUXF5

MUXF5
Primitive: 2-to-1 Look-Up Table Multiplexer with General Output

MUXF5 provides a multiplexer function in a CLB slice for creating a function-of-5

lookup table or a 4-to-1 multiplexer in combination with the associated lookup tables.
I0
The local outputs (LO) from the two lookup tables are connected to the I0 and I1
inputs of the MUXF5. The S input is driven from any internal net. When Low, S selects
O
I1 I0. When High, S selects I1.

S The variants, “MUXF5_D”and “MUXF5_L”, provide additional types of outputs that

X8431 can be used by different timing models for more accurate pre-layout timing
estimation.

Inputs Outputs

S I0 I1 O
0 1 X 1
0 0 X 0
1 X 1 1
1 X 0 0

Usage
This design element can be instantiated and inferred.

VHDL Instantiation Template

-- MUXF5 : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (MUXF5_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- MUXF5: Slice MUX to tie two LUT4's together with general output
-- Xilinx HDL Libraries Guide Version 8.1i

MUXF5_inst : MUXF5
port map (
O => O, -- Output of MUX to general routing
I0 => I0, -- Input (tie directly to the output of LUT4)
I1 => I1, -- Input (tie directoy to the output of LUT4)
S => S -- Input select to MUX
);

-- End of MUXF5_inst instantiation

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MUXF5

Verilog Instantiation Template

// MUXF5 : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (MUXF5_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// MUXF5: Slice MUX to tie two LUT4's together with general output
// For use with All FPGAs
// Xilinx HDL Libraries Guide Version 8.1i

MUXF5 MUXF5_inst (
.O(O), // Output of MUX to general routing
.I0(I0), // Input (tie directly to the output of LUT4)
.I1(I1), // Input (tie directoy to the output of LUT4)
.S(S) // Input select to MUX
);

// End of MUXF5_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

86 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

ISE 8.2i
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MUXF5_D

MUXF5_D
Primitive: 2-to-1 Look-Up Table Multiplexer with Dual Output

MUXF5_D provides a multiplexer function in a CLB slice for creating a function-of-5

I0 lookup table or a 4-to-1 multiplexer in combination with the associated lookup tables.
LO The local outputs (LO) from the two lookup tables are connected to the I0 and I1
O inputs of the MUXF5. The S input is driven from any internal net. When Low, S selects
I1 I0. When High, S selects I1.
S Outputs O and LO are functionally identical. The O output is a general interconnect.
X8432 The LO output is used to connect to other inputs within the same CLB slice.
See also “MUXF5”and “MUXF5_L”

Inputs Outputs

S I0 I1 O LO
0 1 X 1 1
0 0 X 0 0
1 X 1 1 1
1 X 0 0 0

Usage
This design element can only be instantiated. Synthesis tools use the MUXF5, then
MAP uses the MUXF5_D.

VHDL Instantiation Template

-- MUXF5_D : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (MUXF5_D_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- MUXF5_D: Slice MUX to tie two LUT4's together with general and local outputs
-- Xilinx HDL Libraries Guide Version 8.1i

MUXF5_D_inst : MUXF5_D
port map (
LO => LO, -- Ouptut of MUX to local routing
O => O, -- Output of MUX to general routing
I0 => I0, -- Input (tie directly to the output of LUT4)
I1 => I1, -- Input (tie directoy to the output of LUT4)
S => S -- Input select to MUX
);

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MUXF5_D

-- End of MUXF5_D_inst instantiation

Verilog Instantiation Template

// MUXF5_D : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (MUXF5_D_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// MUXF5_D: Slice MUX to tie two LUT4's together with general and local outputs
// For use with All FPGAs
// Xilinx HDL Libraries Guide Version 8.1i

MUXF5_D MUXF5_D_inst (
.LO(LO), // Ouptut of MUX to local routing
.O(O), // Output of MUX to general routing
.I0(I0), // Input (tie directly to the output of LUT4)
.I1(I1), // Input (tie directoy to the output of LUT4)
.S(S) // Input select to MUX
);

// End of MUXF5_D_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

88 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

ISE 8.2i
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MUXF5_L

MUXF5_L
Primitive: 2-to-1 Look-Up Table Multiplexer with Local Output

MUXF5_L provides a multiplexer function in a CLB slice for creating a function-of-5

lookup table or a 4-to-1 multiplexer in combination with the associated lookup tables.
I0
LO The local outputs (LO) from the two lookup tables are connected to the I0 and I1
inputs of the MUXF5. The S input is driven from any internal net. When Low, S selects
I1 I0. When High, S selects I1.

S The LO output is used to connect to other inputs within the same CLB slice.
X8433 See also “MUXF5”and “MUXF5_D”.

Inputs Output

S I0 I1 LO
0 1 X 1
0 0 X 0
1 X 1 1
1 X 0 0

Usage
This design element can only be instantiated. Synthesis tools use the MUXF5
primitive, then MAP uses the MUXF5_L.

VHDL Instantiation Template

-- MUXF5_L : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (MUXF5_L_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- MUXF5_L: Slice MUX to tie two LUT4's together with local output
-- Xilinx HDL Libraries Guide Version 8.1i

MUXF5_L_inst : MUXF5_L
port map (
LO => LO, -- Output of MUX to local routing
I0 => I0, -- Input (tie directly to the output of LUT4)
I1 => I1, -- Input (tie directoy to the output of LUT4)
S => S -- Input select to MUX
);

-- End of MUXF5_L_inst instantiation

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MUXF5_L

Verilog Instantiation Template

// MUXF5_L : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (MUXF5_L_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// MUXF5_L: Slice MUX to tie two LUT4's together with local output
// For use with All FPGAs
// Xilinx HDL Libraries Guide Version 8.1i

MUXF5_L MUXF5_L_inst (
.LO(LO), // Output of MUX to local routing
.I0(I0), // Input (tie directly to the output of LUT4)
.I1(I1), // Input (tie directoy to the output of LUT4)
.S(S) // Input select to MUX
);

// End of MUXF5_L_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

90 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

ISE 8.2i
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MUXF6

MUXF6

Primitive: 2-to-1 Look-Up Table Multiplexer with General Output

MUXF6 provides a multiplexer function in one half of a Spartan-3E CLB (two slices)
I0 for creating a function-of-6 lookup table or an 8-to-1 multiplexer in combination with
the associated four lookup tables and two MUXF5s. The local outputs (LO) from the
O two MUXF5s in the CLB are connected to the I0 and I1 inputs of the MUXF6. The S
I1
input is driven from any internal net. When Low, S selects I0. When High, S selects I1.
S
X8434 The variants, “MUXF6_D” and “MUXF6_L”, provide additional types of outputs that
can be used by different timing models for more accurate pre-layout timing
estimation.

Inputs Outputs

S I0 I1 O
0 1 X 1
0 0 X 0
1 X 1 1
1 X 0 0

Usage
This design element can only be instantiated.

VHDL Instantiation Template

-- MUXF6 : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (MUXF6_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- MUXF6: CLB MUX to tie two MUXF5's together with general output
-- Xilinx HDL Libraries Guide Version 8.1i

MUXF6_inst : MUXF6
port map (
O => O, -- Output of MUX to general routing
I0 => I0, -- Input (tie to MUXF5 LO out)
I1 => I1, -- Input (tie to MUXF5 LO out)
S => S -- Input select to MUX
);

-- End of MUXF6_inst instantiation

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MUXF6

Verilog Instantiation Template

// MUXF6 : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (MUXF6_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// MUXF6: CLB MUX to tie two MUXF5's together with general output
// For use with All FPGAs
// Xilinx HDL Libraries Guide Version 8.1i

MUXF6 MUXF6_inst (
.O(O), // Output of MUX to general routing
.I0(I0), // Input (tie to MUXF5 LO out)
.I1(I1), // Input (tie to MUXF5 LO out)
.S(S) // Input select to MUX
);

// End of MUXF6_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

92 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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MUXF6_D

MUXF6_D
Primitive: 2-to-1 Look-Up Table Multiplexer with Dual Output

MUXF6_D provides a multiplexer function in two slices for creating a function-of-6

I0 lookup table or an 8-to-1 multiplexer in combination with the associated four lookup
LO tables and two MUXF5s. The local outputs (LO) from the two MUXF5s in the CLB are
connected to the I0 and I1 inputs of the MUXF6. The S input is driven from any
O
I1 internal net. When Low, S selects I0. When High, S selects I1.

S Outputs O and LO are functionally identical. The O output is a general interconnect.

X8435 The LO output is used to connect to other inputs within the same CLB slice.
See also “MUXF6”and “MUXF6_L”

Inputs Outputs

S I0 I1 O LO
0 1 X 1 1
0 0 X 0 0
1 X 1 1 1
1 X 0 0 0

Usage
This design element can only be instantiated.

VHDL Instantiation Template

-- MUXF6_D : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (MUXF6_D_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- MUXF6_D: CLB MUX to tie two MUXF5's together with general and local outputs
-- Xilinx HDL Libraries Guide Version 8.1i

MUXF6_D_inst : MUXF6_D
port map (
LO => LO, -- Ouptut of MUX to local routing
O => O, -- Output of MUX to general routing
I0 => I0, -- Input (tie to MUXF5 LO out)
I1 => I1, -- Input (tie to MUXF5 LO out)
S => S -- Input select to MUX
);

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MUXF6_D

-- End of MUXF6_D_inst instantiation

Verilog Instantiation Template

// MUXF6_D : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (MUXF6_D_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// MUXF6_D: CLB MUX to tie two MUXF5's together with general and local outputs
// For use with All FPGAs
// Xilinx HDL Libraries Guide Version 8.1i

MUXF6_D MUXF6_D_inst (
.LO(LO), // Ouptut of MUX to local routing
.O(O), // Output of MUX to general routing
.I0(I0), // Input (tie to MUXF5 LO out)
.I1(I1), // Input (tie to MUXF5 LO out)
.S(S) // Input select to MUX
);

// End of MUXF6_D_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

94 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

ISE 8.2i
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MUXF6_L

MUXF6_L
Primitive: 2-to-1 Look-Up Table Multiplexer with Local Output

MUXF6_L provides a multiplexer function in half of a Spartan-3E CLB (two slices) for
creating a function-of-6 lookup table or an 8-to-1 multiplexer in combination with the
I0
LO associated four lookup tables and two MUXF5s. The local outputs (LO) from the two
MUXF5s in the CLB are connected to the I0 and I1 inputs of the MUXF6. The S input is
I1 driven from any internal net. When Low, S selects I0. When High, S selects I1.

S The LO output is used to connect to other inputs within the same CLB slice.
X8436 See also “MUXF6”and “MUXF6_D”.

Inputs Output

S I0 I1 LO
0 1 X 1
0 0 X 0
1 X 1 1
1 X 0 0

Usage
This design element can only be instantiated.

VHDL Instantiation Template

-- MUXF6_L : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (MUXF6_L_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- MUXF6_L: CLB MUX to tie two MUXF5's together with local output
-- Xilinx HDL Libraries Guide Version 8.1i

MUXF6_L_inst : MUXF6_L
port map (
LO => LO, -- Output of MUX to local routing
I0 => I0, -- Input (tie to MUXF5 LO out)
I1 => I1, -- Input (tie to MUXF5 LO out)
S => S -- Input select to MUX
);

-- End of MUXF6_L_inst instantiation

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MUXF6_L

Verilog Instantiation Template

// MUXF6_L : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (MUXF6_L_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// MUXF6_L: CLB MUX to tie two MUXF5's together with local output
// For use with All FPGAs
// Xilinx HDL Libraries Guide Version 8.1i

MUXF6_L MUXF6_L_inst (
.LO(LO), // Output of MUX to local routing
.I0(I0), // Input (tie to MUXF5 LO out)
.I1(I1), // Input (tie to MUXF5 LO out)
.S(S) // Input select to MUX
);

// End of MUXF6_L_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

96 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

ISE 8.2i
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MUXF7

MUXF7
Primitive: 2-to-1 Look-Up Table Multiplexer with General Output

MUXF7 provides a multiplexer function in a full Spartan-3E CLB for creating a

function-of-7 lookup table or a 16-to-1 multiplexer in combination with the associated
I0
lookup tables. Local outputs (LO) of MUXF6 are connected to the I0 and I1 inputs of
the MUXF7. The S input is driven from any internal net. When Low, S selects I0. When
O High, S selects I1.
I1
S The variants, “MUXF7_D”and “MUXF7_L”, provide additional types of outputs that
X8431 can be used by different timing models for more accurate pre-layout timing
estimation.

Inputs Outputs

S I0 I1 O
0 I0 X I0
1 X I1 I1
X 0 0 0
X 1 1 1

Usage
This design element can only be instantiated.

VHDL Instantiation Template

-- MUXF7 : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (MUXF7_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- MUXF7: CLB MUX to tie two MUXF6's together with general output
-- Xilinx HDL Libraries Guide Version 8.1i

MUXF7_inst : MUXF7
port map (
O => O, -- Output of MUX to general routing
I0 => I0, -- Input (tie to MUXF6 LO out)
I1 => I1, -- Input (tie to MUXF6 LO out)
S => S -- Input select to MUX
);

-- End of MUXF7_inst instantiation

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MUXF7

Verilog Instantiation Template

// MUXF7 : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (MUXF7_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// MUXF7: CLB MUX to tie two MUXF6's together with general output
// For use with FPGA
// Xilinx HDL Libraries Guide Version 8.1i

MUXF7 MUXF7_inst (
.O(O), // Output of MUX to general routing
.I0(I0), // Input (tie to MUXF6 LO out)
.I1(I1), // Input (tie to MUXF6 LO out)
.S(S) // Input select to MUX
);

// End of MUXF7_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

98 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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MUXF7_D

MUXF7_D
Primitive: 2-to-1 Look-Up Table Multiplexer with Dual Output

MUXF7_D provides a multiplexer function in a full Spartan-3E CLB (four slices) for
creating a function-of-7 lookup table or a 16-to-1 multiplexer in combination with the
I0
LO associated lookup tables. Local outputs (LO) of MUXF6 are connected to the I0 and I1
inputs of the MUXF7. The S input is driven from any internal net. When Low, S selects
O I0. When High, S selects I1.
I1
S Outputs O and LO are functionally identical. The O output is a general interconnect.
X8432 The LO output connects to other inputs within the same CLB slice.
See also “MUXF7”and “MUXF7_L”.

Inputs Outputs

S I0 I1 O LO
0 I0 X I0 I0
1 X I1 I1 I1
X 0 0 0 0
X 1 1 1 1

Usage
This design element can only be instantiated.

VHDL Instantiation Template

-- MUXF7_D : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (MUXF7_D_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- MUXF7_D: CLB MUX to tie two MUXF6's together with general and local outputs
-- Xilinx HDL Libraries Guide Version 8.1i

MUXF7_D_inst : MUXF7_D
port map (
LO => LO, -- Ouptut of MUX to local routing
O => O, -- Output of MUX to general routing
I0 => I0, -- Input (tie to MUXF6 LO out)
I1 => I1, -- Input (tie to MUXF6 LO out)
S => S -- Input select to MUX
);

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MUXF7_D

-- End of MUXF7_D_inst instantiation

Verilog Instantiation Template

// MUXF7_D : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (MUXF7_D_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// MUXF7_D: CLB MUX to tie two MUXF6's together with general and local outputs
// For use with FPGAs.
// Xilinx HDL Libraries Guide Version 8.1i

MUXF7_D MUXF7_D_inst (
.LO(LO), // Ouptut of MUX to local routing
.O(O), // Output of MUX to general routing
.I0(I0), // Input (tie to MUXF6 LO out)
.I1(I1), // Input (tie to MUXF6 LO out)
.S(S) // Input select to MUX
);

// End of MUXF7_D_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

100 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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MUXF7_L

MUXF7_L
Primitive: 2-to-1 Look-Up Table Multiplexer with Local Output

MUXF7_L provides a multiplexer function in a full Spartan-3E CLB (four slices) for
I0 creating a function-of-7 lookup table or a 16-to-1 multiplexer in combination with the
LO associated lookup tables. Local outputs (LO) of MUXF6 are connected to the I0 and I1
inputs of the MUXF7. The S input is driven from any internal net. When Low, S selects
I1 I0. When High, S selects I1.
S The LO output is used to connect to other inputs within the same CLB slice.
X8433
See also “MUXF7”and “MUXF7_D”.

Inputs Output

S I0 I1 LO
0 I0 X I0
1 X I1 I1
X 0 0 0
X 1 1 1

Usage
This design element can only be instantiated.

VHDL Instantiation Template

-- MUXF7_L : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (MUXF7_L_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- MUXF7_L: CLB MUX to tie two MUXF6's together with local output
-- Xilinx HDL Libraries Guide Version 8.1i

MUXF7_L_inst : MUXF7_L
port map (
LO => LO, -- Output of MUX to local routing
I0 => I0, -- Input (tie to MUXF6 LO out)
I1 => I1, -- Input (tie to MUXF6 LO out)
S => S -- Input select to MUX
);

-- End of MUXF7_L_inst instantiation

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MUXF7_L

Verilog Instantiation Template

// MUXF7_L : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (MUXF7_L_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// MUXF7_L: CLB MUX to tie two MUXF6's together with local output
// For use with FPGAs.
// Xilinx HDL Libraries Guide Version 8.1i

MUXF7_L MUXF7_L_inst (
.LO(LO), // Output of MUX to local routing
.I0(I0), // Input (tie to MUXF6 LO out)
.I1(I1), // Input (tie to MUXF6 LO out)
.S(S) // Input select to MUX
);

// End of MUXF7_L_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

102 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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MUXF8

MUXF8
Primitive: 2-to-1 Look-Up Table Multiplexer with General Output

MUXF8 provides a multiplexer function in full Spartan-3E CLBs for creating a

function-of-8 lookup table or a 32-to-1 multiplexer in combination with the associated
I0 lookup tables, MUXF5s, MUXF6s, and MUXF7s. Local outputs (LO) of MUXF7 are
connected to the I0 and I1 inputs of the MUXF8. The (S) input is driven from any
O internal net. When Low, (S) selects I0. When High, (S) selects I1.
I1
S See also “MUXF8_D”and “MUXF8_L”.
X8434
Inputs Outputs

S I0 I1 O
0 I0 X I0
1 X I1 I1
X 0 0 0
X 1 1 1

Usage
This design element can only be instantiated.

VHDL Instantiation Template

-- MUXF8 : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (MUXF8_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- MUXF8: CLB MUX to tie two MUXF7's together with general output
-- Xilinx HDL Libraries Guide Version 8.1i

MUXF8_inst : MUXF8
port map (
O => O, -- Output of MUX to general routing
I0 => I0, -- Input (tie to MUXF7 LO out)
I1 => I1, -- Input (tie to MUXF7 LO out)
S => S -- Input select to MUX
);

-- End of MUXF8_inst instantiation

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MUXF8

Verilog Instantiation Template

// MUXF8 : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (MUXF8_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// MUXF8: CLB MUX to tie two MUXF7's together with general output
// For use with FPGAs.
// Xilinx HDL Libraries Guide Version 8.1i

MUXF8 MUXF8_inst (
.O(O), // Output of MUX to general routing
.I0(I0), // Input (tie to MUXF7 LO out)
.I1(I1), // Input (tie to MUXF7 LO out)
.S(S) // Input select to MUX
);

// End of MUXF8_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

104 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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MUXF8_D

MUXF8_D
Primitive: 2-to-1 Look-Up Table Multiplexer with Dual Output

MUXF8_D provides a multiplexer function in two full Spartan-3E CLBs for creating a
function-of-8 lookup table or a 32-to-1 multiplexer in combination with the associated
I0
LO four lookup tables and two MUXF8s. Local outputs (LO) of MUXF7 are connected to
the I0 and I1 inputs of the MUXF8. The (S) input is driven from any internal net. When
O
I1 Low, (S) selects I0. When High, (S) selects I1.
S Outputs O and LO are functionally identical. The O output is a general interconnect.
X8435 The LO output is used to connect to other inputs within the same CLB slice.
See also “MUXF8”and “MUXF8_L”.

Inputs Outputs

S I0 I1 O LO
0 I0 X I0 I0
1 X I1 I1 I1
X 0 0 0 0
X 1 1 1 1

Usage
This design element can only be instantiated.

VHDL Instantiation Template

-- MUXF8_D : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (MUXF8_D_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- MUXF8_D: CLB MUX to tie two MUXF7's together with general and local outputs
-- Xilinx HDL Libraries Guide Version 8.1i

MUXF8_D_inst : MUXF8_D
port map (
LO => LO, -- Ouptut of MUX to local routing
O => O, -- Output of MUX to general routing
I0 => I0, -- Input (tie to MUXF7 LO out)
I1 => I1, -- Input (tie to MUXF7 LO out)
S => S -- Input select to MUX
);

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MUXF8_D

-- End of MUXF8_D_inst instantiation

Verilog Instantiation Template

// MUXF8_D : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (MUXF8_D_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// MUXF8_D: CLB MUX to tie two MUXF7's together with general and local outputs
// For use with FPGAa,
// Xilinx HDL Libraries Guide Version 8.1i

MUXF8_D MUXF8_D_inst (
.LO(LO), // Ouptut of MUX to local routing
.O(O), // Output of MUX to general routing
.I0(I0), // Input (tie to MUXF7 LO out)
.I1(I1), // Input (tie to MUXF7 LO out)
.S(S) // Input select to MUX
);

// End of MUXF8_D_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

106 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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MUXF8_L

MUXF8_L
Primitive: 2-to-1 Look-Up Table Multiplexer with Local Output

MUXF8_L provides a multiplexer function in two full Spartan-3E CLBs for creating a
function-of-8 lookup table or a 32-to-1 multiplexer in combination with the associated
I0
LO four lookup tables and two MUXF8s. Local outputs (LO) of MUXF7 are connected to
the I0 and I1 inputs of the MUXF8. The S input is driven from any internal net. When
I1 Low, S selects I0. When High, S selects I1.
S The LO output connects to other inputs within the same CLB slice.
X8436
See also “MUXF8”and “MUXF8_D”.

Inputs Output

S I0 I1 LO
0 I0 X I0
1 X I1 I1
X 0 0 0
X 1 1 1

Usage
This design element can only be instantiated.

VHDL Instantiation Template

-- MUXF8_L : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (MUXF8_L_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- MUXF8_L: CLB MUX to tie two MUXF7's together with local output
-- Xilinx HDL Libraries Guide Version 8.1i

MUXF8_L_inst : MUXF8_L
port map (
LO => LO, -- Output of MUX to local routing
I0 => I0, -- Input (tie to MUXF7 LO out)
I1 => I1, -- Input (tie to MUXF7 LO out)
S => S -- Input select to MUX
);

-- End of MUXF8_L_inst instantiation

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MUXF8_L

Verilog Instantiation Template

// MUXF8_L : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (MUXF8_L_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// MUXF8_L: CLB MUX to tie two MUXF7's together with local output
// For use with FPGAs.
// Xilinx HDL Libraries Guide Version 8.1i

MUXF8_L MUXF8_L_inst (
.LO(LO), // Output of MUX to local routing
.I0(I0), // Input (tie to MUXF7 LO out)
.I1(I1), // Input (tie to MUXF7 LO out)
.S(S) // Input select to MUX
);

// End of MUXF8_L_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

108 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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OBUF

OBUF
Primitive: Single-ended Output Buffers

Output buffers are necessary for all output signals because they isolate the internal
circuit and provide drive current for signals leaving a chip. The OBUF is a constantly
OBUF enabled output buffer that specifies a single-ended output when a 3-state is not
I O necessary for the output. The output (O) of an OBUF should be connected directly to
the top-level ouput port in the design.

X9445 Usage
OBUFs are optional for use in schematics because they are automatically inserted into
a design, if necessary. To manually add this component, however, the component
should be placed in the top-level schematic connecting the output directly to an
output port marker.
OBUFs are available in bundles of 4, 8, or 16 to make it easier for you to incorporate
them into your design without having to apply multiples of them one at a time. (The
bundles are identified as OBUF4, OBUF8, and OBUF16.)

Available Attributes
Attribute Type Allowed Values Default Description
DRIVE Integer 2, 4, 6, 8, 12, 16, 12 Sets the output drive in
24 mA.
IOSTANDARD String "DEFAULT” "DEFAULT” Use to assign an I/O
standard to an I/O
primitive.
SLEW String "SLOW", "FAST”, "SLOW” Sets the output rise and fall
and “QUIETIO” time.

VHDL Instantiation Template

-- OBUF : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (OBUF_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : connect this function to the design. Delete or comment
-- : out inputs/outs that are not necessary.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- OBUF: Single-ended Output Buffer

-- All devices
-- Xilinx HDL Libraries Guide version 8.1i

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OBUF

OBUF_inst : OBUF
generic map (
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map (
O => O, -- Buffer output (connect directly to top-level port)
I => I -- Buffer input
);

-- End of OBUF_inst instantiation

Verilog Instantiation Template

// OBUF : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (OBUF_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. Delete or comment
// : out inputs/outs that are not necessary.

// <-----Cut code below this line---->

// OBUF: Single-ended Output Buffer

// All devices
// Xilinx HDL Libraries Guide Version 8.1i

OBUF #(
.DRIVE(12), // Specify the output drive strength
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
.SLEW("SLOW") // Specify the output slew rate
) OBUF_inst (
.O(O), // Buffer output (connect directly to top-level port)
.I(I) // Buffer input
);

// End of OBUF_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

110 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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OBUFDS

OBUFDS
Primitive: Differential Signaling Output Buffer with Selectable I/O
Interface

OBUFDS is a single output buffer that supports low-voltage, differential signaling

O
I (1.8v CMOS). OBUFDS isolates the internal circuit and provides drive current for
OB signals leaving the chip. Its output is represented as two distinct ports (O and OB),
one deemed the "master" and the other the "slave." The master and the slave are
OBUFDS
opposite phases of the same logical signal (for example, MYNET and MYNETB).
X9259
Inputs Outputs

I O OB
0 0 1
1 1 0

Usage
This design element should be instantiated rather than inferred.

Available Attributes
Attribute Type Allowed Values Default Description
IOSTANDARD String "DEFAULT” "DEFAULT” Use to assign an I/O standard
to an I/O primitive.

VHDL Instantiation Template

-- OBUFDS : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (OBUFDS_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : connect this function to the design. Delete or comment
-- : out inputs/outs that are not necessary.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- OBUFDS: Differential Output Buffer

-- FPGAs.
-- Xilinx HDL Libraries Guide version 8.1i

OBUFDS_inst : OBUFDS
generic map (
IOSTANDARD => "DEFAULT")
port map (
O => O, -- Diff_p output (connect directly to top-level port)
OB => OB, -- Diff_n output (connect directly to top-level port)

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OBUFDS

I => I -- Buffer input

);

-- End of OBUFDS_inst instantiation

Verilog Instantiation Template

// OBUFDS : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (OBUFDS_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. Delete or comment
// : out inputs/outs that are not necessary.

// <-----Cut code below this line---->

// OBUFDS: Differential Output Buffer

// Spartan-3/3E
// Xilinx HDL Libraries Guide Version 8.1i

OBUFDS #(
.IOSTANDARD("DEFAULT") // Specify the output I/O standard
) OBUFDS_inst (
.O(O), // Diff_p output (connect directly to top-level port)
.OB(OB), // Diff_n output (connect directly to top-level port)
.I(I) // Buffer input
);

// End of OBUFDS_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

112 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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OBUFT

OBUFT
Primitive: 3-State Output Buffer with Active-Low Output Enable
Output buffers are necessary for all output signals because they isolate the internal
OBUFT circuit and provide drive current for signals leaving a chip. The OBUFT is a 3-state
T output buffer with input I, output O, and active-Low output enables (T). When T is
I O Low, data on the inputs of the buffers is transferred to the corresponding outputs.
When T is High, the output is high impedance (off or Z state).

X9449 An OBUFT output should be connected directly to the top-level output or inout port.
OBUFTs are generally used when a single-ended output is needed with a 3-state
capability, such as the case when building bidirectional I/O.

Inputs Outputs

T I O
1 X Z
0 1 1
0 0 0

Usage
OBUFTs are generally inferred by the synthesis when an output port is specified to
have a high impedance, Z, as well as drive an output. It is generally suggested to
infer this element however if more control of the usage of this component is necessary,
it can be instantiated.

Available Attributes
Attribute Type Allowed Values Default Description
DRIVE Integer 2, 4, 6, 8, 12, 16, 24 12 Selects output drive
strength (mA) for the
SelectIO buffers that use
the LVTTL, LVCMOS12,
LVCMOS15, LVCMOS18,
LVCMOS25, or LVCMOS33
interface I/O standard.
IOSTANDARD String "DEFAULT” "DEFAULT” Use to assign an I/O
standard to an I/O
primitive.
SLEW String "SLOW" , "FAST”, "SLOW” Sets the output rise and fall
and “QUIETIO” time.

VHDL Instantiation Template

-- OBUFT : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (OBUFT_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : connect this function to the design. Delete or comment
-- : out inputs/outs that are not necessary.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be

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OBUFT

-- for : added before the entity declaration. This library

-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- OBUFT: Single-ended 3-state Output Buffer

-- All devices
-- Xilinx HDL Language Template version 7.1i

OBUFT_inst : OBUFT
generic map (
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map (
O => O, -- Buffer output (connect directly to top-level port)
I => I, -- Buffer input
T => T -- 3-state enable input
);

-- End of OBUFT_inst instantiation

Verilog Instantiation Template

// OBUFT : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (OBUFT_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. Delete or comment
// : out inputs/outs that are not necessary.

// <-----Cut code below this line---->

// OBUFT: Single-ended 3-state Output Buffer

// All devices
// Xilinx HDL Language Template version 7.1i

OBUFT #(
.DRIVE(12), // Specify the output drive strength
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
.SLEW("SLOW") // Specify the output slew rate
) OBUFT_inst (
.O(O), // Buffer output (connect directly to top-level port)
.I(I), // Buffer input
.T(T) // 3-state enable input
);

// End of OBUFT_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

114 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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OBUFTDS

OBUFTDS
Primitive: 3-State Differential Signaling Output Buffer with Active Low
Output Enable and Selectable I/O Interface

OBUFTDS is a single 3-state, differential signaling output buffer with active Low
T
enable and a Select I/O interface.
O
I
OB
When T is Low, data on the input of the buffer is transferred to the output (O) and
inverted output (OB). When T is High, both outputs are high impedance (off or Z
OBUFTDS state).
X9260
Inputs Outputs

I T O OB
X 1 Z Z
0 0 0 1
1 0 1 0

Usage
This design element is available for instantiation only.

Available Attributes
Attribute Type Allowed Values Default Description
DRIVE Integer 2, 4, 6, 8, 12, 16, 12 Selects output drive strength
24 (mA) for the SelectIO buffers
that use the LVTTL,
LVCMOS12, LVCMOS15,
LVCMOS18, LVCMOS25, or
LVCMOS33 interface I/O
standard.
IOSTANDARD String "DEFAULT” "DEFAULT” Use to assign an I/O standard
to an I/O primitive.
SLEW String "SLOW" or "SLOW” Sets the output rise and fall
"FAST” time.

VHDL Instantiation Template

-- OBUFTDS: Differential 3-state Output Buffer
-- All FPGA
-- Xilinx HDL Libraries Guide version 8.1i

OBUFTDS_inst : OBUFTDS
-- Edit the following generics to specify the I/O standard, drive and slew rate.
generic map (
DRIVE => 12,
IOSTANDARD => "LVDS_25",
SLEW => "SLOW")
port map (
O => O, -- Diff_p output (connect directly to top-level port)
OB => OB, -- Diff_n output (connect directly to top-level port)
I => I, -- Buffer input
T => T -- 3-state enable input
);

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OBUFTDS

-- End of OBUFTDS_inst instantiation

Verilog Instantiation Template

// OBUFTDS: Differential bidirectional Buffer
// All FPGAs
// Xilinx HDL Libraries Guide version 8.1i OBUFTDS OBUFTDS_inst ( .O(O),
// Buffer output .IO(IO), // Diff_p inout (connect directly to
// top-level port) .IOB(IOB),
// Diff_n inout (connect directly to
// top-level port) .I(I),
// Buffer input .T(T)
// 3-state enable input );
// Edit the following defparams to specify the I/O standard, drive and
// slew rate. If the instance name is change, that change needs to be
// reflecting the this defparam. defparam OBUFTDS_inst.DRIVE = 12; defparam OBUFTDS_inst.IOSTANDARD =
"LVDS_25"; defparam OBUFTDS_inst.SLEW = "SLOW";
// End of OBUFTDS_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

116 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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ODDR2

ODDR2
Primitive: Double Data Rate Output D Flip-Flop with Optional Data
Alignment, Clock Enable and Programmable Synchronous or
Asynchronous Set/Reset
The ODDR2 is an output double data rate (DDR) register useful in producing double
data-rate signals exiting the FPGA. The ODDR2 requires two clocks to be connected
ODDR2
D0
to the component, C0 and C1, so that data is provided at the positive edge of both C0
D1 Q

C0
and C1 clocks. The ODDR2 features an active high clock enable port, CE, which can
C1
be used to suspend the operation of the registers and both set and reset ports that can
CE be configured to be synchronous or asynchronous to the respective clocks. The
R ODDR2 has an optional alignment feature, which allows data to be captured by a
S
single clock yet clocked out by two clocks.
X10236

Usage
The ODDR2 must be instantiated to be incorporated into a design. To change the
default behavior of the ODDR2, attributes can be modified via the generic map
(VHDL) or named parameter value assignment (Verilog) as a part of the instantiated
component. The ODDR2 can be either connected directly to a top-level output port in
the design where an appropriate output buffer can be inferred or to an instantiated
OBUF, IOBUF, OBUFDS, OBUFTDS or IOBUFDS. All inputs and outputs of this
component should either be connected or properly tied off.

Available Attributes
Attribute Type Allowed Values Default Description
DDR_ String "NONE", "C0" or "NONE” Sets output alignment to
ALIGNMENT "C1” "NONE", "C0" or "C1."
INIT Integer 0 or 1 0 Sets initial state of the Q0
output to 0 or 1.
SRTYPE String "SYNC" or "SYNC” Specifies "SYNC" or
"ASYNC” "ASYNC" set/reset.

VHDL Instantiation Template

-- ODDR2 : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (ODDR2_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : connect this function to the design. All inputs
-- : and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

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ODDR2

-- ODDR2: Output Double Data Rate Output Register with Set, Reset
-- and Clock Enable. Spartan-3E
-- Xilinx HDL Libraries Guide version 8.1i

ODDR2_inst : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => Q, -- 1-bit output data
C0 => C0, -- 1-bit clock input
C1 => C1, -- 1-bit clock input
CE => CE, -- 1-bit clock enable input
D0 => D0, -- 1-bit data input (associated with C0)
D1 => D1, -- 1-bit data input (associated with C1)
R => R, -- 1-bit reset input
S => S -- 1-bit set input
);

-- End of ODDR2_inst instantiation

Verilog Instantiation Template

// ODDR2 : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (ODDR2_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. Delete or comment
// : out inputs/outs that are not necessary.

// <-----Cut code below this line---->

// ODDR2: Output Double Data Rate Output Register with Set, Reset
// and Clock Enable. Spartan-3E
// Xilinx HDL Libraries Guide Version 8.1i

ODDR2 #(
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_inst (
.Q(Q), // 1-bit DDR output data
.C0(C0), // 1-bit clock input
.C1(C1), // 1-bit clock input
.CE(CE), // 1-bit clock enable input
.D0(D0), // 1-bit data input (associated with C0)
.D1(D1), // 1-bit data input (associated with C1)
.R(R), // 1-bit reset input
.S(S) // 1-bit set input
);

// End of ODDR2_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

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PULLDOWN

PULLDOWN
Primitive: Resistor to GND

PULLDOWN resistor elements are connected to output, or bidirectional pads to

guarantee a logic Low level for nodes that might Float.

Usage
This design element is instantiated rather than inferred.
X3860

VHDL Instantiation Template

-- PULLDOWN : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (PULLDOWN_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : connect this function to the design. Delete or comment
-- : out inputs/outs that are not necessary.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- PULLDOWN: I/O Buffer Weak Pull-down

-- All FPGA
-- Xilinx HDL Libraries Guide version 8.1i

PULLDOWN_inst : PULLDOWN
port map (
O => O -- Pulldown output (connect directly to top-level port)
);

-- End of PULLDOWN_inst instantiation

Verilog Instantiation Template

// PULLDOWN : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (PULLDOWN_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. Delete or comment
// : out inputs/outs that are not necessary.

// <-----Cut code below this line---->

// PULLDOWN: I/O Buffer Weak Pull-down

// All FPGA
// Xilinx HDL Libraries Guide Version 8.1i

PULLDOWN PULLDOWN_inst (
.O(O), // Pulldown output (connect directly to top-level port)
);

// End of PULLDOWN_inst instantiation

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PULLDOWN

For More Information

Consult the Spartan-3E Data Sheet.

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PULLUP

PULLUP
Primitive: Resistor to VCC, Open-Drain, and 3-State Outputs

The pull-up elements establish a High logic level for open-drain elements and macros
when all the drivers are off.

Usage
X3861 This design element is instantiated rather than inferred.

VHDL Instantiation Template

-- PULLUP : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (PULLUP_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : connect this function to the design. Delete or comment
-- : out inputs/outs that are not necessary.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- PULLUP: I/O Buffer Weak Pull-up

-- All FPGA
-- Xilinx HDL Libraries Guide version 8.1i

PULLUP_inst : PULLUP
port map (
O => O -- Pullup output (connect directly to top-level port)
);

-- End of PULLUP_inst instantiation

Verilog Instantiation Template

// PULLUP : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (PULLUP_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. Delete or comment
// : out inputs/outs that are not necessary.

// <-----Cut code below this line---->

// PULLUP: I/O Buffer Weak Pull-up

// All FPGA
// Xilinx HDL Libraries Guide Version 8.1i

PULLUP PULLUP_inst (
.O(O), // Pullup output (connect directly to top-level port)
);

// End of PULLUP_inst instantiation

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PULLUP

For More Information

Consult the Spartan-3E Data Sheet.

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RAM16X1D

RAM16X1D
Primitive: 16-Deep by 1-Wide Static Dual Port Synchronous RAM

RAM16X1D is a 16-word by 1-bit static dual port random access memory with
synchronous write capability. The device has two separate address ports: the read
WE RAM16X1D SPO address (DPRA3 – DPRA0) and the write address (A3 – A0). These two address ports
D are completely asynchronous. The read address controls the location of the data
WCLK DPO driven out of the output pin (DPO), and the write address controls the destination of a
A0 valid write transaction.
A1 When the write enable (WE) is Low, transitions on the write clock (WCLK) are
A2 ignored and data stored in the RAM is not affected. When WE is High, any positive
transition on WCLK loads the data on the data input (D) into the word selected by the
A3
4-bit write address. For predictable performance, write address and data inputs must
DPRA0 be stable before a Low-to-High WCLK transition. This RAM block assumes an active-
DPRA1 High WCLK. WCLK can be active-High or active-Low. Any inverter placed on the
DPRA2 WCLK input net is absorbed into the block.
DPRA3 Mode selection is shown in the following truth table.

Inputs Outputs
X4950
WE (mode) WCLK D SPO DPO
0 (read) X X data_a data_d
1 (read) 0 X data_a data_d
1 (read) 1 X data_a data_d
1 (write) ↑ D D data_d
1 (read) ↓ X data_a data_d
data_a = word addressed by bits A3-A0
data_d = word addressed by bits DPRA3-DPRA0

The SPO output reflects the data in the memory cell addressed by A3 – A0. The DPO
output reflects the data in the memory cell addressed by DPRA3 – DPRA0.
Note: The write process is not affected by the address on the read address port.

Specifying Initial Contents of a RAM

You can use the INIT attribute to specify an initial value directly on the symbol if the
RAM is 1 bit wide and 16, 32, 64, or 128 bits deep. The value must be a hexadecimal
number, for example, INIT=ABAC. If the INIT attribute is not specified, the RAM is
initialized with zero.
See the "INIT" section of the Constraints Guide for more information on the INIT
attribute.
For Spartan-3E wide RAMs (2, 4, and 8-bit wide single port synchronous RAMs with a
WCLK) can also be initialized. These RAMs, however, require INIT_xx attributes.

Usage
This design element can be inferred or instantiated. The instantiation code is shown
below. For information on how to infer RAM, see the XST User Guide.

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RAM16X1D

Available Attributes
Attribute Type Allowed Values Default Description
INIT 16-Bit 16-Bit Hexadecimal All zeros Initializes ROMs, RAMs,
Hexadeci registers, and look-up
mal tables.

VHDL Instantiation Template

-- RAM16X1D : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (RAM16X1D_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- RAM16X1D: 16 x 1 positive edge write, asynchronous read dual-port distributed RAM

-- All FPGAs
-- Xilinx HDL Libraries Guide version 8.1i

RAM16X1D_inst : RAM16X1D
generic map (
INIT => X"0000")
port map (
DPO => DPO, -- Port A 1-bit data output
SPO => SPO, -- Port B 1-bit data output
A0 => A0, -- Port A address[0] input bit
A1 => A1, -- Port A address[1] input bit
A2 => A2, -- Port A address[2] input bit
A3 => A3, -- Port A address[3] input bit
D => D, -- Port A 1-bit data input
DPRA0 => DPRA0, -- Port B address[0] input bit
DPRA1 => DPRA1, -- Port B address[1] input bit
DPRA2 => DPRA2, -- Port B address[2] input bit
DPRA3 => DPRA3, -- Port B address[3] input bit
WCLK => WCLK, -- Port A write clock input
WE => WE -- Port A write enable input
);

-- End of RAM16X1D_inst instantiation

Verilog Instantiation Template

// RAM16X1D : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (RAM16X1D_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// RAM16X1D: 16 x 1 positive edge write, asynchronous read dual-port distributed RAM

// All FPGAs
// Xilinx HDL Libraries Guide Version 8.1i

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RAM16X1D

RAM16X1D #(
.INIT(16'h0000) // Initial contents of RAM
) RAM16X1D_inst (
.DPO(DPO), // Port A 1-bit data output
.SPO(SPO), // Port B 1-bit data output
.A0(A0), // Port A address[0] input bit
.A1(A1), // Port A address[1] input bit
.A2(A2), // Port A address[2] input bit
.A3(A3), // Port A address[3] input bit
.D(D), // Port A 1-bit data input
.DPRA0(DPRA0), // Port B address[0] input bit
.DPRA1(DPRA1), // Port B address[1] input bit
.DPRA2(DPRA2), // Port B address[2] input bit
.DPRA3(DPRA3), // Port B address[3] input bit
.WCLK(WCLK), // Port A write clock input
.WE(WE) // Port A write enable input
);

// End of RAM16X1D_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

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RAM16X1D

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RAM16X1S

RAM16X1S
Primitive: 16-Deep by 1-Wide Static Synchronous RAM

RAM16X1S is a 16-word by 1-bit static random access memory with synchronous

write capability. When the write enable (WE) is set Low, transitions on the write clock
WE RAM16X1S O
(WCLK) are ignored and data stored in the RAM is not affected. When WE is set High,
D
any positive transition on WCLK loads the data on the data input (D) into the word
WCLK selected by the 4-bit address (A3 – A0). For predictable performance, address and data
A0 inputs must be stable before a Low-to-High WCLK transition. This RAM block
A1 assumes an active-High WCLK. However, WCLK can be active-High or active-Low.
A2 Any inverter placed on the WCLK input net is absorbed into the block.
A3
The signal output on the data output pin (O) is the data that is stored in the RAM at
the location defined by the values on the address pins.
X4942
You can initialize RAM16X1S during configuration using the INIT attribute. See
“Specifying Initial Contents of a RAM” in the RAM16X1D section.
Mode selection is shown in the following truth table.

Inputs Outputs

WE(mode) WCLK D O
0 (read) X X Data
1 (read) 0 X Data
1 (read) 1 X Data
1 (write) ↑ D D
1 (read) ↓ X Data
Data = word addressed by bits A3 – A0

Usage
This design element can be inferred or instantiated. The instantiation code is shown
below. For information on how to infer RAM, see the XST User Guide.

Available Attributes
Attribute Type Allowed Values Default Description
INIT Hexadeci Any 16-bit value. All zeros Specifies initial contents of
mal the RAM.

VHDL Instantiation Template

-- RAM16X1S : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (RAM16X1S_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx

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-- primitives : primitives and points to the models that are used

-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- RAM16X1S: 16 x 1 posedge write distributed => LUT RAM

-- All FPGA
-- Xilinx HDL Libraries Guide Version 8.1i

RAM16X1S_inst : RAM16X1S
generic map (
INIT => X"0000")
port map (
O => O, -- RAM output
A0 => A0, -- RAM address[0] input
A1 => A1, -- RAM address[1] input
A2 => A2, -- RAM address[2] input
A3 => A3, -- RAM address[3] input
D => D, -- RAM data input
WCLK => WCLK, -- Write clock input
WE => WE -- Write enable input
);

-- End of RAM16X1S_inst instantiation

Verilog Instantiation Template

// RAM16X1S : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (RAM16X1S_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connect.

// <-----Cut code below this line---->

// RAM16X1S: 16 x 1 posedge write distributed (LUT) RAM

// All FPGA
// Xilinx HDL Libraries Guide Version 8.1i

RAM16X1S #(
.INIT(16'h0000) // Initial contents of RAM
) RAM16X1S_inst (
.O(O), // RAM output
.A0(A0), // RAM address[0] input
.A1(A1), // RAM address[1] input
.A2(A2), // RAM address[2] input
.A3(A3), // RAM address[3] input
.D(D), // RAM data input
.WCLK(WCLK), // Write clock input
.WE(WE) // Write enable input
);

// End of RAM16X1S_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

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RAM32X1D

RAM32X1D
Primitive: 32-Deep by 1-Wide Static Dual Static Port Synchronous RAM

RAM32X1D is a 32-word by 1-bit static dual port random access memory with
WE RAM32x1D
D SPO
synchronous write capability. The device has two separate address ports: the read
WCLK address (DPRA4 – DPRA0) and the write address (A4 – A0). These two address ports
A0 DPO are completely asynchronous. The read address controls the location of the data
A1 driven out of the output pin (DPO), and the write address controls the destination of a
A2
valid write transaction.
A3
A4 When the write enable (WE) is Low, transitions on the write clock (WCLK) are
DPRA0
DPRA1
ignored and data stored in the RAM is not affected. When WE is High, any positive
DPRA2 transition on WCLK loads the data on the data input (D) into the word selected by the
DPRA3 5-bit write address. For predictable performance, write address and data inputs must
DPRA4 be stable before a Low-to-High WCLK transition. This RAM block assumes an active-
X9261
High WCLK. WCLK can be active-High or active-Low. Any inverter placed on the
WCLK input net is absorbed into the block.
You can initialize RAM32X1D during configuration using the INIT attribute. See
“Specifying Initial Contents of a RAM” in the RAM16X1D section.
Mode selection is shown in the following truth table.

Inputs Outputs

WE (mode) WCLK D SPO DPO

0 (read) X X data_a data_d
1 (read) 0 X data_a data_d
1 (read) 1 X data_a data_d
1 (write) ↑ D D data_d
1 (read) ↓ X data_a data_d
data_a = word addressed by bits A4-A0
data_d = word addressed by bits DPRA4-DPRA0

The SPO output reflects the data in the memory cell addressed by A4 – A0. The DPO
output reflects the data in the memory cell addressed by DPRA4 – DPRA0.
Note: The write process is not affected by the address on the read address port.

Usage
This design element can be inferred or instantiated. The instantiation code is shown
below. For information on how to infer RAM, see the XST User Guide.

Available Attributes
Allowed
Attribute Type Default Description
Values
INIT 32-Bit 32-Bit All zeros Initializes ROMs,
Hexadeci Hexadecimal RAMs, registers, and
mal look-up tables.

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VHDL Instantiation Template

-- RAM32X1D : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (RAM32X1D_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- RAM32X1D: 32 x 1 positive edge write, asynchronous read dual-port distributed RAM

-- Viretx-II/II-Pro
-- Xilinx HDL Libraries Guide version 8.1i

RAM32X1D_inst : RAM32X1D
generic map (
INIT => X"00000000")
port map (
DPO => DPO, -- Port A 1-bit data output
SPO => SPO, -- Port B 1-bit data output
A0 => A0, -- Port A address[0] input bit
A1 => A1, -- Port A address[1] input bit
A2 => A2, -- Port A address[2] input bit
A3 => A3, -- Port A address[3] input bit
A4 => A4, -- Port A address[4] input bit
D => D, -- Port A 1-bit data input
DPRA0 => DPRA0, -- Port B address[0] input bit
DPRA1 => DPRA1, -- Port B address[1] input bit
DPRA2 => DPRA2, -- Port B address[2] input bit
DPRA3 => DPRA3, -- Port B address[3] input bit
DPRA4 => DPRA4, -- Port B address[4] input bit
WCLK => WCLK, -- Port A write clock input
WE => WE -- Port A write enable input
);

End of RAM32X1D_inst instantiation

Verilog Instantiation Template

// RAM32X1D : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (RAM32X1D_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// RAM32X1D: 32 x 1 positive edge write, asynchronous read dual-port distributed RAM

// Viretx-II/II-Pro
// Xilinx HDL Libraries Guide Version 8.1i

RAM32X1D #(
.INIT(32'h00000000) // Initial contents of RAM
) RAM32X1D_inst (
.DPO(DPO), // Port A 1-bit data output
.SPO(SPO), // Port B 1-bit data output
.A0(A0), // Port A address[0] input bit
.A1(A1), // Port A address[1] input bit
.A2(A2), // Port A address[2] input bit
.A3(A3), // Port A address[3] input bit
.A4(A4), // Port A address[4] input bit

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.D(D), // Port A 1-bit data input

.DPRA0(DPRA0), // Port B address[0] input bit
.DPRA1(DPRA1), // Port B address[1] input bit
.DPRA2(DPRA2), // Port B address[2] input bit
.DPRA3(DPRA3), // Port B address[3] input bit
.DPRA4(DPRA4), // Port B address[4] input bit
.WCLK(WCLK), // Port A write clock input
.WE(WE) // Port A write enable input
);

// End of RAM32X1D_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

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RAM32X1D

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RAM32X1S

RAM32X1S
Primitive: 32-Deep by 1-Wide Static Synchronous RAM

RAM32X1S is a 32-word by 1-bit static random access memory with synchronous

WE RAM32X1S O
write capability. When the write enable is set Low, transitions on the write clock
D (WCLK) are ignored and data stored in the RAM is not affected. When WE is set High,
WCLK any positive transition on WCLK loads the data on the data input (D) into the word
A0 selected by the 5-bit address (A4 – A0). For predictable performance, address and data
A1 inputs must be stable before a Low-to-High WCLK transition. This RAM block
A2 assumes an active-High WCLK. However, WCLK can be active-High or active-Low.
A3
Any inverter placed on the WCLK input net is absorbed into the block.
A4
The signal output on the data output pin (O) is the data that is stored in the RAM at
X4943 the location defined by the values on the address pins.
You can initialize RAM32X1S during configuration using the INIT attribute. See
“Specifying Initial Contents of a RAM” in the RAM16X1D section.
Mode selection is shown in the following truth table.

Inputs Outputs

WE (mode) WCLK D O
0 (read) X X Data
1 (read) 0 X Data
1 (read) 1 X Data
1 (write) ↑ D D
1 (read) ↓ X Data
Data = word addressed by bits A4 – A0

Usage
This design element can be inferred or instantiated. The instantiation code is shown
below. For information on how to infer RAM, see the XST User Guide.

Available Attributes
Attribute Type Allowed Values Default Description
INIT Hexa- Any 32-bit value. All zeros Specifies initial contents of
decimal the RAM.

VHDL Instantiation Template

-- RAM32X1S : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (RAM32X1S_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx

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RAM32X1S

-- primitives : primitives and points to the models that are used

-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- RAM32X1S: 32 x 1 posedge write distributed => LUT RAM

-- All FPGA
-- Xilinx HDL Libraries Guide Version 8.1i

RAM32X1S_inst : RAM32X1S
generic map (
INIT => X"00000000")
port map (
O => O, -- RAM output
A0 => A0, -- RAM address[0] input
A1 => A1, -- RAM address[1] input
A2 => A2, -- RAM address[2] input
A3 => A3, -- RAM address[3] input
A4 => A4, -- RAM address[4] input
D => D, -- RAM data input
WCLK => WCLK, -- Write clock input
WE => WE -- Write enable input
);

-- End of RAM32X1S_inst instantiation

Verilog Instantiation Template

// RAM32X1S : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (RAM32X1S_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connect.

// <-----Cut code below this line---->

// RAM32X1S: 32 x 1 posedge write distributed (LUT) RAM

// All FPGA
// Xilinx HDL Libraries Guide Version 8.1i

RAM32X1S #(
.INIT(32'h00000000) // Initial contents of RAM
) RAM32X1S_inst (
.O(O), // RAM output
.A0(A0), // RAM address[0] input
.A1(A1), // RAM address[1] input
.A2(A2), // RAM address[2] input
.A3(A3), // RAM address[3] input
.A4(A4), // RAM address[4] input
.D(D), // RAM data input
.WCLK(WCLK), // Write clock input
.WE(WE) // Write enable input
);

// End of RAM32X1S_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

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RAM64X1S

RAM64X1S
Primitive: 64-Deep by 1-Wide Static Synchronous RAM

RAM64X1S is a 64-word by 1-bit static random access memory (RAM) with

WE RAM64x1S synchronous write capability. When the write enable is set Low, transitions on the
D O
WCLK
write clock (WCLK) are ignored and data stored in the RAM is not affected. When WE
A0 is set High, any positive transition on WCLK loads the data on the data input (D) into
A1 the word selected by the 6-bit address (A5 – A0). For predictable performance,
A2 address and data inputs must be stable before a Low-to-High WCLK transition. This
A3
RAM block assumes an active-High WCLK. However, WCLK can be active-High or
A4
A5 active-Low. Any inverter placed on the WCLK input net is absorbed into the block.

X9265
The signal output on the data output pin (O) is the data that is stored in the RAM at
the location defined by the values on the address pins.
You can initialize RAM64X1S during configuration using the INIT attribute. See
“Specifying Initial Contents of a RAM” in the RAM16X1D section.
Mode selection is shown in the following truth table.

Inputs Outputs

WE (mode) WCLK D O
0 (read) X X Data
1 (read) 0 X Data
1 (read) 1 X Data
1 (write) ↑ D D
1 (read) ↓ X Data
Data = word addressed by bits A5 – A0

Usage
This design element can be inferred or instantiated. The instantiation code is shown
below. For information on how to infer RAM, see the XST User Guide.

Available Attributes
Attribute Type Allowed Values Default Description
INIT 64-Bit 64-Bit Hexadecimal All zeros Initializes ROMs, RAMs,
Hexa- registers, and look-up
decimal tables.

VHDL Instantiation Template

-- RAM64X1S : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (RAM64X1S_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library

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RAM64X1S

-- Xilinx : contains the component declarations for all Xilinx

-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- RAM64X1S: 64 x 1 positive edge write, asynchronous read single-port distributed RAM

-- FPGAs
-- Xilinx HDL Libraries Guide version 8.1i

RAM64X1S_inst : RAM64X1S
generic map (
INIT => X"0000000000000000")
port map (
O => O, -- 1-bit data output
A0 => A0, -- Address[0] input bit
A1 => A1, -- Address[1] input bit
A2 => A2, -- Address[2] input bit
A3 => A3, -- Address[3] input bit
A4 => A4, -- Address[4] input bit
A5 => A5, -- Address[5] input bit
D => D, -- 1-bit data input
WCLK => WCLK, -- Write clock input
WE => WE -- Write enable input
);

-- End of RAM64X1S_inst instantiation

Verilog Instantiation Template

// RAM64X1S : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (RAM64X1S_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connect.

// <-----Cut code below this line---->

// RAM64X1S: 64 x 1 positive edge write, asynchronous read single-port distributed RAM

// FPGAs.
// Xilinx HDL Libraries Guide Version 8.1i

RAM64X1S #(
.INIT(64'h0000000000000000) // Initial contents of RAM
) RAM64X1S_inst (
.O(O), // 1-bit data output
.A0(A0), // Address[0] input bit
.A1(A1), // Address[1] input bit
.A2(A2), // Address[2] input bit
.A3(A3), // Address[3] input bit
.A4(A4), // Address[4] input bit
.A5(A5), // Address[5] input bit
.D(D), // 1-bit data input
.WCLK(WCLK), // Write clock input
.WE(WE) // Write enable input
);

// End of RAM64X1S_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

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RAM128X1S

RAM128X1S
Primitive: 128-Deep by 1-Wide Static Synchronous RAM

RAM128X1S is a 128-word by 1-bit static random access memory with synchronous

WE RAM128x1S write capability. When the write enable is Low, transitions on the write clock (WCLK)
D O
WCLK
are ignored and data stored in the RAM is not affected. When WE is High, any
A0 positive transition on WCLK loads the data on the data input (D) into the word
A1 selected by the 7-bit address (A6 – A0). For predictable performance, address and data
A2
inputs must be stable before a Low-to-High WCLK transition. This RAM block
A3
A4
assumes an active-High WCLK. However, WCLK can be active-High or active-Low.
A5 Any inverter placed on the WCLK input net is absorbed into the block.
A6
The signal output on the data output pin (O) is the data that is stored in the RAM at
X9267
the location defined by the values on the address pins.
You can initialize RAM128X1S during configuration using the INIT attribute. See
“Specifying Initial Contents of a RAM” in the RAM16X1D section.
Mode selection is shown in the following truth table.

Inputs Outputs

WE (mode) WCLK D O
0 (read) X X Data
1 (read) 0 X Data
1 (read) 1 X Data
1 (write) ↑ D D
1 (read) ↓ X Data
Data = word addressed by bits A6 – A0

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the user’s source code.

Available Attributes
Attribute Type Allowed Values Default Description
INIT 128-Bit 128-Bit Hexadecimal All zeros Initializes ROMs, RAMs,
Hexadeci registers, and look-up
mal tables.

VHDL Instantiation Template

-- RAM128X1S : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (RAM128X1S_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library

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RAM128X1S

-- Xilinx : contains the component declarations for all Xilinx

-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- RAM128X1S: 128 x 1 positive edge write, asynchronous read single-port distributed RAM
-- FPGAs.
-- Xilinx HDL Libraries Guide version 8.1i

RAM128X1S_inst : RAM128X1S
generic map (
INIT => X"00000000000000000000000000000000")
port map (
O => O, -- 1-bit data output
A0 => A0, -- Address[0] input bit
A1 => A1, -- Address[1] input bit
A2 => A2, -- Address[2] input bit
A3 => A3, -- Address[3] input bit
A4 => A4, -- Address[4] input bit
A5 => A5, -- Address[5] input bit
A6 => A6, -- Address[6] input bit
D => D, -- 1-bit data input
WCLK => WCLK, -- Write clock input
WE => WE -- Write enable input
);

-- End of RAM128X1S_inst instantiation

Verilog Instantiation Template

// RAM128X1S : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (RAM128X1S_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connect.

// <-----Cut code below this line---->

// RAM128X1S: 128 x 1 positive edge write, asynchronous read single-port distributed RAM
// FPGAs.
// Xilinx HDL Libraries Guide Version 8.1i

RAM128X1S #(
.INIT(128'h00000000000000000000000000000000) // Initial contents of RAM
) RAM128X1S_inst (
.O(O), // 1-bit data output
.A0(A0), // Address[0] input bit
.A1(A1), // Address[1] input bit
.A2(A2), // Address[2] input bit
.A3(A3), // Address[3] input bit
.A4(A4), // Address[4] input bit
.A5(A5), // Address[5] input bit
.A6(A6), // Address[6] input bit
.D(D), // 1-bit data input
.WCLK(WCLK), // Write clock input
.WE(WE) // Write enable input
);

// End of RAM128X1S_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

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RAMB16_Sm_Sn

RAMB16_Sm_Sn
Primitive: 16384-Bit Data Memory and 2048-Bit Parity Memory, Dual-
Port Synchronous Block RAM with Port Width (m or n) Configured to 1,
2, 4, 9, 18, or 36 Bits

WEA RAMB16_S1_S1 WEA RAMB16_S1_S2 WEA RAMB16_S1_S4

ENA ENA ENA
SSRA DOA [0:0] SSRA DOA [0:0] SSRA DOA [0:0]
CLKA CLKA CLKA
ADDRA [13:0] ADDRA [13:0] ADDRA [13:0]

DIA [0:0] DIA [0:0] DIA [0:0]

WEB WEB WEB

ENB ENB ENB
SSRB DOB [0:0] SSRB DOB [1:0] SSRB DOB [3:0]
CLKB CLKB CLKB
ADDRB [13:0] ADDRB [12:0] ADDRB [11:0]

DIB [0:0] DIB [1:0] DIB [3:0]

WEA RAMB16_S1_S9 WEA RAMB16_S1_S18 WEA RAMB16_S1_S36

ENA ENA ENA
SSRA DOA [0:0] SSRA DOA [0:0] SSRA DOA [0:0]
CLKA CLKA CLKA
ADDRA [13:0] ADDRA [13:0] ADDRA [13:0]

DIA [0:0] DIA [0:0] DIA [0:0]

WEB WEB WEB

ENB ENB ENB
SSRB DOPB [0:0] SSRB DOPB [1:0] SSRB DOPB [3:0]
CLKB CLKB CLKB
DOB [7:0] DOB [15:0] DOB [31:0]
ADDRB [10:0] ADDRB [9:0] ADDRB [8:0]

DIB [7:0] DIB [15:0] DIB [31:0]

DIPB [0:0] DIPB [1:0] DIPB [3:0]

X9466

RAMB16_S1_S1 through RAMB16_S1_S36 Representations

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WEA RAMB16_S2_S9

RAMB16_S2_S2 RAMB16_S2_S4 ENA

WEA WEA
SSRA DOA [1:0]
ENA ENA
CLKA
SSRA DOA [1:0] SSRA DOA [1:0]
ADDRA [12:0]
CLKA CLKA
ADDRA [12:0] ADDRA [12:0] DIA [1:0]

DIA [1:0] DIA [1:0]

WEB
ENB
WEB WEB
ENB ENB SSRB DOPB [0:0]
CLKB
SSRB DOB [1:0] SSRB DOB [3:0] DOB [7:0]
ADDRB [10:0]
CLKB CLKB
ADDRB [12:0] ADDRB [11:0] DIB [7:0]

DIB [1:0] DIB [3:0] DIPB [0:0]

WEA RAMB16_S2_S18 WEA RAMB16_S2_S36

ENA ENA RAMB16_S4_S4
WEA
SSRA DOA [1:0] SSRA DOA [1:0] ENA
CLKA CLKA
SSRA DOA [3:0]
ADDRA [12:0] ADDRA [12:0]
CLKA
DIA [1:0] DIA [1:0] ADDRA [11:0]

DIA [3:0]

WEB WEB
ENB ENB
WEB
SSRB DOPB [1:0] SSRB DOPB [3:0] ENB
CLKB CLKB
DOB [15:0] DOB [31:0] SSRB DOB [3:0]
ADDRB [9:0] ADDRB [8:0]
CLKB
DIB [15:0] DIB [31:0] ADDRB [11:0]

DIPB [1:0] DIPB [3:0] DIB [3:0]

WEA RAMB16_S4_S9 WEA RAMB16_S4_S18 WEA RAMB16_S4_S36

ENA ENA ENA
SSRA DOA [3:0] SSRA DOA [3:0] SSRA DOA [3:0]
CLKA CLKA CLKA
ADDRA [11:0] ADDRA [11:0] ADDRA [11:0]

DIA [3:0] DIA [3:0] DIA [3:0]

WEB WEB WEB

ENB ENB ENB
SSRB DOPB [0:0] SSRB DOPB [1:0] SSRB DOPB [3:0]
CLKB CLKB CLKB
DOB [7:0] DOB [15:0] DOB [31:0]
ADDRB [10:0] ADDRB [9:0] ADDRB [8:0]

DIB [7:0] DIB [15:0] DIB [31:0]

DIPB [0:0] DIPB [1:0] DIPB [3:0]

X9467

RAMB16_S2_S2 through RAMB16_S4_S36 Representations

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RAMB16_Sm_Sn

WEA RAMB16_S9_S9 WEA RAMB16_S9_S18 WEA RAMB16_S9_S36

ENA ENA ENA

SSRA SSRA DOPA [0:0] SSRA DOPA [0:0]

DOPA [0:0]
CLKA CLKA CLKA
DOA [7:0] DOA [7:0]
DOA [7:0] ADDRA [10:0] ADDRA [10:0]
ADDRA [10:0]

DIA [7:0] DIA [7:0] DIA [7:0]

DIPA [0:0] DIPA [0:0] DIPA [0:0]

WEB WEB WEB

ENB ENB ENB
SSRB DOPB [0:0] SSRB DOPB [1:0] SSRB DOPB [3:0]
CLKB CLKB CLKB
DOB [7:0] DOB [15:0] DOB [31:0]
ADDRB [10:0] ADDRB [9:0] ADDRB [8:0]

DIB [7:0] DIB [15:0] DIB [31:0]

DIPB [0:0] DIPB [1:0] DIPB [3:0]

WEA RAMB16_S18_S18 WEA RAMB16_S18_S36 WEA RAMB16_S36_S36

ENA ENA ENA
SSRA DOPA [1:0] SSRA DOPA [1:0] SSRA DOPA [3:0]
CLKA CLKA CLKA
DOA [15:0] DOA [15:0] DOA [31:0]
ADDRA [9:0] ADDRA [9:0] ADDRA [8:0]

DIA [15:0] DIA [15:0] DIA [31:0]

DIPA [1:0] DIPA [1:0] DIPA [3:0]

WEB WEB WEB

ENB ENB ENB
SSRB DOPB [1:0] SSRB DOPB [3:0] SSRB DOPB [3:0]
CLKB CLKB CLKB
DOB [15:0] DOB [31:0] DOB [31:0]
ADDRB [9:0] ADDRB [8:0] ADDRB [8:0]

DIB [15:0] DIB [31:0] DIB [31:0]

DIPB [1:0] DIPB [3:0] DIPB [3:0]

X9468

RAMB16_S9_S9 through RAMB16_S36_S36 Representations

The RAMB16_Sm_Sn components listed in the following table are dual-ported
dedicated random access memory blocks with synchronous write capability. Each
block RAM port has 16384 bits of data memory. Ports configured as 9, 18, or 36-bits
wide have an additional 2048 bits of parity memory. Each port is independent of the
other while accessing the same set of 16384 data memory cells. Each port is

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independently configured to a specific data width. The possible port and cell
configurations are listed in the following table.

Port A Port B
Data Cellsa Parity Address Data Bus Parity Data Cellsa Parity Address Data Bus Parity
Component
Cellsa Bus Bus Cellsa Bus Bus
RAMB16_S1_ 16384 x 1 - (13:0) (0:0) - 16384 x 1 - (13:0) (0:0) -
S1
RAMB16_S1_ 16384 x 1 - (13:0) (0:0) - 8192 x 2 - (12:0) (1:0) -
S2
RAMB16_S1_ 16384 x 1 - (13:0) (0:0) - 4096 x 4 - (11:0) (3:0) -
S4
RAMB16_S1_ 16384 x 1 - (13:0) (0:0) - 2048 x 8 2048 x 1 (10:0) (7:0) (0:0)
S9
RAMB16_S1_ 16384 x 1 - (13:0) (0:0) - 1024 x 16 1024 x 2 (9:0) (15:0) (1:0)
S18
RAMB16_S1_ 16384 x 1 - (13:0) (0:0) - 512 x 32 512 x 4 (8:0) (31:0) (3:0)
S36
RAMB16_S2_ 8192 x 2 - (12:0) (1:0) - 8192 x 2 - (12:0) (1:0) -
S2
RAMB16_S2_ 8192 x 2 - (12:0) (1:0) - 4096 x 4 - (11:0) (3:0) -
S4
RAMB16_S2_ 8192 x 2 - (12:0) (1:0) - 2048 x 8 2048 x 1 (10:0) (7:0) (0:0)
S9
RAMB16_S2_ 8192 x 2 - (12:0) (1:0) - 1024 x 16 1024 x 2 (9:0) (15:0) (1:0)
S18
RAMB16_S2_ 8192 x 2 - (12:0) (1:0) - 512 x 32 512 x 4 (8:0) (31:0) (3:0)
S36
RAMB16_S4_ 4096 x 4 - (11:0) (3:0) - 4096 x 4 - (11:0) (3:0) -
S4
RAMB16_S4_ 4096 x 4 - (11:0) (3:0) - 2048 x 8 2048 x 1 (10:0) (7:0) (0:0)
S9
RAMB16_S4_ 4096 x 4 - (11:0) (3:0) - 1024 x 16 1024 x 2 (9:0) (15:0) (1:0)
S18
RAMB16_S4_ 4096 x 4 - (11:0) (3:0) - 512 x 32 512 x 4 (8:0) (31:0) (3:0)
S36
RAMB16_S9_ 2048 x 8 2048 x 1 (10:0) (7:0) (0:0) 2048 x 8 2048 x 1 (10:0) (7:0) (0:0)
S9
RAMB16_S9_ 2048 x 8 2048 x 1 (10:0) (7:0) (0:0) 1024 x 16 1024 x 2 (9:0) (15:0) (1:0)
S18
RAMB16_S9_ 2048 x 8 2048 x 1 (10:0) (7:0) (0:0) 512 x 32 512 x 4 (8:0) (31:0) (3:0)
S36
RAMB16_S18 1024 x 16 1024 x 2 (9:0) (15:0) (1:0) 1024 x 16 1024 x 2 (9:0) (15:0) (1:0)
_S18
RAMB16_S18 1024 x 16 1024 x 2 (9:0) (15:0) (1:0) 512 x 32 512 x 4 (8:0) (31:0) (3:0)
_S36

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Port A Port B
RAMB16_S36 512 x 32 512 x 4 (8:0) (31:0) (3:0) 512 x 32 512 x 4 (8:0) (31:0) (3:0)
_S36
aDepth x Width

Each port is fully synchronous with independent clock pins. All port A input pins
have setup time referenced to the CLKA pin and its data output bus DOA has a clock-
to-out time referenced to the CLKA. All port B input pins have setup time referenced
to the CLKB pin and its data output bus DOB has a clock-to-out time referenced to the
CLKB.
The enable ENA pin controls read, write, and reset for port A. When ENA is Low, no
data is written and the outputs (DOA and DOPA) retain the last state. When ENA is
High and reset (SSRA) is High, DOA and DOPA are set to SRVAL_A during the Low-
to-High clock (CLKA) transition; if write enable (WEA) is High, the memory contents
reflect the data at DIA and DIPA. When ENA is High and WEA is Low, the data stored
in the RAM address (ADDRA) is read during the Low-to-High clock transition. By
default, WRITE_MODE_A=WRITE_FIRST, when ENA and WEA are High, the data
on the data inputs (DIA and DIPA) is loaded into the word selected by the write
address (ADDRA) during the Low-to-High clock transition and the data outputs
(DOA and DOPA) reflect the selected (addressed) word.
The enable ENB pin controls read, write, and reset for port B. When ENB is Low, no
data is written and the outputs (DOB and DOPB) retain the last state. When ENB is
High and reset (SSRB) is High, DOB and DOPB are set to SRVAL_B during the Low-
to-High clock (CLKB) transition; if write enable (WEB) is High, the memory contents
reflect the data at DIB and DIPB. When ENB is High and WEB is Low, the data stored
in the RAM address (ADDRB) is read during the Low-to-High clock transition. By
default, WRITE_MODE_B=WRITE_FIRST, when ENB and WEB are High, the data on
the data inputs (DIB and PB) are loaded into the word selected by the write address
(ADDRB) during the Low-to-High clock transition and the data outputs (DOB and
DOPB) reflect the selected (addressed) word.
The above descriptions assume active High control pins (ENA, WEA, SSRA, CLKA,
ENB, WEB, SSRB, and CLKB). However, the active level can be changed by placing an
inverter on the port. Any inverter placed on a RAMB16 port is absorbed into the block
and does not use a CLB resource.
Port A Truth Table

Inputs Outputs

ADD
GSR ENA SSRA WEA CLKA DIA DIPA DOA DOPA RAM Contents
RA
Data RAM Parity RAM
1 X X X X X X X INIT_A INIT_A No Chg No Chg
0 0 X X X X X X No Chg No Chg No Chg No Chg
0 1 1 0 ↑ X X X SRVAL_A SRVAL_A No Chg No Chg
0 1 1 1 ↑ addr data pdata SRVAL_A SRVAL_A RAM(addr) RAM(addr)
=>data =>pdata
0 1 0 0 ↑ addr X X RAM(addr) RAM(addr) No Chg No Chg

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Port A Truth Table

Inputs Outputs

ADD
GSR ENA SSRA WEA CLKA DIA DIPA DOA DOPA RAM Contents
RA
0 1 0 1 ↑ addr data pdata No Chg1 No Chg1 RAM(addr) RAM(addr)
RAM RAM(addr) =>data =>pdata
(addr)2 2
data3 pdata3
GSR=Global Set Reset

INIT_A=Value specified by the INIT_A attribute for output register. Default is all zeros.
SRVAL_A=register value

addr=RAM address
RAM(addr)=RAM contents at address ADDR
data=RAM input data
pdata=RAM parity data

1WRITE_MODE_A=NO_CHANGE
2WRITE_MODE_A=READ_FIRST
3WRITE_MODE_A=WRITE_FIRST

Port B Truth Table

Inputs Outputs

GSR ENB SSRB WEB CLKB ADDRB DIB DIPB DOB DOPB RAM Contents
Data RAM Parity RAM
1 X X X X X X X INIT_B INIT_B No Chg No Chg
0 0 X X X X X X No Chg No Chg No Chg No Chg
0 1 1 0 ↑ X X X SRVAL_B SRVAL_B No Chg No Chg
0 1 1 1 ↑ addr data pdata SRVAL_B SRVAL_B RAM(addr) RAM(addr)
=>data =>pdata
0 1 0 0 ↑ addr X X RAM(add RAM(add No Chg No Chg
r) r)

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Port B Truth Table

Inputs Outputs

GSR ENB SSRB WEB CLKB ADDRB DIB DIPB DOB DOPB RAM Contents
0 1 0 1 ↑ addr data pdata No Chg1 No Chg1 RAM(addr) RAM(addr)
RAM RAM(add =>data =>pdata
(addr)2 r)2
data3 pdata3
GSR=Global Set Reset

INIT_B=Value specified by the INIT_B attribute for output registers. Default is all zeros.
SRVAL_B=register value

addr=RAM address
RAM(addr)=RAM contents at address ADDR
data=RAM input data
pdata=RAM parity data

1WRITE_MODE_B=NO_CHANGE
2WRITE_MODE_B=READ_FIRST
3WRITE_MODE_B=WRITE_FIRST

Address Mapping
Each port accesses the same set of 18432 memory cells using an addressing scheme
that is dependent on the width of the port. For all port widths, 16384 memory cells are
available for data as shown in the “Port Address Mapping for Data” table below. For
9-, 18-, and 36-bit wide ports, 2408 parity memory cells are also available as shown in
“Port Address Mapping for Parity” table below. The physical RAM location that is
addressed for a particular width is determined from the following formula.
Start=((ADDR port+1)*(Widthport)) -1
End=(ADDRport)*(Widthport)
The following tables shows address mapping for each port width.

Port Address Mapping for Data

Data
Port Data Addresses
Width
1 16384 <-- 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
2 8192 <-- 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
4 4096 <-- 07 06 05 04 03 02 01 00
8 2048 <-- 03 02 01 00
16 1024 <-- 01 00
32 512 <-- 00

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Port Address Mapping for Parity

Parity Width Port Parity Addresses

1 2048 <----- 03 02 01 00
2 1024 <----- 01 00
4 512 <----- 00

Initializing Memory Contents of a Dual-Port RAMB16

You can use the INIT_xx attributes to specify an initialization value for the memory
contents of a RAMB16 during device configuration. The initialization of each
RAMB16_Sm_Sn is set by 64 initialization attributes (INIT_00 through INIT_3F) of 64
hex values for a total of 16384 bits.
You can use the INITP_xx attributes to specify an initial value for the parity memory
during device configuration or assertion. The initialization of the parity memory for
ports configured for 9, 18, or 36 bits is set by 8 initialization attributes (INITP_00
through INITP_07) of 64 hex values for a total of 2048 bits.
If any INIT_xx or INITP_xx attribute is not specified, it is configured as zeros. Partial
strings are padded with zeros to the left.
See the Constraints Guide for more information on these attributes.

Initializing the Output Register of a Dual-Port RAMB16

In Spartan-3E, each bit in an output register can be initialized at power on (when GSR
is high) to either a 0 or 1. In addition, the initial state specified for power on can be
different than the state that results from assertion of a set/reset. Four properties
control initialization of the output register for a dual-port RAMB16: INIT_A, INIT_B,
SRVAL_A, and SRVAL_B. The INIT_A attribute specifies the output register value at
power on for port A and the INIT_B attribute specifies the value for port B. You can
use the SRVAL_A attribute to define the state resulting from assertion of the SSR
(set/reset) input on port A. You can use the SRVAL_B attribute to define the state
resulting from assertion of the SSR input on port B.
The INIT_A, INIT_B, SRVAL_A, and SRVAL_B attributes specify the initialization
value as a hexadecimal String. The value is dependent upon the port width. For
example, for a RAMB16_S1_S4 with port A width equal to 1 and port B width equal to
4, the port A output register contains 1 bit and the port B output register contains 4
bits. Therefore, the INIT_A or SRVAL_A value can only be specified as a 1 or 0. For
port B, the output register contains 4 bits. In this case, you can use INIT_B or
SRVAL_B to specify a hexadecimal value from 0 through F to initialize the 4 bits of the
output register.
For those ports that include parity bits, the parity portion of the output register is
specified in the high order bit position of the INIT_A, INIT_B, SRVAL_A, or SRVAL_B
value.
The INIT and SRVAL attributes default to zero if they are not set by the user.
See the Constraints Guide for more information on these attributes.

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Write Mode Selection

The WRITE_MODE_A attribute controls the memory and output contents of port A
for a dual-port RAMB16. The WRITE_MODE_B attribute does the same for port B. By
default, both WRITE_MODE_A and WRITE_MODE_B are set to WRITE_FIRST. This
means that input is read, written to memory, and then passed to output. You can set
the write mode for port A and/or port B to READ_FIRST to read the memory
contents, pass the memory contents to the outputs, and then write the input to
memory. Or, you can set the write mode to NO_CHANGE to have the input written to
memory without changing the output. The “Port A and Port B Conflict Resolution”
section describes how read/write conflicts are resolved when both port A and port B
are attempting to read/write to the same memory cells.

Port A and Port B Conflict Resolution

Spartan-3E block SelectRAM is True Dual-Port RAM that allows both ports to
simultaneously access the same memory cell. When one port writes to a given
memory cell, the other port must not address that memory cell (for a write or a read)
within the clock-to-clock setup window.
The following tables summarize the collision detection behavior of the dual-port
RAMB16 based on the WRITE_MODE_A and WRITE_MODE_B settings.

WRITE_MODE_A=NO_CHANGE and WRITE_MODE_B=NO_CHANGE

Data Parity
WEA WEB CLKA CLKB DIA DIB DIPA DIPB DOA DOB DOPA DOPB
RAM Ram
0 0 ↑ ↑ DIA DIB DIPA DIPB RAM RAM RAM RAM No Chg No Chg
1 0 ↑ ↑ DIA DIB DIPA DIPB No Chg X No Chg X DIA DIPA
0 1 ↑ ↑ DIA DIB DIPA DIPB X No Chg X No Chg DIB DIPB
1 1 ↑ ↑ DIA DIB DIPA DIPB No Chg No Chg No Chg No Chg X X

WRITE_MODE_A=READ_FIRST and WRITE_MODE_B=READ_FIRST

Data Parity
WEA WEB CLKA CLKB DIA DIB DIPA DIPB DOA DOB DOPA DOPB
RAM Ram
0 0 ↑ ↑ DIA DIB DIPA DIPB RAM RAM RAM RAM No Chg No Chg
1 0 ↑ ↑ DIA DIB DIPA DIPB RAM RAM RAM RAM DIA DIPA
0 1 ↑ ↑ DIA DIB DIPA DIPB RAM RAM RAM RAM DIB DIPB
1 1 ↑ ↑ DIA DIB DIPA DIPB RAM RAM RAM RAM X X

WRITE_MODE_A= WRITE_FIRST and WRITE_MODE_B=WRITE_FIRST

Data Parity
WEA WEB CLKA CLKB DIA DIB DIPA DIPB DOA DOB DOPA DOPB
RAM Ram
0 0 ↑ ↑ DIA DIB DIPA DIPB RAM RAM RAM RAM No Chg No Chg
1 0 ↑ ↑ DIA DIB DIPA DIPB DIA X DIPA X DIA DIPA

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WRITE_MODE_A= WRITE_FIRST and WRITE_MODE_B=WRITE_FIRST

Data Parity
WEA WEB CLKA CLKB DIA DIB DIPA DIPB DOA DOB DOPA DOPB
RAM Ram
0 1 ↑ ↑ DIA DIB DIPA DIPB X DIB X DIPB DIB DIPB
1 1 ↑ ↑ DIA DIB DIPA DIPB X X X X X X

WRITE_MODE_A=NO_CHANGE and WRITE_MODE_B=READ_FIRST

Data Parity
WEA WEB CLKA CLKB DIA DIB DIPA DIPB DOA DOB DOPA DOPB
RAM Ram
0 0 ↑ ↑ DIA DIB DIPA DIPB RAM RAM RAM RAM No Chg No Chg
1 0 ↑ ↑ DIA DIB DIPA DIPB No Chg X No Chg X DIA DIPA
0 1 ↑ ↑ DIA DIB DIPA DIPB RAM RAM RAM RAM DIB DIPB
1 1 ↑ ↑ DIA DIB DIPA DIPB No Chg X No Chg X DIB DIPB

WRITE_MODE_A=NO_CHANGE and WRITE_MODE_B=WRITE_FIRST

Data Parity
WEA WEB CLKA CLKB DIA DIB DIPA DIPB DOA DOB DOPA DOPB
RAM Ram
0 0 ↑ ↑ DIA DIB DIPA DIPB RAM RAM RAM RAM No Chg No Chg
1 0 ↑ ↑ DIA DIB DIPA DIPB No Chg X No Chg X DIA DIPA
0 1 ↑ ↑ DIA DIB DIPA DIPB X DIB X DIPB DIB DIPB
1 1 ↑ ↑ DIA DIB DIPA DIPB No Chg X No Chg X X X

WRITE_MODE_A=READ_FIRST and WRITE_MODE_B=WRITE_FIRST

Data Parity
WEA WEB CLKA CLKB DIA DIB DIPA DIPB DOA DOB DOPA DOPB
RAM Ram
0 0 ↑ ↑ DIA DIB DIPA DIPB RAM RAM RAM RAM No Chg No Chg
1 0 ↑ ↑ DIA DIB DIPA DIPB RAM RAM RAM RAM DIA DIPA
0 1 ↑ ↑ DIA DIB DIPA DIPB X DIB X DIPB DIB DIPB
1 1 ↑ ↑ DIA DIB DIPA DIPB X DIB X DIPB DIA DIPA

Usage
These design elements can be inferred or instantiated. The instantiation code is shown
below. For information on how to infer RAM, see the XST User Guide.

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Available Attributes
Allowed
Attribute Type Default Description
Values
INIT_00 To Binary/Hex- Any All zeros Specifies the initial contents of
INIT_3F adecimal the data portion of the RAM
array.
INIT_A Binary/Hex- Any All zeros Identifies the initial value of the
adecimal DOA/DOB output port after
completing configuration. For
Type, the bit width is dependent
on the width of the A or B port
of the RAM.
INIT_B Binary/Hex- Any All zeros Identifies the initial value of the
adecimal DOA/DOB output port after
completing configuration. For
Type, the bit width is dependent
on the width of the A or B port
of the RAM.
INITP_00 To Binary/Hex- Any All zeros Specifies the initial contents of
INITP_07 adecimal the parity portion of the RAM
array.
SIM_ String ¨ALL”, ¨ALL” Specifies the behavior during
COLLISION_ ¨NONE”, simulation in the event of a data
CHECK ¨WARNING” collision (data being read or
, or written to the same address from
¨GENERATE both ports of the Ram
_X_ONLY” simultaneously. "ALL" issues a
warning to simulator console
and generate an X or all
unknown data due to the
collision. This is the
recommended setting.
"WARNING" generates a
warning only and
"GENERATE_X_ONLY"
generates an X for unknown
data but won’t output the
occurrence to the simulation
console. "NONE" completely
ignores the error. It is suggested
to only change this attribute if
you can ensure the data
generated during a collision is
discarded.
SRVAL_A Binary/Hex- Any All zeros Allows the individual selection
adecimal of whether the DOA/DOB
output port sets (go to a one) or
reset (go to a zero) upon the
assertion of the SSRA/SSRB pin.
For Type, the bit width is
dependent on the width of the A
or B port of the RAM.

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Allowed
Attribute Type Default Description
Values
SRVAL_B Binary/Hex- Any All zeros Allows the individual selection
adecimal of whether the DOA/DOB
output port sets (go to a one) or
reset (go to a zero) upon the
assertion of the SSRA/SSRB pin.
For Type, the bit width is
dependent on the width of the A
or B port of the RAM.
WRITE_MODE String "WRITE_FIR "WRITE_ Specifies the behavior of the
_A ST", "READ_ FIRST” DOA/DOB port upon a write
FIRST" or command to the respected port.
"NO_ If set to "WRITE_FIRST", the
CHANGE” same port that is written to
displays the contents of the
written data to the outputs upon
completion of the operation.
"READ_FIRST" displays the
prior contents of the RAM to the
output port prior to writing the
new data. "NO_CHANGE"
keeps the previous value on the
output port and won’t update
the output port upon a write
command. This is the suggested
mode if not using the read data
from a particular port of the
RAM.
WRITE_MODE String "WRITE_ "WRITE_ Specifies the behavior of the
_B FIRST", FIRST” DOA/DOB port upon a write
"READ_ command to the respected port.
FIRST" or If set to "WRITE_FIRST", the
"NO_ same port that is written to
CHANGE” displays the contents of the
written data to the outputs upon
completion of the operation.
"READ_FIRST" displays the
prior contents of the RAM to the
output port prior to writing the
new data. "NO_CHANGE"
keeps the previous value on the
output port and won’t update
the output port upon a write
command. This is the suggested
mode if not using the read data
from a particular port of the
RAM.

VHDL and Verilog Instantiation

For VHDL and Verilog coding examples for each configuration of this RAM, refer to
the ISE HDL Language Templates in the ISE Project Navigator software.

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For More Information

Consult the Spartan-3E Data Sheet.

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RAMB16_Sn

Primitive: 16384-Bit Data Memory and 2048-Bit Parity Memory, Single-

Port Synchronous Block RAM with Port Width (n) Configured to 1, 2, 4,
9, 18, or 36 Bits

WE RAMB16_S1 WE RAMB16_S2 WE RAMB16_S4

EN EN EN
SSR DO [0:0] SSR DO [1:0] SSR DO [3:0]
CLK CLK CLK
ADDR [13:0] ADDR [12:0] ADDR [11:0]

DI [0:0] DI [1:0] DI [3:0]

WE RAMB16_S9 WE RAMB16_S18 WE RAMB16_S36

EN DOP [0:0] EN DOP [1:0] EN DOP [3:0]
SSR SSR SSR
DO [7:0] DO [15:0] DO [31:0]
CLK CLK CLK
ADDR [10:0] ADDR [9:0] ADDR [8:0]

DI [7:0] DI [15:0] DI [31:0]

DIP [0:0] DIP [1:0] DIP [3:0]

X9465

RAMB16_S1 through RAMB16_S36 Representations

RAMB16_S1, RAMB16_S2, RAMB16_S4, RAMB16_S9, RAMB16_S18, and
RAMB16_S36 are dedicated random access memory blocks with synchronous write
capability. The block RAM port has 16384 bits of data memory. RAMB16_S9,
RAMB16_S18, and RAMB16_S36 have an additional 2048 bits of parity memory. The
RAMB16_Sn cell configurations are listed in the following table.
The enable (EN) pin controls read, write, and reset. When EN is Low, no data is

Component Data Cells Parity Cells Address Bus Data Bus Parity Bus

Depth Width Depth Width

RAMB16_S1 16384 1 - - (13:0) (0:0) -
RAMB16_S2 8192 2 - - (12:0) (1:0) -
RAMB16_S4 4096 4 - - (11:0) (3:0) -
RAMB16_S9 2048 8 2048 1 (10:0) (7:0) (0:0)
RAMB16_S18 1024 16 1024 2 (9:0) (15:0) (1:0)
RAMB16_S36 512 32 512 4 (8:0) (31:0) (3:0)

written and the outputs (DO and DOP) retain the last state. When EN is High and
reset (SSR) is High, DO and DOP are set to SRVAL during the Low-to-High clock
(CLK) transition; if write enable (WE) is High, the memory contents reflect the data at
DI and DIP. When SSR is Low, EN is High, and WE is Low, the data stored in the RAM
address (ADDR) is read during the Low-to-High clock transition. The output value
depends on the mode. By default WRITE_MODE=WRITE_FIRST, when EN and WE

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are High and SSR is Low, the data on the data inputs (DI and DIP) is loaded into the
word selected by the write address (ADDR) during the Low-to-High clock transition.
See “Write Mode Selection” for information on setting the WRITE_MODE.
The above description assumes an active High EN, WE, SSR, and CLK. However, the
active level can be changed by placing an inverter on the port. Any inverter placed on
a RAMB16 port is absorbed into the block and does not use a CLB resource.

Inputs Outputs

GSR EN SSR WE CLK ADDR DI DIP DO DOP RAM Contents

Data RAM Parity RAM
1 X X X X X X X INIT INIT No Chg No Chg
0 0 X X X X X X No Chg No Chg No Chg No Chg
0 1 1 0 ↑ X X X SRVAL SRVAL No Chg No Chg
0 1 1 1 ↑ addr data pdata SRVAL SRVAL RAM(addr) RAM(addr)
=>data =>pdata
0 1 0 0 ↑ addr X X RAM(addr) RAM(addr) No Chg No Chg
0 1 0 1 ↑ addr data pdata No Chga No Chga RAM(addr) RAM(addr)
RAM RAM(addr) =>data =>pdata
(addr)b b
datac pdatac
GSR=Global Set Reset signal

INIT=Value specified by the INIT attribute for data memory. Default is all zeros.
SRVAL=Value after assertion of SSR as specified by the SRVAL attribute.

addr=RAM address
RAM(addr)=RAM contents at address ADDR
data=RAM input data
pdata=RAM parity data

aWRITE_MODE=NO_CHANGE
bWRITE_MODE=READ_FIRST
cWRITE_MODE=WRITE_FIRST

Initializing Memory Contents of a Single-Port RAMB16

You can use the INIT_xx attributes to specify an initialization value for the memory
contents of a RAMB16 during device configuration. The initialization of each
RAMB16_Sn is set by 64 initialization attributes (INIT_00 through INIT_3F) of 64 hex
values for a total of 16384 bits.
You can use the INITP_xx attributes to specify an initial value for the parity memory
during device configuration or assertion. The initialization of the parity memory for
ports configured for 9, 18, or 36 bits is set by 8 initialization attributes (INITP_00
through INITP_07) of 64 hex values for a total of 2048 bits.
If any INIT_xx or INITP_xx attribute is not specified, it is configured as zeros. Partial
strings are padded with zeros to the left.
See the Constraints Guide for more information on these attributes.

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Initializing the Output Register of a Single-Port RAMB16

In Spartan-3E, each bit in the output register can be initialized at power on to either a
0 or 1. In addition, the initial state specified for power on can be different than the
state that results from assertion of a set/reset. Two types of properties control
initialization of the output register for a single-port RAMB16: INIT and SRVAL. The
INIT attribute specifies the output register value at power on. You can use the SRVAL
attribute to define the state resulting from assertion of the SSR (set/reset) input.
The INIT and SRVAL attributes specify the initialization value as a hexadecimal
String. The value is dependent upon the port width. For example, for a RAMB16_S1
with port width equal to 1, the output register contains 1 bit. Therefore, the INIT or
SRVAL value can only be specified as a 1 or 0. For RAMB16_S4 with port width equal
to 4, the output register contains 4 bits. In this case, you can specify a hexadecimal
value from 0 through F to initialize the 4 bits of the output register.
For those ports that include parity bits, the parity portion of the output register is
specified in the high order bit position of the INIT or SRVAL value.
The INIT and SRVAL attributes default to zero if they are not set by the user.

Write Mode Selection

The WRITE_MODE attribute controls RAMB16 memory and output contents. By
default, the WRITE_MODE is set to WRITE_FIRST. This means that input is read,
written to memory, and then passed to output. You can set the WRITE_MODE to
READ_FIRST to read the memory contents, pass the memory contents to the outputs,
and then write the input to memory. Or, you can set the WRITE_MODE to
NO_CHANGE to have the input written to memory without changing the output.

Usage
This design element can be inferred or instantiated. The instantiation code is shown
below. For information on how to infer RAM, see the XST User Guide.

Available Attributes
Attribute Type Allowed Values Default Description
INIT Binary/Hexa- Any All zeros Identifies the initial
decimal value of the DO
output port after
completing
configuration. The bit
width is dependent
on the width of the A
or B port of the RAM.
INIT_00 ? Binary/Hexa- Any All zeros Specifies the initial
INIT_3F decimal contents of the data
portion of the RAM
array.
INITP_00 ? Binary/Hexa- Any All zeros Specifies the initial
INITP_07 decimal contents of the parity
portion of the RAM
array.

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Attribute Type Allowed Values Default Description

SRVAL Binary/Hexa- Any All zeros Allows the individual
decimal selection of whether
the DO output port
sets (go to a one) or
reset (go to a zero)
upon the assertion of
the SSR pin. The bit
width is dependent
on the width of the A
or B port of the RAM.
WRITE_ String "WRITE_FIRST", "WRITE_ Specifies the behavior
MODE "READ_FIRST" or FIRST” of the DO port upon a
"NO_CHANGE” write command to the
respected port. If set
to "WRITE_FIRST",
the same port that is
written to displays the
contents of the
written data to the
outputs upon
completion of the
operation.
"READ_FIRST"
displays the prior
contents of the RAM
to the output port
prior to writing the
new data.
"NO_CHANGE"
keeps the previous
value on the output
port and won’t
update the output
port upon a write
command. This is the
suggested mode if not
using the read data
from a particular port
of the RAM.

VHDL and Verilog Instantiation

For VHDL and Verilog coding examples for each configuration of this RAM, refer to
the ISE HDL Language Templates in the ISE Project Navigator software.

For More Information

Consult the Spartan-3E Data Sheet.

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ROM16X1
Primitive: 16-Deep by 1-Wide ROM

ROM16X1 is a 16-word by 1-bit read-only memory. The data output (O) reflects the
word selected by the 4-bit address (A3 – A0). The ROM is initialized with the INIT =
A0 ROM16X1 O value parameter during configuration. The value consists of four hexadecimal digits
A1 that are written into the ROM from the most-significant digit A=FH to the least-
A2 significant digit A=0H. For example, the INIT=10A7 parameter produces the data
stream:
A3
0001 0000 1010 0111
An error occurs if the INIT=value is not specified.
X4137
Usage
This design element should be instantiated rather than inferred.

Available Attributes
Attribute Type Allowed Values Default Description
INIT Hexa- Any 16-bit value. All zeros Specifies the contents of the
decimal ROM.

VHDL Instantiation Template

-- ROM16X1 : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (ROM16X1_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- ROM16X1: 16 x 1 Asynchronous Distributed => LUT ROM

-- Xilinx HDL Libraries Guide Version 8.1i

ROM16X1_inst : ROM16X1
generic map (
INIT => X"0000")
port map (
O => O, -- ROM output
A0 => A0, -- ROM address[0]
A1 => A1, -- ROM address[1]
A2 => A2, -- ROM address[2]
A3 => A3 -- ROM address[3]
);

-- End of ROM16X1_inst instantiation

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ROM16X1

Verilog Instantiation Code

// ROM16X1 : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (ROM16X1_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connect.

// <-----Cut code below this line---->

// ROM16X1: 16 x 1 Asynchronous Distributed (LUT) ROM

// All FPGAs
// Xilinx HDL Libraries Guide Version 8.1i

ROM16X1 #(
.INIT(16'h0000) // Contents of ROM
) ROM16X1_inst (
.O(O), // ROM output
.A0(A0), // ROM address[0]
.A1(A1), // ROM address[1]
.A2(A2), // ROM address[2]
.A3(A3) // ROM address[3]
);

// End of ROM16X1_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

156 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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ROM32X1

ROM32X1
Primitive: 32-Deep by 1-Wide ROM

ROM32X1 is a 32-word by 1-bit read-only memory. The data output (O) reflects the
ROM32X1 word selected by the 5-bit address (A4 – A0). The ROM is initialized with the INIT =
A0 O value parameter during configuration. The value consists of eight hexadecimal digits
A1 that are written into the ROM from the most-significant digit A=1FH to the least-
A2 significant digit A=00H. For example, the INIT=10A78F39 parameter produces the
A3 data stream:
A4
0001 0000 1010 0111 1000 1111 0011 1001

X4130 An error occurs if the INIT=value is not specified.

Usage
This design element should be instantiated rather than inferred.

Available Attributes
Attribute Type Allowed Values Default Description
INIT Hexa- Any 32-bit value. All zeros Specifies the contents of
decimal the ROM.

VHDL Instantiation Template

-- ROM32X1 : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (ROM32X1_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- ROM32X1: 32 x 1 Asynchronous Distributed => LUT ROM

-- Xilinx HDL Libraries Guide Version 8.1i

ROM32X1_inst : ROM32X1
generic map (
INIT => X"00000000")
port map (
O => O, -- ROM output
A0 => A0, -- ROM address[0]
A1 => A1, -- ROM address[1]
A2 => A2, -- ROM address[2]
A3 => A3, -- ROM address[3]
A4 => A4 -- ROM address[4]
);
-- End of ROM32X1_inst instantiation

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ROM32X1

Verilog Instantiation Code

// ROM32X1 : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (ROM32X1_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connect.

// <-----Cut code below this line---->

// ROM32X1: 32 x 1 Asynchronous Distributed (LUT) ROM

// All FPGAs
// Xilinx HDL Libraries Guide Version 8.1i

ROM32X1 #(
.INIT(32'h00000000) // Contents of ROM
) ROM32X1_inst (
.O(O), // ROM output
.A0(A0), // ROM address[0]
.A1(A1), // ROM address[1]
.A2(A2), // ROM address[2]
.A3(A3), // ROM address[3]
.A4(A4) // ROM address[4]
);

// End of ROM32X1_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

158 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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ROM64X1

ROM64X1
Primitive: 64-Deep by 1-Wide ROM

ROM64X1 is a 64-word by 1-bit read-only memory. The data output (O) reflects the
A0 ROM64X1 O word selected by the 6-bit address (A5 – A0). The ROM is initialized with an INIT =
A1 value parameter during configuration. The value consists of 16 hexadecimal digits
A2 that are written into the ROM from the most-significant digit A=FH to the least-
A3 significant digit A=0H.
A4 An error occurs if the INIT=value is not specified.
A5

X9730
Usage
This design element should be instantiated rather than inferred.

Available Attributes
Attribute Type Allowed Values Default Description
INIT Hexa- Any 64-bit value. All zeros Specifies the contents of the
decimal ROM.

VHDL Instantiation Template

-- ROM64X1 : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (ROM64X1_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- ROM64X1: 64 x 1 Asynchronous Distributed => LUT ROM

-- FPGAs.
-- Xilinx HDL Libraries Guide Version 8.1i

ROM64X1_inst : ROM64X1
generic map (
INIT => X"0000000000000000")
port map (
O => O, -- ROM output
A0 => A0, -- ROM address[0]
A1 => A1, -- ROM address[1]
A2 => A2, -- ROM address[2]
A3 => A3, -- ROM address[3]
A4 => A4, -- ROM address[4]
A5 => A5 -- ROM address[5]
);

-- End of ROM64X1_inst instantiation

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ROM64X1

Verilog Instantiation Code

// ROM64X1 : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (ROM64X1_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connect.

// <-----Cut code below this line---->

// ROM64X1: 64 x 1 Asynchronous Distributed (LUT) ROM

// FPGAs.
// Xilinx HDL Libraries Guide Version 8.1i

ROM64X1 #(
.INIT(64'h0000000000000000) // Contents of ROM
) ROM64X1_inst (
.O(O), // ROM output
.A0(A0), // ROM address[0]
.A1(A1), // ROM address[1]
.A2(A2), // ROM address[2]
.A3(A3), // ROM address[3]
.A4(A4), // ROM address[4]
.A5(A5) // ROM address[5]
);

// End of ROM64X1_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

160 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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ROM128X1

ROM128X1
Primitive: 128-Deep by 1-Wide ROM

ROM128X1 is a 128-word by 1-bit read-only memory. The data output (O) reflects the
A0 ROM128X1 O word selected by the 7-bit address (A6 – A0). The ROM is initialized with an INIT =
A1 value parameter during configuration. The value consists of 32 hexadecimal digits
A2 that are written into the ROM from the most-significant digit A=FH to the least-
A3 significant digit A=0H.
A4
An error occurs if the INIT=value is not specified.
A5
A6
Usage
X9731
This design element should be instantiated rather than inferred.

Available Attributes
Attribute Type Allowed Values Default Description
INIT Hexa- Any 128-bit value. All zeros Specifies the contents of
decimal the ROM.

VHDL Instantiation Template

-- ROM128X1 : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (ROM128X1_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- ROM128X1: 128 x 1 Asynchronous Distributed => LUT ROM

-- FPGAs.
-- Xilinx HDL Libraries Guide Version 8.1i

ROM128X1_inst : ROM128X1
generic map (
INIT => X"00000000000000000000000000000000")
port map (
O => O, -- ROM output
A0 => A0, -- ROM address[0]
A1 => A1, -- ROM address[1]
A2 => A2, -- ROM address[2]
A3 => A3, -- ROM address[3]
A4 => A4, -- ROM address[4]
A5 => A5, -- ROM address[5]
A6 => A6 -- ROM address[6]
);

-- End of ROM128X1_inst instantiation

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ROM128X1

Verilog Instantiation Code

// ROM128X1 : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (ROM128X1_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connect.

// <-----Cut code below this line---->

// ROM128X1: 128 x 1 Asynchronous Distributed (LUT) ROM

// FPGAs.
// Xilinx HDL Libraries Guide Version 8.1i

ROM128X1 #(
.INIT(128'h00000000000000000000000000000000) // Contents of ROM
) ROM128X1_inst (
.O(O), // ROM output
.A0(A0), // ROM address[0]
.A1(A1), // ROM address[1]
.A2(A2), // ROM address[2]
.A3(A3), // ROM address[3]
.A4(A4), // ROM address[4]
.A5(A5), // ROM address[5]
.A6(A6) // ROM address[6]
);

// End of ROM128X1_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

162 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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ROM256X1

ROM256X1
Primitive: 256-Deep by 1-Wide ROM

ROM256X1 is a 256-word by 1-bit read-only memory. The data output (O) reflects the
A0 ROM256X1 O word selected by the 8-bit address (A7– A0). The ROM is initialized with an
A1 INIT=value parameter during configuration. The value consists of 64 hexadecimal
A2 digits that are written into the ROM from the most-significant digit A=FH to the least-
A3 significant digit A=0H.
A4
A5 An error occurs if the INIT=value is not specified.
A6
A7
Usage
X9732
This design element should be instantiated rather than inferred.

Available Attributes
Attribute Type Allowed Values Default Description
INIT Hexa- Any 256-bit value. All zeros Specifies the contents of
decimal the ROM.

VHDL Instantiation Template

-- ROM256X1 : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (ROM256X1_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- ROM256X1: 256 x 1 Asynchronous Distributed => LUT ROM

-- FPGAs.
-- Xilinx HDL Libraries Guide Version 8.1i

ROM256X1_inst : ROM256X1
generic map (
INIT => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
O => O, -- ROM output
A0 => A0, -- ROM address[0]
A1 => A1, -- ROM address[1]
A2 => A2, -- ROM address[2]
A3 => A3, -- ROM address[3]
A4 => A4, -- ROM address[4]
A5 => A5, -- ROM address[5]
A6 => A6 -- ROM address[6]
A7 => A7 -- ROM address[7]
);

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ROM256X1

-- End of ROM256X1_inst instantiation

Verilog Instantiation Code

// ROM256X1 : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (ROM256X1_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connect.

// <-----Cut code below this line---->

// ROM256X1: 256 x 1 Asynchronous Distributed (LUT) ROM

// FPGAs.
// Xilinx HDL Libraries Guide Version 8.1i

ROM256X1 #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000) // Contents of ROM
) ROM256X1_inst (
.O(O), // ROM output
.A0(A0), // ROM address[0]
.A1(A1), // ROM address[1]
.A2(A2), // ROM address[2]
.A3(A3), // ROM address[3]
.A4(A4), // ROM address[4]
.A5(A5), // ROM address[5]
.A6(A6) // ROM address[6]
.A7(A7) // ROM address[7]
);

// End of ROM256X1_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

164 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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SRLC16E

SRLC16E
Primitive: 16-Bit Shift Register Look-Up-Table (LUT) with Carry and
Clock Enable

SRLC16E is a shift register look up table (LUT) with carry and clock enable. The
D SRLC16E
CE Q
inputs A3, A2, A1, and A0 select the output length of the shift register. The shift
CLK Q15
register can be of a fixed, static length or it can be dynamically adjusted.
A0 The shift register LUT contents are initialized by assigning a four-digit hexadecimal
A1
number to an INIT attribute. The first, or the left-most, hexadecimal digit is the most
A2
significant bit. If an INIT value is not specified, that value defaults to a value of four
A3
zeros (0000) so that the shift register LUT is cleared during configuration.
X9298 The data (D) is loaded into the first bit of the shift register during the Low-to-High
clock (CLK) transition. When CE is High, during subsequent Low-to-High clock
transitions, data is shifted to the next highest bit position as new data is loaded. The
data appears on the Q output when the shift register length determined by the
address inputs is reached.
The Q15 output is available for the user to cascade multiple shift register LUTs to
create larger shift registers.

Inputs Output

Am CLK CE D Q Q15
Am X 0 X Q(Am) Q(15)
Am X 1 X Q(Am) Q(15)
Am ↑ 1 D Q(Am - 1) Q15
m= 0, 1, 2, 3

Usage
This design element can be inferred or instantiated.

Available Attributes
Attribute Type Allowed Values Default Description
INIT 16-Bit 16-Bit Hexadecimal 16'h0000 Sets the initial value of
Hexa- content and output of
decimal shift register after
configuration

VHDL Instantiation Template

-- SRLC16E : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (SRL16E_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library

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SRLC16E

-- Xilinx : contains the component declarations for all Xilinx

-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- SRLC16E: 16-bit cascable shift register LUT with clock enable operating on posedge of clock
-- FPGAs.
-- Xilinx HDL Libraries Guide version 8.1i

SRLC16E_inst : SRLC16E
generic map (
INIT => X"0000")
port map (
Q => Q, -- SRL data output
Q15 => Q15, -- Carry output (connect to next SRL)
A0 => A0, -- Select[0] input
A1 => A1, -- Select[1] input
A2 => A2, -- Select[2] input
A3 => A3, -- Select[3] input
CE => CE, -- Clock enable input
CLK => CLK, -- Clock input
D => D -- SRL data input
);

-- End of SRLC16E_inst instantiation

Verilog Instantiation Code

// SRLC16E : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (SRL16E_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// SRLC16E: 16-bit cascable shift register LUT with clock enable operating on posedge of clock
// FPGAs.
// Xilinx HDL Libraries Guide Version 8.1i

SRLC16E #(
.INIT(16'h0000) // Initial Value of Shift Register
) SRLC16E_inst (
.Q(Q), // SRL data output
.Q15(Q15), // Carry output (connect to next SRL)
.A0(A0), // Select[0] input
.A1(A1), // Select[1] input
.A2(A2), // Select[2] input
.A3(A3), // Select[3] input
.CE(CE), // Clock enable input
.CLK(CLK), // Clock input
.D(D) // SRL data input
);

// End of SRLC16E_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet.

166 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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STARTUP_SPARTAN3E

STARTUP_SPARTAN3E
Primitive: Spartan-3E User Interface to the GSR, GTS, Configuration
Startup Sequence and Multi-Boot Trigger Circuitry
The STARTUP_SPARTAN3E component allows the connection of ports, or user
circuitry, to control certain dedicated circuitry and routes within the FPGA. Signals
GSR
STARTUP_SPARTAN3E connected to the GSR port of this component can control the global set/reset (referred
to as GSR) of the device. The GSR net connects to all registers in the device and places
GTS the registers into their initial value state. Connecting a signal to the GTS port connects
MBT that port to the dedicated route controlling the 3-state outputs of every pin in the
device. Connecting a clock signal to the CLK input allows the startup sequence after
CLK configuration to be synchronized to a user defined clock. The MBT (Multi-Boot
Trigger) pin allows the triggering of a new configuration.
X10235

Usage
The STARTUP_SPARTAN3E component must be instantiated to be incorporated into
a design. Do not connect any input not needed for the design.

VHDL Instantiation Template

-- STARTUP_SPARTAN3E : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (STARTUP_SPARTAN3E_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : connect this function to the design. Delete or comment
-- : out inputs/outs that are not necessary.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- STARTUP_SPARTAN3E: Startup primitive for GSR, GTS, startup sequence

-- control and Multi-Boot Configuration. Spartan-3E
-- Xilinx HDL Libraries Guide version 8.1i

STARTUP_SPARTAN3E_inst : STARTUP_SPARTAN3E
port map (
CLK => CLK, -- Clock input for start-up sequence
GSR => GSR_PORT, -- Global Set/Reset input (GSR cannot be used for the port name)
GTS => GTS_PORT -- Global 3-state input (GTS cannot be used for the port name)
MBT => MBT -- Multi-Boot Trigger input
);

-- End of STARTUP_SPARTAN3E_inst instantiation

Verilong Instantiation Template

// STARTUP_SPARTAN3E : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (STARTUP_SPARTAN3E_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and

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STARTUP_SPARTAN3E

// : connect this function to the design. Delete or comment

// : out inputs/outs that are not necessary.

// <-----Cut code below this line---->

// STARTUP_SPARTAN3E: Startup primitive for GSR, GTS, startup sequence control

// and Multi-Boot Configuration Trigger. Spartan-3E
// Xilinx HDL Libraries Guide Version 8.1i

STARTUP_SPARTAN3E STARTUP_SPARTAN3E_inst (
.CLK(CLK), // Clock input for start-up sequence
.GSR(GSR_PORT), // Global Set/Reset input (GSR can not be used as a port name)
.GTS(GTS_PORT), // Global 3-state input (GTS can not be used as a port name)
.MBT(MBT) // Multi-Boot Trigger input
);

// End of STARTUP_SPARTAN3E_inst instantiation

For More Information

Consult the Spartan-3E Data Sheet. Also see the Synthesis and Verification Design
Guide for more information on using the GSR and GTS signals of the
STARTUP_SPARTAN3E component.

168 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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XORCY

XORCY

Primitive: XOR for Carry Logic with General Output

XORCY is a special XOR with general O output used for generating faster and smaller
LI arithmetic functions.
O
CI
Usage
X8410 Its O output is a general interconnect. See also “XORCY_D”and “XORCY_L”.

VHDL Instantiation Code

-- XORCY : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (XORCY_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- XORCY: Carry-Chain XOR-gate with general output

-- Xilinx HDL Libraries Guide version 8.1i

XORCY_inst : XORCY
port map (
O => O, -- XOR output signal
CI => CI, -- Carry input signal
LI => LI -- LUT4 input signal
);

-- End of XORCY_inst instantiation

Verilog Instantiation Code

// XORCY : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (XORCY_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// XORCY: Carry-Chain XOR-gate with general output

// For use with All FPGAs
// Xilinx HDL Libraries Guide Version 8.1i

XORCY XORCY_inst (
.O(O), // XOR output signal
.CI(CI), // Carry input signal
.LI(LI) // LUT4 input signal
);

// End of XORCY_inst instantiation

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For More Information

Consult the Spartan-3E Data Sheet.

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XORCY_D

XORCY_D
Primitive: XOR for Carry Logic with Dual Output

XORCY_D is a special XOR used for generating faster and smaller arithmetic
LO functions.
LI
O Usage
CI
XORCY_D has two, functionally identical outputs: O and LO. The O output is a
X8409 general interconnect. The LO output connects to another output within the same CLB
slice.

VHDL Instantiation Code

-- XORCY_D : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (XORCY_D_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- XORCY_D: Carry-Chain XOR-gate with local and general outputs

-- Xilinx HDL Libraries Guide Version 8.1i

XORCY_D_inst : XORCY_D
port map (
LO => LO, -- XOR local output signal
O => O, -- XOR general output signal
CI => CI, -- Carry input signal
LI => LI -- LUT4 input signal
);

-- End of XORCY_D_inst instantiation

Verilog Instantiation Code

// XORCY_D : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (XORCY_D_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// XORCY_D: Carry-Chain XOR-gate with local and general outputs

// For use with All FPGAs
// Xilinx HDL Libraries Guide Version 8.1i

XORCY_D XORCY_D_inst (
.LO(LO), // XOR local output signal
.O(O), // XOR general output signal

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.CI(CI), // Carry input signal

.LI(LI) // LUT4 input signal
);

// End of XORCY_D_inst instantiation.

For More Information

Consult the Spartan-3E Data Sheet.

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XORCY_L

XORCY_L

Primitive: XOR for Carry Logic with Local Output

XORCY_L is a special XOR with local LO output used for generating faster and
LO smaller arithmetic functions.
LI
CI Usage
The LO output connects to another output within the same CLB slice.
X8404

VHDL Instantiation Code

-- XORCY_L : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (XORCY_L_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use

-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that are used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- XORCY_L: Carry-Chain XOR-gate with local => direct-connect ouput

-- Xilinx HDL Libraries Guide Version 8.1i

XORCY_L_inst : XORCY_L
port map (
LO => LO, -- XOR local output signal
CI => CI, -- Carry input signal
LI => LI -- LUT4 input signal
);

-- End of XORCY_L_inst instantiation

Verilog Instantiation Code

// XORCY_L : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (XORCY_L_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// XORCY_L: Carry-Chain XOR-gate with local (direct-connect) ouput

// For use with All FPGAs
// Xilinx HDL Libraries Guide Version 8.1i

XORCY_L XORCY_L_inst (
.LO(LO), // XOR local output signal
.CI(CI), // Carry input signal
.LI(LI) // LUT4 input signal
);

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// End of XORCY_L_inst instantiation.

For More Information

Consult the Spartan-3E Data Sheet.

174 www.xilinx.com Spartan-3E Libraries Guide for HDL Designs

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