ESE 570 MOS INVERTERS STATIC

(DC Steady State)

CHARACTERISTICS

Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 1

 VDD

Vin Vout

Ideal VTC Logic “0” = 0 V

Logic “1” = VDD

Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 2

 VOH ≤ VDD

o.c.
VOL ≥ 0
Cout

For DC steady-state Cout is open VDD

circuit.

VDD
0
VOL
Kenneth R. Laker, University of Pennsylvania, updated 12Feb15
VT0n 3
 VOH ≤ VDD → max output voltage when the logic output is “1”
VOL ≥ 0 → min output voltage when the logic output is “0”
VIL → max input voltage that can be interpreted as a logic “0”
VIH → min input voltage that can be interpreted as a logic “1”

NOTE: VIL ≥ VOL and VIH ≤ VOH

VDD

Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 4

 Slope of VTC
or
inverter gain

Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 5

 Steady-State (Static) Output Voltage Behavior

(oC)
Tj = Ta + ΘP (oC)
Θ -> Thermal Resistance (oC/W)
P → Pstatic, Pdynamic (W)

PDC = Pstatic = VDD ID (Vin = VOH or VOL)

V DD
P static= [ I D .V in =V OL /*I D .V in =V OH /]
2
Minimum area nMOS, pMOS transistor layouts limited by design rules
Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 6
 Minimum Area (Unit) MOS Transistor Layouts

Unit pMOS Layout

281

61 31 41
31
41 14 1
21
51 21 51 21
2 2 41
Area=28∗14 1 =392 1 21

Unit nMOS Layout

201
61 31 81
41
21 41 E2 = 2λ
21
21
2 2
Area=20∗8 1 =160 1
11
Unit Dimensions: L nu=L pu=2 1 ; W nu =W pu =4 1
Relevant Design Rules
Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 7
 VSB

kn'
kn' = KPn = A/V2

Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 8

“Visual” Representation of the Resistive-Load Inverter
NMOS driver transistor

A ID = 0
C
<
B

≥
Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 9
 CALCULTION OF VOH

VDD

Vin = 0 < VT0,n => nMOS Cut-off

Vout = VOH = VDD

Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 10

 CALCULTION OF VOL

Vin = VDD
implies

Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 11

 CALCULTION OF VIL

-1

VIL

@ Vin = VIL

Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 12

 CALCULTION OF VIH

VIH

Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 13

 CALCULTION OF VIH CONT.

Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 14

 CALCULTION OF Vth

Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 15

 VDD

0 VT0n VDD
Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 16
 Take Limit as knRL -> ∞

-> VT0n

-> VT0n 1
V out .V in=V IL /=V DD − -> VDD
k n RL
-> VT0n
V out .V in =V IH /=
-
2 V DD
3 k n RL
-> 0

-> 0

Vout
VDD
knRL -> ∞

semi-ideal VTC
Vin
0 VT0n VDD
Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 17
 1

V DD
P static .average/= [ I D .V in =0/* I D .V in =V DD /]
2

Vin = 0
P(Vin = “0”) = 0

Vin = VDD Vout = VOL

V DD −V OL
ID(Vin = “1”) = IL =
RL
V DD −V OL
P(Vin = “1”).=V DD
RL

Pstatic (average)

Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 18

 VDD

Multiplying by RL
W 30 x 2.V
10 −6
W
DD −V OL / 2.5−0.2/
R
5−0.2=
L = ' R 2
=
[2.5−1/0.2−.0.2/
2
−6 ] 2
0
L k n .2.V
2 DD−VLT0n/V OL −V OL / 30 x 10 .2.5−1/0.2−.0.2/ /
L

W
R L=2.05 x 105 0 NO UNIQUE W/L, RL
L
Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 19
 W 5
R L =2.05 x 10 0
L

Pstatic (average) [mW]

V DD V DD −V OL
P static .average /=
2 RL

Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 20

 VOL = 0.147 V or 8.503 V ?

Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 21

 Preferred Design

Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 22

 SATURATED NMOS ENHANCEMENT-LOAD INVERTER

VSB,L ≠ 0

VSB,d
VSB,L

Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 23

 SATURATED NMOS ENHANCEMENT-LOAD INVERTER

Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 24

 NMOS DEPLETION-LOAD INVERTER

ENH& DEP LOADS REPLACED BY CMOS!

Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 25

 QUICK REVIEW
“Visual” Representation of the NMOS
Resistive-Load Inverter
driver transistor

A ID = 0
C
<
B

≥
Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 26
 QUICK REVIEW

VDD

0 VT0n VDD
Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 27
 QUICK REVIEW
W 5
R L =2.05 x 10 0
L
Pstatic (average) [mW]

V DD V DD −V OL
P static .average /=
2 RL

Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 28

 => VGSp = Vin - VDD

=> VDSp = Vout - VDD

IDn = IDp

≤
≤

≥
≥
Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 29
 “Visual” Representation of the CMOS Inverter
A

Vout Vout = Vin - VT0p

A E
V OH =V DD -1 Vout = Vin - VT0n
LIN LIN E
SAT
&
OFF
V in+V T0n SAT
LIN
LIN
& V in,V DD *V T0p
-VT0p OFF
-1
V OL=0 Vin
VT0n V th V DD
-VT0n V IL V IH VDD+VT0p
Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 30
 “Visual” Representation of the CMOS Inverter

Vout Vout = Vin - VT0p

A E
V OH =V DD -1 Vout = Vin - VT0n
LIN LIN
&
SAT
SAT
SAT
SAT LIN
&
SAT LIN
-VT0p &
-1 SAT
V OL=0 Vin
VT0n V th V DD
-VT0n V IL V IH VDD+VT0p
Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 31
 IDn = IDp

-1 Vout = Vin - VT0p

Vout = Vin - VT0n

V th−V T0p

V th
V th−V T0n
V out
=∞ (iff λ = 0)
V in
-1
V th V DD
-VT0n
V IL V IH
Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 32
 IDn = IDp = 0

0=

IDn = IDp = 0

=0
Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 33
 IDn = IDp

Eq.(1)

Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 34

 (1)
Eq.(1)

(and set Vin = VIL)

(-1)
' VIL ' VIL
k Wn k W p d V out
. / 2.V in −V T0n /= . / [2.V out −V DD /*2.V in −V DD −V T0p / ]
2 L n 2 L p d V in
d V out (-1)
¿[−2.V out −V DD / ]
d V in

Eq.(2)

SOLVE Eq. (1) and Eq. (2) for Vout and VIL or use simulation.
Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 35
 IDn = IDp

Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 36

 Eq.(3)

Eq.(4)

SOLVE Eq. (3) and Eq. (4) for Vout and VIH or use simulation.
Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 37
 IDn = IDp

Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 38

Setting for Vin = Vth and solving for Vth

Eq.(5)

where k 'n .W / L/n2n .W / L/n

k R= ' =
k p .W / L/ p 2 p .W / L/ p
RECALL THAT
2n ,2 p

Usually Ln = Lp is set to min L:

k 'n .W / L/n 2n W n
k R= ' =
k p .W / L/ p 2 p W p

Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 39

 DESIGN OF CMOS INVERTERS

V th =
V T0n *
- 1
kR
.V DD *V T0p /
Eq.(5)
Eq.(5)
1*
1
-
kR
2 Important design
V DD *V T0p −V th
Solving Eq.(5) for kR k R =.
V th −V T0n
/ Eq. for CMOS
inverter VTC.

1
If Vth is ideal Vth
set to V th =V th .ideal /= 2 V DD
0.5V DD *V T0p 2 2n .W / L/n
k R=. /=
0.5 V DD −V T0n 2 p .W / L/ p
Symmetric CMOS Inverter
W p 2n W n
V If Vand
If,th(ideal)
also VT0n = -V
and V = -VV
= =>=(k
V )symmetric =1.k=> / . /=
=1 . /
th(ideal) T0p
T0n T0T0p RT0 R Lp
symetric 2 p Ln

Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 40

 Vth vs. 1/kR

1 2p W p
=
k R 2n W n
where Ln = Lp
Vth (volts)

1/kR

V th =
V T0n *
-1
kR
.V DD *V T0p /
VDD = 5V; VT0n = - VT0p = 1 V
1*
- 1
kR
Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 41
Symmetric CMOS inverter Vth(ideal) and VT0n = - VT0p = VT0 => .k R /symetric =1

.W / L/ p ≈2.52 .W / L/n

FROM Eq. (1) and Eq. (2)

FROM Eq. (3) and Eq. (4)

Symmetrical

Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 42

 DERIVE: for Symmetric CMOS Inverter
Symmetric CMOS inverter: Vth = VDD/2, VT0n = - VT0p = VT0 and kR = 1

Eq.(1)

1
Eq.(2) => V IL =V out − 2 V DD
Substitute V out =V IL * 1 V DD , V = V and Sym-Inv Cond. into Eq.(1), i.e.
2 in IL

V 2IL −2V IL V T0 *V 2T0

1
.=2 V 2IL −2V IL V DD *2 V IL V T0 −V IL V DD *V 2DD −V T0 V DD −V 2IL *V IL V DD − V 2DD
4
2 3
2 V IL V DD −4 V IL V T0 =−V T0 −V T0 V DD * V 2DD
4
3
V IL .2 V DD −4V T0 /= V 2DD −V T0 V DD −V 2T0 V = 1 .3V DD *2V T0 /.V DD −2V T0 /
4 IL QED
8 V −2V
DD T0
Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 43
EXAMPLE: Compute the noise margins for a symmetric CMOS
inverter has been designed to achieve Vth = VDD/2, where VDD = 5 V
and VT0n = - VT0p = 1 V.

V DD
5 2 3 2
NM H =V OH −V IH =V DD −. V DD − V T0 /= V DD * V T0 =2.125V
0 8 8 8 8
3 2 3 2
NM L =V IL −V OL=V IL = V DD * V T0 = V DD * V T0 =2.125V
8 8 8 8

RECALL (with VDD = 5 V)

1. NMH, NML > VDD/4 = 1.25 V
2. Ideal NM => NMH = NML = 2.5 V > VDD/2

Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 44

Pstatic

Pstatic = 0
Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 45
If the inverter cell is part of a
standard cell library, it will adhere Smaller Area
to the cell layout protocols. Layout

Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 46

 VDD ≥ Vout > - VT0p

Pstatic > 0
Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 47