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1.given An Input Clock of 1Mhz, Convert It To 1Hz For Timer. Please Finish Your Design by Using Systemverilog

The document provides a SystemVerilog code to convert an input clock of 1MHz to an output clock of 1Hz for use in a timer circuit. It does this by using a counter that counts from 0 to 50,000,000 on each clock cycle, only toggling the output cout when the count reaches 50,000,000, effectively dividing the input clock frequency by 50,000,000 to get an output frequency of 1Hz. A second example is provided to convert a 50MHz clock to a 1Hz clock using a 28-bit counter that counts to 25,000,000 on each cycle.

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16 views2 pages

1.given An Input Clock of 1Mhz, Convert It To 1Hz For Timer. Please Finish Your Design by Using Systemverilog

The document provides a SystemVerilog code to convert an input clock of 1MHz to an output clock of 1Hz for use in a timer circuit. It does this by using a counter that counts from 0 to 50,000,000 on each clock cycle, only toggling the output cout when the count reaches 50,000,000, effectively dividing the input clock frequency by 50,000,000 to get an output frequency of 1Hz. A second example is provided to convert a 50MHz clock to a 1Hz clock using a 28-bit counter that counts to 25,000,000 on each cycle.

Uploaded by

afdsjiodasfjknafdkj
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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1.Given an input clock of 1MHz, convert it to 1Hz for timer.

Please finish your design by using


SystemVerilog.

1. module Lab6a(clock, reset, cout);


2. input clock, reset;
3. output cout;
4.
5. reg count; //counts upto 50000000
6. reg cout; //original 4 bit counter
7.
8.
9. always @ (posedge clock)
10. begin
11. if (~reset) begin
12. if(count==50000000) begin
13. count <= 0;
14. cout = cout + 1;
15. end else begin
16. count <= count + 1;
17. cout <= cout;
18. end
19. end else begin
20. count <=0;
21. cout <= 0;
22. end
23. end
24. endmodule

50MHz to 1Hz

module slowClock(clk, reset, clk_1Hz);


input clk, reset;
output clk_1Hz;

reg clk_1Hz = 1'b0;


reg [27:0] counter;

always@(posedge reset or posedge clk)


begin
if (reset == 1'b1)
begin
clk_1Hz <= 0;
counter <= 0;
end
else
begin
counter <= counter + 1;
if ( counter == 25_000_000)
begin
counter <= 0;
clk_1Hz <= ~clk_1Hz;
end
end
end
endmodule

Assume that you have an input clock of 1Hz and switches of SW1, SW2. Please design a timer that will
count how much time you spend in the unit of second (using systemVerilog). SW1 is the

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