A Design Methodology for Implementing DSP with Xilinx@System Generator for

Matlab@

Matthew Ownby Dr. Wagdy H. Mahmoud

Department of Electrical and Computer Engineering Department of Electrical and Computer Engineering
Tennessee Technological University Tennessee Technological University
Box. 5004 Box. 5004
Cookeville, TN 38505 USA Cookeville, TN 38505 USA

Key Words: Simulink, DSP, Matlab, Xilinx

Absnacr- This paper presents a methodology for Field reconfigurabilty of FPGA systems allows
implementing real-time DSP applications on a programming their hardware for a specific inshument
reconfigurable logic platform using Xilinx' System and/or computing system. The use of FPGA systems
Generator for Matlab@. The methodology aims at reduces the overall system development time. The physical
improving the eficiency of learning the use of such and electrical testing of the hardware can be done
complex design system. The methodology steps will be concurrently with the detailed design and programming of
demonstrated using DSP design examples built with the system. Design errors can be caught and easily
Xilinx@System Generator for Matlab'. Assessment of rectified at any stage of the development process. This
the methodology is also discussed. minimizes the effect of errors on the project schedule.

I. INTRODUCTION In recent years, the complexities of hardware designs

have increased significantly. However, due to the ever-
One of the most challenging processes in system decreasing design cycle, and the scarcity of experienced
design is identifying a starling point. In order to guarantee designers, the on-time completion of such design projects
the development of such systems, we need to follow a has become a challenging task. Therefore, designers have
disciplined methodology for the design process. been searching for more cost-effective and automated
Methodologies help us handle complex design efficiently, design tools. Since System Generator is presently
minimize design time, eliminate many sources of errors, considered cutting edge technology, a design methodology
reduce the need for a large number of experienced for its use to implement DSP applications into FPGA
designers, minimize the manpower needed to complete the platform would be beneficial. The developed methodology
design, and generally produce optimal solution designs. addresses the following issues:
The benefits of following such a methodology absolutely
outweigh its development costs. Developing a 1.) Determining the design specifcations
methodology for the hardware implementation of complex, 2.) Designing a system in Simulink@utilizing System
real-time DSP applications on a reconfigurable logic GeneratorB design blocks
platform using Xilinx@System Generator for Matlab@is 3.) Simulating the design in S i m u l i @
the main goal of this paper. The developed methodology 4.) System Generator' Software to produce VHDL
provides a step-by-step template that eases the learning code and test bench
curve of the complex design tools. 5.) Simulate/ Implement VHDL code utilizing
ModelsimW XilinxC3 software
Advances in VLSI process technology have been
applied to the manufacturing of reconiigurable logic II. DETERMINING THE DESIGN SPECIFICAnONS
including field programmable gate arrays (FPGA) chips
and helped their rapid growth in logic capacity, The DSP application chosen for the demonstration of
performance and popularity. The extreme flexibility of the design methodology is a function that measures the
FPGA, the development of elaborate simulation and time delay between two sine waves. This function has
synthesis tools. and the widespread acceptance of applications in a radar system. The goal of this function is
hardware description languages sncb as VHDL and to be able to measure the time delay between two signals
Verilog have made FPGA-based systems the medium of ranging from 10 microseconds to 50 microseconds. Also,
choice for the hardware development and implementation the design must be equipped to disregard any noise
of high-performance. compnte-intensive applications such distortion. In order to detect a delay of 10 microseconds, a
as digital signal processing (DSP) and image processing. sine wave was set at IO KHZ. S i m u l i m states that the
time delay setting has to be greater then signal input

0-7803-7339-1/02/$17.0002002 IEEE
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 --I

Figure 1: System Design

Based on the assumption that the signal needs to be ten

times greater then the transport delay, a frequency of 10
KHZ was used for the project (IOKHZ also works for the
50 microsecond case.). This first step of determining
design specifcations is a standard step for any design
methodology.

m. DESIGN A SYSTEM IN SIMLDKB UTILIZING

SYSTEM GENERATORB DESIGN BLOCKS DCIIF

Figure 2: Analog Input Stage

Familiarity to SimulinkB is helpful at this point.
SimulinkD is a graphical interface that permits a
designerkngineer to develop a graphical model of a
I.) Analog Input
system using MatlabB functions. If you are familiar with
The fust stage of the design is the simulated analog
Sirnulink@to design DSP applications, this step is a matter
input stage as shown in Figure 2. The two sine wave
of using the XilinxB design blocks instead of standard
generators are set to IO KHZ in order to properly
SimulinkB design blocks. If SimulinkB is a new
recognize a 10-microseconddelay. The signal generator in
experience, the SimulinkO User's Guide [l] and
Simulink uses radians per second instead of hertz. Since
S i m u l i B demos are sources of introduction for
SimulinkD. Figure 1 is the design of the.time delay detect the frequency must he approximately 62,831 radians per
second (- 10 KHZ), any setting at or above 62,831 radians
system in SimulinkB.
per a second should be adequate for simulation. For the
simulation, 62.83 1 radiansisecond was initially tested.
As shown in Figure 1, the system consists of five major
With digital logic ranging from 3.3 to 5 volts, the
sections consisting of:
- was set to an amulitude of 5 volts.
- signal
simulation input
For the simulation, the amplitude of the noise was set to
1.) Analog Input
0.2 volts with a frequency of 125,663 radians/second (-20
2.) A/D converter and Comparing
KHZ). The fmal stage of the analog system is the low pass
3.) Set Flag
filters. The purpose of a low pass filter is often to
4.) Counter
eliminate noise such as white noise, transmission line
5.) output noise, etc., from a signal. For the purpose of this
simulation, an eighth order Butterworth low pass filter was
selected [2]. Since the input frequency is set at 62,831
radianskecond, the cut off frequency needs to be greater
then 62,831 and less then 125,663 radians/second (for the
simulation. the cutoff frequency was set to 75,000 radians
per second.)

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2.) A/D Converter and Comparison Stage In order to make the counter work properly, a flag
needs to be set and held until the simulation ended or the
The second stage of the design is the conversion of the system was reset. With any digital system, the best way to
analog (or continuous time) signal into a digital (or hold a value at a certain time would be to use a state
discrete time) signal and the comparison of the two input machine. With the System GeneratorE state machine
waves (Figure 3). block, the state is controlled by a single hit. The best way
to set and hold a flag was to set the output to logical '1'
when the state machine received a signal from the
comparer in stage 2. This is why two state machines are
used (See Figure 4.) When the fmt state machine receives
a signal from the comparer, a signal is sent to the next
stage to start the counting. When the second comparer
sends the signal, the XOR logic stops the signal from
going to the counter.

Figure 3: A D Converter and Comparison Stage 4.j Counter stage

Stages 2 through 5 all use the XiIiiCt design blocks Figure 5a shows the System view of the counter stage.
so that System GeneratorE can convert the design from Figure 5b shows the design of the delay counter. The
Sholink@ to VHDL. To allow an analog input for the counter stage is the beart of the design. The counter starts
FPGA chip, an A/D converter is needed. The A/D counting when the fust signal reaches 2 volts and stops
converter was set to signed, 16 and 8 binary point bits to counting when the second signal reached 2 volts. Since the
allow for the analog signal to swing from +5 volts to - 5 counter is set to count every le-5 samples (the same as the
volts. A sample period of le-5 was set in order to see a sample rate of the A D converter), the counter is counting
delay as little as 10 microseconds. The comparison blocks the delay between the two signals.
are used as a trigger. When the input signals are greater
then 2 volts, a signal is sent from the comparer stage to the
next stage to set a flag for the counter.

3.) Set Flag Stage

Figure 5a: Counter Stage (System View)

Figure 4: Set Flag Stage m

Enrblr

Figure 5b: Delay Counter

After the counter fmishes counting, the output data

has to be normalized. For example. a SO-microsecond
delay will have a result from the counter of 50. To get the
data to the appropriate output, the output is multiplied by a
constant value of le-5. At this point, the data is sent to the
output stage.

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 Figure 6: Output Stage

5.) Output Stage

The output stage (Figure 6) consists of a D/A Figure 8: Output with 3 delay set 10 SO microseconds
converter and an output scope. This stage is not needed for note: Y-axis shows the calculated time delay)
the design to work. For simulation purpose in SimulinkQ,
the D/A is needed in order to display the data to the scope. V. THE SYSTEM GENEXATORQ SOFTWARE TO
PRODUCE VHDL CODE AND TEST BENCH.

N.SIMULATION OF THE DESIGN IN In Figure 1, a X i l i i Q block label System Generatom

SIMULINKQ is part of the design (Figure 9.) The System Generatom
block is the program that generates VHDL code for the
The input signal frequency, noise frequency, and SimulinkQ model that has been created using the XilinxQ
cutoff frequency for the low pass filter are set to the data blocks.
selected above (62,83 1 radiandsecond, 125,663
radianslsecond, and 75,000 radiadsecond, respectively).
The next step is to vary the time delay from 10
microseconds to 50 microseconds. Since the design can
run continuously, the simulation run will he restricted from
System
0 to 0.002 seconds. Figure 7 shows the output at 10 Generator
microseconds. Figure 8 shows the output with the delay
set to 50 microseconds. Figure 9: System Generator Xilinx Block

Figure 7: Output with a delay set to 10 microseconds

(Note: Y-axis shows the calculated time delay)
Figure 10: System Generatom Window

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 Figure 10 shows the System [email protected]
window tells the Xilinxm ISE 4.2 the chip to be used and
the clock speed of the design to be set. For simulation
purpose, the major switch is the “Create Test bench”. This
switch when selected will automatically create a test bench
for the system in VHDL along with creating the VHDL
code of the system.

VI. SIMULATE/ IMPLEMENT VHDL CODE

UTILIZING MODELSIM@/XILINXm SOFTWARE

Along with creating the VHDL code, the System

Generatom program also creates a project file for the
X i l m ISE 4.2 software. The project created allows the
designer to simulate the code in ModelsimQ as well as
program the code into FPGA chip using the Xilinx@ ISE
4.2.

VIl. CONCLUSION/FUTURE WORK

Using System Generato@ digital designers can

implement DSP applications into digital designs faster and
easier using S i m u l i @ and a simple design methodology.

At the time of this paper release. Xilinxm has

developed a newer version OF System Generatofl. With a
newer version of the s o h a r e , the design block for System
Generator@ should improve and become easier to use.
With this development, the design step in this
methodology may need to he updated to reflect new
changes in the software.

M.REFERENCES

[l] Mathworks Inc., “Matlab@ Student Version: Learning

SimulinkQ 4, “ The Mathworks Inc., 2001.
[2] C. Williams, “Designing Digital Filters,” Prentice-
Hall Inc., 1986.
[3] Xilinx Corp, “ X i l i System Generator For
SimulinkQ”. Version 2.1, April 2001.

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