Low-Voltage Differential Signaling (LVDS)

Application Note 1382-6

by Stephen Kempainen, National Semiconductor

Who Should Read This Wherever you need high-speed solutions move information on a
Application Note? data transfer (100 Mb/s and board, between boards, modules,
higher), LVDS offers a solution. shelves, and racks, or box-to-box.
Digital designers utilizing low- There are many applications in The transmission media can be
voltage differential signaling many market segments that use copper cables or printed circuit
(LVDS) for high-speed data LVDS for data transmission. board (PCB) traces. In the future,
transmissiom. These include: LVDS will also carry protocols for
inter-system communication.
LVDS Provides Higher Bit Rates, • stackable hubs for data
Lower Power, and Improved communications Table of Contents
Noise Performance • wireless base stations LVDS Provides Higher Bit Rates,
and ATM switches in Lower Power, and Improved
Due to the Internet’s tremendous telecommunications Noise Performance . . . . . . . . . . . . . . . . . 1
growth, data transfers are • flat-panel displays and servers Generic LVDS. . . . . . . . . . . . . . . . . . . . . . . 2
increasing dramatically in all in the computer market Multiple Technologies and
areas of communications. In addi- • peripherals like printers and Supply Voltages . . . . . . . . . . . . . . . . . . . . 3
tion, data streams for digital digital copy machines Gigabits at Milliwatts . . . . . . . . . . . . . . . 4
video, HDTV, and color graphics • high-resolution displays in Flat Supply Current vs.
are requiring higher and higher industrial applications Operating Frequency . . . . . . . . . . . . . . . . 6
bandwidth. The digital communi- • flat-panel displays in the Low Electromagnetic Interference . . . . 7
cations deluge is the driving force automotive market Cost Benefits . . . . . . . . . . . . . . . . . . . . . . . 8
for high-speed interconnects Many Channels per Chip . . . . . . . . . . . . . . 8
between chips, functional boards, In these applications, high-speed DC Balance for Longer Cables . . . . . . . . 9
and systems. The data may be data moves within and between
Bus LVDS . . . . . . . . . . . . . . . . . . . . . . . . . 10
digital, but it is analog Low- systems. Moving data within a
The Complexities of
Voltage Differential Signaling system (intrasystem data trans- Signal Integrity . . . . . . . . . . . . . . . . . . . . 11
(LVDS) that designers are choos- fer) is the main use for LVDS Serializer/Deserializer Example . . . . . . . 11
ing to drive these high-speed solutions today. Moving informa- LVDS in Low-Power Applications. . . . 12
transmission lines. LVDS’s proven tion between systems (intersys-
Test and Evaluation Considerations . . 13
speed, low power, noise control, tem data transfer) requires stan-
and cost advantages are popular dard communication protocols BER Eye Diagram . . . . . . . . . . . . . . . . . . 15
in point-to-point applications for such as IEEE 1394, Fibre Recovered Clock Jitter . . . . . . . . . . . . . 16
telecommunications, data Channel, and Gigabit Ethernet. ParBERT 81250 Simplifies
communications, and displays. Since the hardware and software the Characterization and
overhead for intersystem proto- Testing of LVDS Devices . . . . . . . . . . . . 17
LVDS uses high-speed analog
circuit techniques to provide cols is too expensive to use for 81200 Provides the Tools
to Test LVDS. . . . . . . . . . . . . . . . . . . . . . . 18
multi-gigabit data transfers on intrasystem data transfers, a sim-
copper interconnects. ple and low-cost LVDS link is an Related Literatute . . . . . . . . . . . . . . . . . 19
attractive alternative. Thus, LVDS Support, Services, and Assistance. . . 20
Generic LVDS

Low-voltage differential signaling The differential receiver is a high-

is a generic interface standard for impedance device that detects
high-speed data transmission. differential signals as low as
The ANSI/TIA/EIA-644-1995 20 mV and then amplifies them
standard specifies the physical into standard logic levels. The sig-
layer as an electronic interface. nal has a typical driver offset of
This standard defines driver and 1.2 V, and the receiver accepts an
receiver electrical characteristics input range of ground to 2.4 V.
only. It does not define protocol, This allows rejection of common-
interconnect, or connector details mode noise picked up along the
because these details are applica- interconnect of up to ±1 V.
tion specific. The LVDS
Standard’s Working Group chose In addition, hot plugging of LVDS
to define only the electrical char- drivers and receivers is possible
acteristics to ensure that LVDS because the constant current
becomes a multipurpose interface drive eliminates damage poten-
standard. Therefore, each appli- tial. Another feature is the re-
cation that uses LVDS should also ceiver’s failsafe function, which
reference the appropriate proto- prevents output oscillations when
col and interconnect standard. the input pins are floating.

The equivalent circuit structure

of the LVDS physical layer is
shown in figure 1. In the driver, a Power supply tolerance
greater than ±10%
current source limits output to
about 3 mA, and a switch box Tx Rx
steers the current through the
termination resistor. This differ-
ential driver produces odd-mode Current steering driver Differential receiver
transmission: equal and opposite 3 mA
currents flowing in the transmis- Supports ±1
VCommon Mode
sion lines. The current returns
within the wire pair, so the cur-
rent loop area is small, and there- or
fore generates the lowest amount
of EMI (electro-magnetic interfer- Current returns
Single resistor
ence). The current source limits within the pair
termination
(small loop area
any spike current that could for lowest EMI)
occur during transitions. Because
there are no spike currents, data Figure 1. The equivalent circuit structure
rates as high as 1.5 Gb/s are of the LVDS physical layer.
possible without a substantial
increase in power dissipation. In
addition, the constant current
driver output can tolerate trans-
mission lines shorted together,
or to ground, without creating
thermal problems.

2
Multiple Technologies and Supply Voltages

When choosing the signal-level between logic states is only

voltages for drivers and receivers, 300 mV, LVDS can change states The diagram in figure 2 empha-
the standards committee consid- very fast. An LVDS signal also sizes the advantage of a low volt-
ered LVDS implementation in changes voltage levels without a age swing for higher perform-
technologies such as Bipolar, fast slew rate. Slowing the transi- ance. For example, when the sig-
BiCMOS, CMOS, and even GaAs. tion rate decreases the radiated nal level changes 300 mV in
In addition, the working group field strength. Slower transitions 333 ps, the slew rate is only
targeted a wide range of power reduce the problem of reflections 0.9 V/ns, which is less than the
supplies (such as 5 V, 3.3 V, and from transmission-path imped- 1 V/ns benchmark slew rate com-
2.5 V) for implementing LVDS, to ance discontinuities, decreasing monly acceptable for minimizing
ensure that LVDS would be the emissions and crosstalk prob- signal distortion and crosstalk. If
interface of choice for future lems. Low voltage swing reduces you use the old benchmark that
generations of products. power consumption because it the rise and fall times should be
lowers the voltage across the ter- no more than two thirds of the bit
Low-voltage signals have many mination resistors and lowers the width, then signals with 333-ps
advantages, including fast bit overall power dissipation. transitions can operate as high as
rates, lower power, and better 1 Gb/s with plenty of margin.
noise performance. Design engi-
neers have previously used full-
tRISE = tFALL
swing CMOS and LVTTL (low volt- Single Ended
age transistor-transistor logic), VoB 1.35 V
1.2 V
but as bit rates increase, these VoA 1.05 V
solutions become unattractive.
More recently, designers have +300 mV
Differential single
+ 100 mV
turned to reduced-swing tech- Vod = VoA - VoB
- 100 mV
OV Diff.
nologies such as SSTL and GTL -300 mV
to gain speed, save power, and
reduce noise. LVDS increases
Figure 2. The lowered voltage swing
these advantages by lowering maintains high speed without excessive
voltage swings to about 300 mV. slew rate.
To increase noise immunity and
noise margins even further, LVDS
uses differential data transmis-
sion. Differential signals are
immune to common-mode noise,
the primary source of system
noise. Because its voltage change

3
Gigabits at Milliwatts

The simple phrase “Gigabits at

milliwatts!” conveniently DS90C387 DS90C388
describes the benefits of an LVDS LVDS
1 1
RED 1 RED 1
system. These benefits are high- 1
DATA
1
GREEN 1 GREEN 1
speed data throughput, power- BLUE 1 1 1
BLUE 1

DC Balance Encode

Decode & Deskew

Parallel - to - LVDS

LVDS - to - Parallel
miser operation, noise control, RED 2 1 1
RED 2
low cost, and higher integration. GREEN 2 1 1
GREEN 2
BLUE 2 1 5.38 1
BLUE 2
Gbps
LVDS system features, such as
serializing data, encoding the FPLINE FPLINE
clock, and low skew, all work FPFRAME FPFRAME
together for higher performance. DRDY DRDY
Skew is a big problem for sending Control Control
LVDS
parallel data and its clock across FPSHIFT IN PLL PLL FPSHIFT IN
Clock
32.5 to 112 MHz 32.5 to 112 MHz
32.5 to 112 MHz
cables or printed circuit board (170 MHz SPM)
traces. The problem is that the
phase relation of the data and Figure 3. The OpenLDI (Open LVDS Display
clock can be lost due to different Interface) chipset is an example of LVDS’s
travel times through the link. high performance.
However, the ability to serialize
parallel data into a high-speed then deserializes it at the receiv-
signal with embedded clock elimi- An example of LVDS’s high per- er. The chipset supports TTL
nates the skew problem. The formance is the OpenLDI (Open clock rates up to 112 MHz. To do
problem disappears because the LVDS Display Interface) chipset this, each LVDS data channel seri-
clock travels with the data over that supports 24-bit color and alizes 6 TTL lines, plus a DC bal-
the same differential pair of provides throughput of over ance bit, into a single high-speed
wires. The receiver uses clock 5 Gb/s using only 8 data pairs LVDS pair. That pair operates at
and data recovery to extract the and a clock pair (figure 3). The 784 Mb/s with a data throughput
embedded clock, which is phase chipset serializes a 48-bit TTL of 672 Mb/s. The OpenLDI chipset
aligned to the data. interface down to the 8 pairs and can also operate at TTL bit rates
as low as 33 Mb/s.

4
Gigabits at Milliwatts (continued)

Besides giving tremendous

throughput, the chipset reduces
the interconnect width and pro-
vides other system benefits. The
cable and connector are smaller
and lower cost; the cable is more
flexible, and the connector has
fewer pins.

The beautiful eye pattern in

figure 4 is taken at the end of
a 5-meter cable between the
transmitter and receiver of the
OpenLDI chipset. The transmitter
drives a Pseudo Random Bit
Sequence through the cable, and
the receiver recovers the signal.
The markers show the bit width
to be 1.275 ns, indicating a data
rate of 784 Mb/s. Each of the 8 Figure 4. Eye pattern measured at the end
pairs carries this raw data rate, of a 5-meter cable between the transmitter
resulting in an aggregate band- and receiver of the OpenLDI chipset.
width of almost 6.3 Gb/s. This
data rate includes overhead for
DC balance, so the actual payload
bandwidth is 5.38 Gb/s.

5
Flat Supply Current vs. Operating Frequency

A significant advantage of LVDS Another advantage of LVDS is its

technology is the lower power low electromagnetic-interference
requirement. The graph in figure 5 (EMI) generation. The reasons
shows LVDS’s supply current LVDS generates low emissions are
remaining flat as the operating its low voltage swing, slow edge
frequency increases, whereas the rates, the odd-mode differential
supply current for CMOS and signals, and the minimal Icc
GTL (gunning transistor logic) spikes from constant current
technology increases exponential- drivers. High-frequency signal
ly as frequency increases. LVDS transitions flowing through a
benefits because it uses a con- transmission path create electro-
stant-current line driver rather magnetic fields that radiate emis-
than a voltage-mode driver. sions. The field’s strength is pro-
portional to the energy carried by
The load power calculation the signal. By reducing the volt-
(3.3 mA times the 330-mV drop age swing and the current energy,
across the 100-Ω termination LVDS minimizes these fields.
resistor) means LVDS has only However, even the reduced elec-
1.1-mW load power consumption. tromagnetic fields can cause
By comparison, GTL consumes radiation problems.
40 mA of load current through a
1 V drop across the load resistor,
which is a whopping 40-mW load
power dissipation. LVDS also has Icc vs frequency
low power requirements com-
pared to Pseudo ECL (PECL). The TTL/CMOS
Icc (mA)

DS90CO31 is an LVDS pin-com-

patible replacement part for the GTL
Pseudo ECL 41L Quad
Differential Line Driver. The
LVDS part consumes 16 times
less supply current than the
PECL part (3 mA compared to LVDS
50 mA). Furthermore, the low
power consumption inherent in
10 100 MHz
LVDS technology eliminates the
need for either heat sinks or spe-
cial packaging. This benefit also
Figure 5. LVDS’s supply current remains
reduces the system cost of gigabit flat as the operating frequency increases.
data transfers.

6
Low Electromagnetic Interference

Differential signal paths reduce inputs, so when the noise appears

the harmful effects of these fields commonly to both inputs, the
to further minimize these radia- input differential signal ampli-
tion problems. Balanced differen- tude is undisturbed. This com-
tial lines have equal but opposite mon-mode noise rejection also
currents, called odd-mode sig- applies to noise sources such as
nals. When the fields created by power supply variations, sub-
these odd-mode signals are closely strate noise, and ground bounce.
coupled, they tend to tie each
other up and thus cannot escape The LVDS flat panel display
to cause harm. Therefore, it is (FPD) Link standard shown in
important to maintain a balanced figure 6 demonstrates the low
and closely-coupled differential noise-generation characteristics
transmission path to reduce emis- for LVDS while targeting LCD
sion of electromagnetic interfer- applications for notebook and
ence. Differential signals also sub-notebook computers. The
have the advantage of tolerating FPD link moves large amounts of
interference from outside sources display data from the notebook
such as inductive radiation from PC to the display panel. The
electric motors or crosstalk from system designers had to solve the
neighboring transmission lines. problem of twisted-pair cables or
When the differential transmis- flex circuit carrying high-speed
sion lines are closely coupled, the data through the panel hinge
induced signal is common-mode without creating EMI problems.
noise that appears as a common- They chose to use LVDS tech-
mode voltage at the receiver nology because it has better
input. The differential receiver EMI performance than all other
responds only to the difference interface technologies.
between the plus and the minus

1.84 Gbps RGB Row/Column

VGA Tx Rx TCON
LVDS 65 MHz Drivers

Figure 6. The LVDS Flat Panel Display Link

moves large amounts of data from the
notebook PC to the display panel.

7
Cost Benefits

All of the LVDS advantages dis- izers. This saves about 50 percent Integration also benefits from dif-
cussed so far also benefit system of the cabling, connector, and ferential signals. These signals
cost. There are even more system printed circuit board costs when tolerate high levels of switching
cost savings from using LVDS. compared to a parallel intercon- noise, so they can be reliably inte-
The first is LVDS’s ability to nect. The FPD-Link chipset dem- grated with large-scale digital cir-
tolerate minor impedance mis- onstrates this system cost sav- cuits. In addition, LVDS generates
matches in transmission paths. ings. The chipset takes the 18- or very little noise due to the con-
As long as the differential signal 24-bit-wide RGB (Red/Green/Blue) stant-current nature of the output
passes through balanced disconti- bus and the VSYNC, HSYNC, and structures. Therefore, complete
nuities in closely coupled trans- Data Enable control lines and interface Systems-on-a-Chip are
mission paths, the signal can multiplexes them down to only 4 feasible. Digital blocks for inte-
maintain integrity. The effect of or 5 pairs. This low-cost 4- or 5- gration include DC balance, clock
non-impedance-controlled con- pair link passes data through the embedding, clock recovery,
nectors, printed circuit board hinge to the panel where it is encoders and decoders, and
vias, and chip packaging is not demultiplexed. Typical intercon- de-skew blocks. Higher-level
as detrimental to differential nects range from about 8 cm to 40 digital functions such as hard-
signals as it is to single-ended cm in length and use low-cost flex ware protocol assist, management
signals. In addition, it is possible circuit or twisted-pair cabling. and statistics counters, and rout-
to use fewer circuit board layers ing decision logic are also using
because of the relative immunity The final LVDS system benefit is LVDS on-chip as the interface of
to crosstalk that is inherent in its integration capability. Because choice. Further integration of the
differential signals. it is possible to implement high- blocks shown in the FPD-Link
speed LVDS in a standard CMOS chipset (figure 6) is already hap-
LVDS requires only a simple ter- process, integrating complex pening. Obvious candidates for
mination resistor, which can be digital functions with LVDS’s integration are the LVDS trans-
integrated onto the chip. This analog circuits is very beneficial. mitter with the VGA (video
costs much less than using multi- Integrating serializers and deseri- graphics adapter) controller and
ple resistor and capacitor compo- alizers is only the beginning to the LVDS receiver with the timing
nents for each transmission line. mixed-signal LVDS chips. controller.
In addition, LVDS requires no ter-
mination or Vddq voltage supply, a Many Channels per Chip The OpenLDI chipset supports
big cost savings over technologies cable lengths up to 10 meters by
such as GTL, LVTTL, and SSTL. LVDS’s low power consumption integrating special functions.
enables integrating many chan- These functions are transmitter
Because LVDS is capable of han- nels per chip. For example, it is pre-emphasis, DC balance coding,
dling the high-speed data that possible to serialize a 128-bit, and cable deskew. They all work
results from serializing many on-chip parallel bus down to 8 to extend the reach and band-
parallel bits into a single data differential channels. This nar- width of OpenLDI interconnects
stream, LVDS chips commonly rower link dramatically reduces to flat-panel-monitor applications
integrate serializers and deserial- pin count and total link cost. that may require longer cables.

8
DC Balance for Longer Cables

The OpenLDI chipset implements cable charge, thus keeping the The pre-emphasis feature is user
a simple DC balancing scheme disparity between plus 10 and selectable. When pre-emphasis is
that reduces inter-symbol inter- minus 9. The 7th LVDS data bit selected, the transmitter has two
ference (ISI). This demonstrates indicates whether the data in the current drive levels. It delivers
integrating digital functions onto payload is “true” or “inverted”. additional dynamic current dur-
the same chip as the LVDS inter- ing transitions to overcome the
face. Without DC balance, a long This simple DC balance scheme cable’s filtering, and supplies a
cable can result in ISI for a single keeps the signal eye diagram wide lower drive current after the
bit transition and cause a bit open at the receiver end. In addi- transition. It opens the signal eye
error. This happens because a tion, it provides enough DC bal- diagram by overcoming cable
single bit transition, after a long ance to satisfy fiber-optical inter- distortion of the signal.
string of no transitions, may not connect requirements, allowing
contain the energy necessary to the OpenLDI chipset to interface LVDS is now spawning follow-on
change the stored charge through with standard parallel fiber- technologies that expand its
the entire cable. The term “dis- optical products. applications. The first follow-on
parity” describes the stored is Bus LVDS, which allows the
charge on the cable. If the dispar- Another integrated enhancement low-voltage differential signals
ity magnitude is large, then the to the OpenLDI chipset is the to work in bi-directional and
single bit transition cannot over- transmitter pre-emphasis feature. multi-drop configurations.
come the inter-symbol interfer- Without pre-emphasis, the signal Another LVDS derivative, ground
ence at the end of the cable. The coming out of a cable loses the referenced LVDS (GLVDS), is pro-
OpenLDI part provides DC bal- sharp transition edges due to the gressing through the standardiza-
ance on a frame-by-frame basis. cable’s high-frequency filter tion process. GLVDS moves the
During the frame, the transmitter effect. With pre-emphasis, the differential signal’s common-
monitors the input signal for driver accentuates the transitions mode voltage close to ground,
transitions. If no transitions to compensate for the filter effect which allows chips operating
occur, the transmitter inverts the at the end of the cable. from very low supply voltages to
next frame to maintain balanced communicate over a high-speed
standard interface.

9
Bus LVDS

A review of bus topology helps in The second multidrop bus differs drive this bus to a given differen-
understanding the development from the first because it is driven tial voltage level as it would for
of Bus LVDS (BLVDS), the first from the center rather than the the unidirectional bus.
offspring of LVDS. The top two end of the bus. This configuration
buses in figure 7 show multidrop is useful for reducing flight-time The third bus is a multipoint,
configurations. The top configura- variations from the driver to all bidirectional bus because it has
tion is unidirectional because receivers. However, it requires a multiple drivers and receivers
there is a single driver at one end termination resistor at each end (transceivers). This is the most
of the bus. This simple multidrop of the bus to prevent reflections. difficult bus to design for high
bus requires only a single termi- Furthermore, the larger the performance because of the vari-
nation that is on the opposite end capacitive loads and the less able driver positions, which
of the bus from the driver, to stop space between them, the lower cause various reflections that
reflections of the driven signal. the bus’s loaded impedance. depend on where the signal
Each of the attached receivers Because the termination resistors originates in the bus. It also
reduces the loaded bus imped- must match this lower impedance must be terminated on both ends
ance. The loading amount to stop reflections, they can be as to prevent reflections.
depends on the connector, vias, low as 54Ω in a heavily loaded
packaging, and receiver input bus. The two termination resis-
capacitance. If these factors are tors are seen in parallel by the
well designed to keep the loading driver, so the driver must source
small, plain LVDS can drive as much as three times the cur-
this configuration. rent of point-to-point LVDS to

D R
R R R R R R

Multi-drop
R R
R R R R R R
D

T T T T T T T
Multi-point
Figure 7. Multidrop and multipoint bus topologies
are useful in BLVDS applications.

10
The Complexities of Signal Integrity

Signal integrity in a heavily One of the essential features This chipset distributes data over
loaded backplane is a very com- required in a multidrop bus is a serial channel in multidrop dis-
plicated problem due to the many the ability to insert cards into tribution systems. One serializer
impedance discontinuities inher- the bus without powering it down. can drive many deserializers in
ent in the backplane environ- The optimal hot-insertion capa- either of the multidrop configura-
ment. The worst-case situation in bility is to insert cards without tions shown in figure 7. Multi-
bus signaling occurs when a card stopping or disturbing the data point application is also possible
in the middle of the bus drives a traffic on the bus. BLVDS sup- with certain limitations due to
signal into the backplane and the ports this optimal hot-insertion PLL lock time. The limitations
card in the adjacent slot looks to capability, as the signal glitch arise when a new driver begins
receive the signal. The edge rate caused by inserting the capacitive to drive the bus and all the
from the driving card is very fast load of the plug-in card occurs receivers must lock to that dri-
as the signal leaves it and travels equally on each of the differential ver’s clock signal. In addition, the
down the backplane. The adjacent lines that have a low impedance chipset works in point-to-point
cards see the fast edge propagate connection between them. There- applications. The chipset sup-
into the signal stub. This fast edge fore there is no change to the ports TTL clock rates from 16 to
rate causes reflections on the differential signal. 66 MHz. For example, the chipset
stub that can glitch through the transfers a 660-Mb/s payload
receiver threshold region. (The Serializer/Deserializer Example over a 10-meter cable when the
most important factor for high- 10-bit interface operates with a
speed performance in all bus An application example of Bus 66-MHz clock.
topologies is keeping each receiv- LVDS technology is the serializer/
er’s non-terminated stub very deserializer chipset. The trans- The chipset’s waveform has a
short, minimizing reflections mitter serializes a 10-bit parallel 10-bit payload surrounded by
from that stub.) LVTTL interface into a single two embedded clock bits. The
BLVDS data channel, and also actual serial bit rate with a
BLVDS uses the same basic embeds the clock in the serial 40-MHz clock is 480 Mb/s, but
schematic as LVDS, but extends stream. The BLVDS receiver the throughput is 400 Mb/s. The
LVDS’s point-to-point and simple recovers the clock and data to receiver uses the embedded
multidrop applications to true deserialize them back into the clock edges to lock onto the
multipoint busing functionality. 10-bit parallel interface. inbound serial stream and to
It does this by boosting the drive align the data at the parallel out-
current to 10 mA to drive double put. It provides greater system
terminations on heavily loaded benefits than other LVDS parts
buses, and by providing driver by eliminating the cost of a cable
output impedance that matches or PCB differential pair for the
the line impedance to reduce clock signal.
reflections from driver outputs.

11
LVDS in Low-Power Applications

LVDS is also being adapted for The simplified GLVDS schematic these power supplies use ground
very low-power applications, such shown in figure 8 is very similar as a common reference. That
as a remote base station depend- to both LVDS and BLVDS. One of common ground is the common
ing on wind- or sun-generated the few differences is the circuit voltage level where GLVDS signals
power. This is ground-referenced from the middle of the receiver are working.
LVDS (GLVDS), which is a pro- termination to the receiver’s
posed standard interface. The ground. The GLVDS name refers The GLVDS standard does not
JEDEC JC-16 committee for low- to this ground reference for the specify any transmitter drive cur-
voltage interface standards is receiver termination. GLVDS rent. The intention is to leave that
considering the standard. The requires termination to be open to the individual applica-
proposed standard has transmit- on-chip rather than an off-chip tions that use the interface tech-
ter output voltages between 0 V option, as is the case with LVDS nology. This would allow the
and 0.5 V, and receiver input sen- and BLVDS. driver to provide a small current
sitivity of at least 100 mV. The (for example, 1.5 mA to 3 mA) for
very low transmitter output volt- Another important feature of this chip-to-chip applications that
age provides for low power con- technology is the ability for chips have short interconnects. For
sumption by the interface. This with far different power sup- applications that need to drive
lower power consumption is an plies—from 5 V down to 0.5 V—to long cable lengths, the driver
advantage this technology brings communicate with each other. would have to supply a larger
to the LVDS family of standards. This is possible because all of current output (8 mA to 15 mA).

Current steering driver

Differential receiver
0.5V

Support VDD+0.5 to
–1V Common Mode

or

Resistor termination
network referenced
to receiver ground

Figure 8. The simplified GLVDS

schematic shows its similarity
to both LVDS and BLVDS.

12
Test and Evaluation Considerations

There are many considerations Figure 9 shows a block diagram of components (CSC) takes the raw
with testing and evaluating high- the setup for the OpenLDI DUT test data and converts it to an
performance LVDS devices. For interface board. The Agilent 81200 easy-to-understand visual format.
example, the test equipment data generator/analyzer is a
needs the two clock rates that complete test system capable of The data generator/analyzer uses
result from serializing the parallel 1.32-Gb/s testing (although the ports to identify groups of gener-
data into high-speed signals. The system works at a frequency of ator and analyzer signals. In the
test system must be able to gener- up to 2.67 Gb/s). The data OpenLDI deserializer test exam-
ate and analyze the data at both generator/analyzer achieves ple, there are two generator ports
clock frequencies. Testing the 1.32 Gb/s by multiplexing two of and two analyzer ports. The gen-
receiver of the Open LVDS display the 660-Mb/s channels into one erator ports, Port 1 and Port 3,
interface (OpenLDI) chipset can generator or analyzer channel. supply the two frequencies
demonstrate some performance The test fixture uses an OpenLDI required for testing the LVDS
issues. chipset DUT board. The deserializer. The analyzer ports,
characterization software Port 2 and Port 4, sample the data.

81200 Data Generator and Analyzer

Clock Serial Parallel Clock
Out Data Out Data In In
7 Terminals

8 Port 4
8 Port 3
8 333 MHz
DC Balance Encode

Decode & Deskew

Parallel - to - LVDS

LVDS - to - Parallel
8
8
8

Port 1 Port 2
PLL PLL
Clock In Clock Out
LVDS Clock
47.57 MHz DS90C387 DS90C388 47.57 MHz

Figure 9. The test setup for the OpenLDI

DUT interface board.

13
Test and Evaluation Considerations (continued)

For the first set of tests, the data The first analysis that uses the each side of the valid-data win-
generator/analyzer creates the visual display capability of the dow, the BER increases to a
high-frequency serial data at CSC shows the actual recoverable nonzero value. The BER is a con-
333 MHz, which corresponds to bit width of the serial data. stant value for each of the serial
333-Mb/s NRZ (nonreturn to zero) Sweeping the serial data delay bits preceding and following the
data generation. The generator and checking the BER at the par- bit being checked for correctness.
also provides the serializer’s allel Port 4 allow the data bit The values are constant but not at
input clock at 1/7 the serial data width to be displayed. 1 because of the repetitive bit pat-
rate. The serializer then generates tern used in this test. If the bit
the LVDS clock input to the Figure 10 shows the delay vs. pattern had instead been a PRBS
deserializer. The analyzer moni- BER for the first two of the seven pattern, then the BER for each of
tors the clock out from the deseri- parallel bits. The bit width at the other bits would be 0.5, which
alizer and samples the data off of 333 Mb/s is nominally 3 ns, but as means there is an equal, and ran-
the seven parallel data terminals. the BER graph shows, the recov- dom, chance that the bit would be
ered bit is about 2.4 ns wide. On either 1 or 0.

Figure 10. The delay vs. the BER for

the first two of seven parallel bits
shows the recoverable bit is about
2.4 ns wide.

14
BER Eye Diagram

The next analysis tool is the BER signal-integrity information such the bit width decreases as the
eye diagram. The CSC (computer as overshoot, undershoot, and signaling frequency increases.
software component) generates edge jitter. A BER eye diagram The graph on the right shows that
this diagram by sweeping the demonstrates the valid-data win- although the nominal bit width at
sampling delay and the threshold dow for the recovered bits, which 666 Mb/s is 1.5 ns, the valid-data
of the analyzer on Port 4. The ultimately depends on receiver window delivered by the receiver
graph displays the BER as a color sampling performance in addition and deserializer is really about
at each sampling point. The result to signal integrity. 1.1 ns wide.
is an eye pattern with the black
center representing the correctly Figure 11 visually emphasizes the This BER eye diagram is useful in
sampled data. Other colors show useable portion of the serial bit characterizing receiver perform-
the increasing errors as the sam- width that was also shown in fig- ance. It allows examining the eye
ple point moves further away ure 10. The BER eye width for diagram for each individual bit.
from the window (figure 11). Port 4, terminal 1, at 333 Mb/s At the highest performance level,
shows the same 2.4-ns bit width these eye diagrams must show
This eye pattern differs from an as in the serial-port delay vs. limited variation between bits to
oscilloscope eye diagram because BER graph. ensure there is maximum margin
it does not simultaneously show for board and cable skew. This
multiple transitions. An oscillo- The BER eye diagram for the characterization helps system
scope eye diagram displays 666-Mb/s serial data shows how designers to achieve reliable

Figure 11. BER eye diagrams for two data

rates show how the bit width decreases
as the signaling frequency increases.

15
Recovered Clock Jitter

The deserializer’s recovered transition (0.8 V) results in differ- Bus LVDS excels at driving heavily
clock-out jitter can also be exam- ent mean transition times for loaded backplanes such as those
ined with the CSC (computer each of the edges. used in telecommunications sys-
software component). In this tems. It also works well in distrib-
case, the data generator/analyzer The CSC also provides calcula- uting signals from a single driver
creates a histogram using the tions for sigma and 6-sigma to multiple receivers. BLVDS also
BER measurement. It performs analysis of the histogram. The finds applications in driving
these histogram measurements Sigma button displays a measure- bussed cable interconnects of a
on a running device to obtain ment that corresponds to the few meters in length.
accurate jitter measurements. RMS jitter, while the 6-Sigma but-
The CSC uses the deviation of the ton displays a measurement that GLVDS could work in very low-
BER (dBER/dt) to calculate the corresponds to a peak-to-peak power applications such as
jitter. It measures the signal tran- jitter measurement. In figure 12, remote base stations where
sitions by selectively looking at the CSC reports that rms (root power may be locally supplied
the pass-to-fail and the fail-to- mean square) jitter is about and generated by wind or sun.
pass BER transitions. 45.2 ps for both the rising and It could also be useful as a
falling edges of the deserializer chip-to-chip interconnect for
Figure 12 shows the jitter on both clock-out. very short distances. The main
the rising edge and the falling function for GLVDS might be as
edge for the deserializer recov- Some applications are suitable the interconnect technology for
ered clock-out signal. Because the for more than one of the various chips that have power supplies
sampling point for the analyzer LVDS technologies, but there are of 1 V or less. Low-Voltage Dif-
is set at the same point for both others in which only one would ferential Signaling will continue
the high and low transitions excel. Plain old standard LVDS to evolve toward more and more
(1.4 V in this case), the jitter is excels in applications requiring system applications.
symmetrical on the transitions. driving relatively short intercon-
Setting the sampling point at dif- nects, and also where EMI is a
ferent thresholds for the rising critically sensitive issue for
transition (2 V) and falling the interconnect, such as in
display technology.

Figure 12. The deserializer’s recovered

clock-out jitter shows symmetrical jitter
when using the same threshold (1.4 V).

16
ParBERT 81250 Simplifies the Characterization and Testing of LVDS Devices

The advantages of higher speed testing used in telecommunica-

and better noise performance of tions and system area network
LVDS devices must be properly (SAN) ICs, multiple transmitter
characterized before an LVDS and receiver testing in manufac-
device can be properly designed turing, and forward error correc-
into a system. The Agilent tion (FEC) device testing.
Technologies ParBERT 81250 pro-
vides measurement capabilities Manufacturing test engineers
that until now were difficult and responsible for testing multiple
time consuming to perform. The transmitters and receivers
ParBERT 81250 is a modular often find that reducing the
instrument that provides parallel cost-per-test is critical. The
bit error rate testing up 2.66 Gb/s Agilent 81250 ParBERT and
for up to 64 channels. It provides SpectralBER help by providing
chip control signals, divided or scalable VXI platforms that let
multiplied clock signals, 1-Mb/s designers customize the number
to 2.6-Gb/s operation with propri- of channels needed.
etary formats, as well as low volt-
age differential signaling (LVDS) For designers who need to test
load generation or analysis. You SAN-related multiplexers or
can test SAN-related multiplexers demultiplexers, including Gigabit
and demultiplexers, including Ethernet, flat panel display link,
gigabit Ethernet, flat panel dis- Fibre Channel, and InfiniBand,
play links, Fibre Channel, and the combination of the 81250
InfiniBand. ParBERT 81250 is ParBERT, 86130A BitAlyzer and
especially suitable for multiplexer the 86100A Infiniium DCA helps
and demultiplexer (MUX/DeMUX), solve physical high-speed
or SERDES (serializer/deseralizer) design problems.

Figure 13. The Agilent ParBERT 81250

parallel bit error rate tester

17
81200 Provides the Tools to Test LVDS

Testing and evaluating LVDS- Powerful sequencing capabilities

based components and systems is and full control of pulse parame-
a challenge. Not only are the data ters for each individual channel
rates very high and the signals mean that you can really stress
differential, but the types of tests your device under test (DUT).
required are often complex and The system generates pseudo
time consuming to perform. The random word sequences (PRWS)
Agilent 81200 provides an easier and pseudo random binary sig-
way to evaluate a design or per- nals (PRBS) up to 215-1. Analysis
form manufacturing tests. It pro- is in real time, saving you time
vides a number of visual presen- because no post-processing
tations that allow you to quickly is necessary.
analyze measured data and evalu-
ate the outcome of tests. If you work on telecommunica-
tions multiplexers and demulti-
The Agilent 81200 data generator/ plexers (MUX/DeMUX), SERDES
analyzer platform is a flexible (serializer/deseralizer), or trans-
real-time stimulus and response mitters and receivers, you can
system that now works at up to take advantage of the thorough
2.67 Gbit/s for up to 64 channels. parallel BER measurements of
It provides chip control signals, the ParBERT 81250 system. For
divided or multiplied clock compliance testing, it generates
signals, 1-Mb/s to 2.67-Gb/s PRWS and PRBS up to 231-1,
operation with proprietary for- and also has sophisticated syn-
mats, as well as LVDS load chronization features.
generation or analysis.

Figure 14. The Agilent 81200 data

generator/analyzer

18
Related Literature

Publication Title Publication Type Publication Number

Need to Test BER? Complete Solutions for Color brochure 5968-9250E

High Speed Digital Transmission Testing

Agilent ParBERT 81250 43G Parallel Product overview 5988-3020EN

Bit Error Ratio Tester

Agilent 81200 Color brochure 5980-0488E

Data Generator/Analyzer Platform

Test Tools for InfiniBand Color brochure 5988-2424EN

19
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