Analog Integrated Circuits and Signal Processing, 22, 231±243 (2000)

# 2000 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.

``Square Root Domain'' Filter Design and Performance

MURAT ESKIYERLI2 AND ALISON PAYNE1

1
Department of Electrical and Electronic Engineering, Imperial College of Science, Technology and Medicine, Exhibition Road, London, SW7 2BT, UK
2
Sony Semiconductor of America, Mixed Signal Division, 33000, Zanker Road, San Jose, CA 95134, USA

Accepted 31 August, 1998

Abstract. This paper discusses the implementation and performance of square root domain ®lters, which can be
considered as the CMOS equivalent of the bipolar log domain technique. The square root design methodology is
based on exploiting the MOSFET large-signal square law characteristic to implement ®lters which are input-output
linear, but operate with internally non-linear signals. The design of subcircuits required for the implementation of
square root domain ®lters is described based on the MOSFET translinear principle, and various performance issues
are discussed. Simulation and measured results are also presented to con®rm the validity of this approach, which
may be attractive for low-voltage operation at frequencies in the MHz range.

Key Words: analog integrated circuits, analog ®lters, CMOS translinear circuits

1. Introduction in CMOS technology known as ``MOSFET-C'' ®lters

was ®rst reported in 1983 by Banu and Tsividis [1].
The integration of analog and digital circuits on a These ®lters were derived from classical RC-active
silicon chip is constrained by the fact that most of the ®lters, where a MOSFET in the linear region of
area is occupied by the digital circuitry, and operation is employed as a tuneable linear resistance.
consequently the fabrication technology is optimized The inherent non-linearities of the MOSFET resistors
for digital processing. Since digital circuits are are cancelled by symmetrical circuit design [2].
fabricated almost exclusively in CMOS VLSI, the Tuneability is limited by the fact that the MOSFET
development of analog interface circuit design resistors should operate in the linear region, while the
methodologies which are compatible with this operating frequency range is limited by the need for
technology is a topic currently attracting a great deal opamps. Another important class of integrated
of interest. continuous-time active ®lters are transconductor-C
Continuous-time ®lters are an important part of the (gm-C) ®lters. These ®lters can inherently operate at
interface circuitry between analog and digital parts of high frequencies due to their open-loop topology [3].
a system, for anti-aliasing ®lters for A/D and D/A However, there generally is a trade-off between
converters, etc. The design of fully-integrated speed, linearity and power consumption, and many
continuous-time ®lters presents various design con- different transconductor designs have been reported
straints; a lack of high-Q integrated inductors with emphasis on one or more characteristics such as
necessitates the use of active elements, and variations linearity, high operating frequency, supply voltage,
in absolute component values (tolerances typically slew rate and tuneability [4,5].
between 10±50%) means that the ®lter design Recently a new class of integrated continuous time
parameters must generally be tuneable. ®lters have emerged in bipolar technology, known as
A class of integrated continuous-time active ®lters ``log-domain'' or ``dynamic translinear'' ®lters. These
circuits exploit the inherently non-linear exponential
Alison Payne is with the Department of Electrical Engineering, characteristic of bipolar transistors to implement
Imperial College of Science, Technology and Medicine, Exhibition
Road, London SW7 2BT, UK.
circuits which are input-output linear, although
Murat Eskiyerli is with Sony Semiconductor of America, 33000 internal signals are highly non-linear. Frey initially
Zanker Road, San Jose, CA 95134, USA. proposed a state-space design approach [6], whereby a

125
232 M. Eskiyerli and A. Payne

set of linear state equations are transformed to a 2. CMOS Square Law Synthesis
nonlinear (exponential) form. The resulting non-linear
state equations are then directly implemented as the The idea of exploiting the MOSFET square law
summation of bipolar transistor currents at internal characteristic to implement a required transfer
nodes. Perry and Roberts introduced a technique function is not new, but until recently only real-time
enabling the signal ¯ow-graph synthesis of log- static circuit functions had been reported. A simple
domain LC ladder ®lters [7], and a method of log- example is the linear transconductor shown in Fig. 1,
domain ®lter synthesis based on the transformation of proposed by Bult and Wallingra [14]. Assuming that
conventional gm-C ®lter architectures has also been the devices are in saturation, the square law relation-
described [8]. Following an alternative transistor-level ship between drain current Id and gate-source voltage
approach, the low-level synthesis of log-domain ®lters Vgs is assumed as:
has also recently been proposed [9]. For each of these
methods, the resulting circuits generally exhibit the Id ˆ b…Vgs ÿ Vth †2 …1†
following features:
* Large-signal device equations are used in the Vth and b represent the threshold voltage and
circuit synthesis, therefore circuit operation is not transconductance parameter respectively. If the
limited to small-signal levels. devices are matched (equal b and Vth ), the resulting
* The circuits are current-mode which offers poten- output current:
tially high speed properties (due to low impedance I1 ÿ I2 ˆ b…V2 ÿ 2Vth †…V2 ÿ 2Vin † …2†
levels) and lower supply voltages [10].
* The circuits are easily tuneable through the thus for constant V2 , the output current is a linear
variation of bias currents. function of Vin .
Micropower log domain circuits have also been More complex linear transconductor designs have
implemented based on the exponential relationship been reported based on the exploitation of the square
between gate-source voltage and drain current in a law, which offer wider dynamic range, differential
subthreshold MOSFET. However, the operating operation etc. [15,16]. Non linear circuit functions
frequency of subthreshold circuits is generally limited such as squarers and multipliers have also been
to the kHz range, which restricts their operation to proposed based on this methodology, e.g. [14,15,17±
very speci®c applications, e.g. biomedical sensors 19].
[11]. Following a slightly different approach, Seevinck
The attractive features of log-domain circuits, and Wiegerink proposed a CMOS square law version
combined with the desire to implement analogue
®lters in CMOS VLSI technology, has led to the
proposal of ``square-root domain synthesis'' as a new
CMOS ®lter design methodology [12,13]. The
proposed methodology uses MOSFET devices in
the strong inversion region of operation, and thus is
based on the quadratic relationship between gate-to-
source voltage and drain current. This paper outlines
the general concept and discusses various square root
domain synthesis and performance issues. The paper
is organized as follows: in Section 2, MOSFET
square law synthesis techniques are reviewed and the
generalized translinear principle is introduced; in
Section 3, the state-space synthesis of square root
domain ®lters is described; Section 4 discusses
implementation issues and the validity of the
square law approximation; Section 5 presents
measured results and conclusions are given in Fig. 1. Linear transconductor based on the MOSFET square law
Section 6. characteristic.

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 ``Square Root Domain'' Filter Design and Performance 233

of the well-known bipolar translinear (BTL) principle roots of the drain currents divided by the trans-
[20], which they termed the MOS translinear (MTL) conductance parameters in the CCW direction.
principle [21]. The MTL principle is a generalized Although this expression is not as elegant as the
synthesis methodology for the implementation of BTL principle, the MTL principle can still be
linear and non-linear circuit functions. An MTL loop exploited to implement various non-linear circuit
contains an equal number of MOSFET gate-to-source functions which will prove useful in the implementa-
voltages arranged clockwise (CW) and counterclock- tion of square root domain ®lters. An interesting
wise (CCW), thus the loop contains an even number feature of both BTL and MTL circuits is that input
of devices. If the loop contains both NMOS and signals are applied as currents, and voltage swings
PMOS devices, there must be an equal number of CW within the circuit are of secondary interest. These
and CCW NMOS devices and an equal number of CW ``internal'' voltage swings are additionally fairly
and CCW PMOS devices. An example of a NMOS small (changes in Vbe or Vgs ), leading to the potential
MTL loop is shown in Fig. 2; summing the voltages for high frequency operation at low power supply
around this loop and substituting the square law voltages.
characteristic given in (1) gives the result:
s s s s
Id1 Id3 Id2 Id4
‡ ˆ ‡ …3† 3. Square Root Domain Filter Synthesis
b1 b3 b2 b4
The concept of square-root domain ®lter synthesis has
For a general MTL loop containing N NMOS devices
emerged as the square law equivalent of the
in each direction and P PMOS devices in each
exponential log-domain methodology. The general
direction (thus total number of devices ˆ 2…N ‡ P††,
principle of square-root domain synthesis was
the MTL principle is derived as:
discussed in [12], but Mulder et al. were the ®rst to
s s! s s!
j ˆX
N;k ˆ P
Idj Idk
j ˆX
N;k ˆ P
Idj Idk report a true square-root domain ®lter implementation
‡ ˆ ‡ in [13].
j;k ˆ 1
bj bk j;k ˆ 1
bj bk
CW CCW The design of a simple square-root domain circuit
…4† will be illustrated here by following a state-space
mapping process, similar to the original log-domain
where Idj , bj represent the drain current and
methodology proposed by Frey [6]. Low-level
transconductance parameter of the j th N-channel
integrator-based ®lter synthesis or LC-ladder synth-
device respectively, while Idk , bk relate to the kth
esis methods proposed for log-domain ®lters can
P-channel device. Thus, the MTL principle can be
similarly be adapted for square root domain ®lters
stated as:
[24], and will not be discussed here. The aim of this
The sum of the square roots of the drain currents
paper is to present the general principle, and to discuss
divided by the transconductance parameters in the
various issues which currently limit the performance
CW direction is equal to the sum of the square
of square root domain circuit implementations.
A second order ®lter can be described by the state
equations:
oo
x_1 ˆ ÿ x ÿ o o x 2 ‡ o o u1
Q 1
x_2 ˆ oo x1 ÿ oo u2
y ˆ x1 …5†

where u1 and u2 are input signals, y is the output, x1

and x2 are state variables, and a dot denotes time
differentiation. oo and Q represent the natural
frequency and quality factor of the ®lter. In a typical
Fig. 2. A four-transistor NMOS translinear loop. implementation one of the inputs is held constant,

127
234 M. Eskiyerli and A. Payne

while the other is used as the signal input. For varying Io and Ioq respectively (the reason for the
example, if u2 is held constant and the input is applied doubling of the current sources, i.e. 2Io in Fig. 3, will
at u1 , the resulting bandpass transfer function can be become clear when the full ®lter implementation is
derived: described). The implementation of a square root
domain ®lter thus requires the design of non-linear
Y…s† oo s
H1 …s† ˆ ˆ …6† circuit building blocks, in contrast to conventional IC
U1 …s† s2 ‡ …oo =Q†s ‡ oo 2 ®lter design which is based on the implementation of
Alternatively if u1 is held constant and the input signal linear circuit elements such as transconductors. If
is applied to u2 , a lowpass transfer function can be these non-linear blocks can be designed with good
derived: conformity to the required non-linear function over a
wide input dynamic range, then square root domain
Y…s† o2o ®lters may present an attractive alternative to
H2 …s† ˆ ˆ 2 …7†
U2 …s† s ‡ …oo =Q†s ‡ o2o conventional CMOS ®lter techniques for certain
applications.
Consider a quadratic mapping on the state variables,
such that:
2
x1 ˆ I1 ˆ b1 …V1 ÿ Vth † 4. Non-Linear Subcircuit Implementation and
2 Performance
x2 ˆ I2 ˆ b2 …V2 ÿ Vth † …8†
Substituting these variables into the linear state Equations (10) (and Fig. 3) show that, to implement
equations (5), and multiplying by constants C1 and C2 : the square root domain biquad, two separate non-
 linear functions are required. The ®rst is a geometric
p C o
2C1 b1 I1 V_1 ˆ ÿ 1 o I1 ÿ C1 oo I2 ‡ C1 oo Iin1 mean function:
Q q
 p Iout ˆ Ix Iy =4 …11†
2C2 b2 I2 V_2 ˆ C2 oo I1 ÿ C2 oo Iin2 …9†
The second function has the form:
where the input signals u1 and u2 are replaced by s
currents Iin1 and Iin2 respectively, since the state Ix Iy2
variables have been transformed to current variables. Iout ˆ …12†
4Iz
Assuming that C1 ˆ C2 ˆ C and b1 ˆ b2 ˆ b for
simplicity, and de®ning tuning currents This second function can be implemented by two
2
Io ˆ …oo C† =b and Ioq ˆ Io =Q2 : subcircuits: a current squarer/divider to implement the
s s function Iw ˆ …Iy 2 =Iz †, followed by a geometric mean
1 q 1 I 2
1 I 2
CV_ 1 ˆ ÿ I1 Ioq ÿ Io 2
‡ Io in1 circuit to implement Iout ˆ H…Ix Iw =4†. The required
2 2 I1 2 I1 non-linear functions (geometric mean and current
s s squarer/divider) can be synthesized using the MTL
1 I 2 1 I2 principle, and form the basic building blocks for
CV_ 2 ˆ Io ÿ1
Io in2 …10†
2 I2 2 I2 higher order square root domain ®lter synthesis [24].

The left hand sides of (10) represent currents ¯owing

into capacitors of value C connected with voltages V1
4.1. Geometric Mean Circuit
or V2 across them. The right hand sides of (10) are
clearly non-linear, requiring current squaring/dividing
Consider a four transistor NMOS MTL loop, with M1 ,
and current square-rooting circuits. A high-level
M2 in a CCW direction and M3 , M4 in a CW direction.
block diagram implementation of the square root
Assuming all devices are matched we can write:
domain biquad ®lter is shown in Fig. 3; summing
currents at nodes V1 and V2 derives the expressions p p p p
Id1 ‡ Id2 ˆ Id3 ‡ Id4 …13†
given in (10). The ®lter cut-off frequency oo and
quality factor Q can be independently tuned by De®ne Id1 ˆ Ix and Id2 ˆ Iy as the input currents. If

128
 ``Square Root Domain'' Filter Design and Performance 235

Fig. 3. A block diagram implementation of a square root domain biquad ®lter.

we ensure that Id3 ˆ Id4 , and de®ne an output current

Iout ˆ Id4 ÿ …Ix ‡ Iy †=4, then:
p p2
p
Ix ‡ Iy Ix ‡ Iy Ix Iy
Iout ˆ ÿ ˆ
4 4 2
…14†
The required geometric mean function can thus be
implemented by the MTL circuit proposed in [21] and
shown in Fig. 4. This is a current-sinking geometric
mean circuit; a current-sourcing version could be
implemented by using PMOS rather than NMOS
devices, or by using an additional inverting current
mirror. This circuit is known as a ``stacked'' MTL
topology (since M2 and M3 are stacked above M1 and
M4 ). Fig. 5(a) shows simulation results (solid lines)
using Spectre level 15 models from Austria Micro
Systems (AMS) 0.8 mm CMOS process, with Ix ®xed Fig. 4. Geometric mean circuitÐa ``stacked MTL'' implementa-
at the values shown and Iy varying. All MOSFETs tion.

129
236 M. Eskiyerli and A. Payne

(b)
(a)

Fig. 5. Comparison of ideal and simulated results for the ``stacked MTL'' geometric mean with (a) body effect included and (b) no body
effect.

have an aspect ratio of 12 mm/0.8 mm. The ideal when using an up-down topology rather than a stacked
geometric mean characteristics are also shown in loop.
dashed lines. The considerable deviation (up to 20%
at low current levels) between the ideal and simulated
characteristics is due to the body effect …Vbs 6ˆ 0† 4.2. Current Squarer/Divider Circuit
causing threshold voltage mismatch, since this is an
N-well process and thus all NMOS devices share the Bult and Wallinga proposed a current squarer/divider
same substrate. On a P-well process it would be circuit in [14], but since this implementation is based
possible to place each device in a separate well, on a stacked loop topology the accuracy is
connecting each source to the well to avoid the body insuf®cient for our purposes. An up-down loop
effect. The simulation results in this case are shown in topology which eliminates the body effect was
Fig. 5(b), and demonstrate a good conformity with the proposed in [21] and is shown in Fig. 6 (this is a
ideal characteristics over a wide range of input current sourcing circuit; a current sinking version
currents, with minimum gate length devices.
However the disadvantage of placing each transistor
in an individual well is the increase in silicon area, and
a reduction in bandwidth due to the large well-
substrate capacitance of each individual well.
A better solution is to use an ``up-down'' loop
topology such as the example shown in Fig. 2. In this
case all devices will have approximately the same
source voltage and the body effect is minimized; to
further reduce the effect of threshold voltage
mismatch, the magnitude of Vbs should be made as
large as possible. Simulations show that the resulting
circuit has good accuracy and wide bandwidth, thus
this topology was chosen in all following architec-
tures. However the complexity of the circuit required
to provide the correct input currents may be increased Fig. 6. Current squarer/dividerÐan ``up-down MTL'' topology.

130
 ``Square Root Domain'' Filter Design and Performance 237

could be implemented by using NMOS rather than

PMOS devices). When all transistors are matched
(equal values of b ), the MTL expression for the loop
can be written as:
p p p p
Id1 ‡ Id2 ˆ Id3 ‡ Id4 …15†

Transistors M5 and M6 form a current mirror which

ensures Ix ˆ Id4 ÿ Id3 . De®ning an output current
Iout ˆ Id3 ‡ Id4 ÿ 2Iy , gives the result:

Ix2
Iout ˆ …16†
8Iy

This expression is valid as long as Id3 and Id4 are

greater than zero, i.e.: (a)

ÿ 4Iy 5 Ix 5 4Iy …17†

Fig. 7 shows simulation results for the current

squarer/divider circuit using AMS 0.8 mm CMOS
technology. All p-channel MOSFETs were imple-
mented with aspect ratio 12.8 mm/0.8 mm, and
regulated cascode current sources were implemented
to drive the circuit. The circuit was simulated to
evaluate both the current squaring and current
dividing behavior. Fig. 7(a) shows the simulation
results (solid lines) for the current squaring action,
with the dividing current Iy held constant at the
values shown and input current Ix varying. The ideal
characteristics are also shown as dashed lines. The
quadratic relationship is clear for input currents in
the range given by equation (17); outside of this (b)
range the output current increases linearly with the
input current. The device dimensions were optimized Fig. 7. Comparison of ideal ans imulated results for the current
for input currents around 200 mA. Fig. 7(b) shows the squarer/divider circuit demonstrating (a) the current squaring
action and (b) current dividing action.
simulation results (solid lines) for the circuit dividing
action, with the squaring input current Ix held
constant at the values shown and the dividing current
Iy varying. Ideal characteristics are again shown as 4.3. Sub-Circuit Performance Limitations
dashed lines. The curves are bounded at the lower
end of the range by equation (17). At the upper end, Errors in the sub-circuit performance due to the body
the simulated characteristics are increasingly in error effect have already been mentioned, and can be
due to mobility reduction effects at higher current minimized by selecting an up-down loop topology.
levels (discussed below). Because the output current Other second order effects which are likely to affect
is the difference of two large currents, the relative circuit performance include mobility reduction,
errors increase at higher current levels. The small- channel-length modulation, and threshold voltage
signal bandwidth of the circuit was simulated to be mismatches. These issues will be discussed brie¯y
more than 300 MHz; this ®gure was also con®rmed below in relation to the current squarer/divider circuit
by large-signal transient simulation. of Fig. 6, but similar comments will apply to the

131
238 M. Eskiyerli and A. Payne
 q 2
geometric mean circuit (and indeed, to other similar 1 ‡ 32 y Iy =bIx
MTL circuit structures). Iout ˆ  q2
8 1 ‡ y Iy =b Iy
 q p
Mobility Reduction. As the transverse electric ®eld 1 ‡ 32 y Iy =b y Iy=bIx 4
along the channel …Ex † increases in magnitude, the ‡  q2
mobility of carriers in the channel decreases. There 128 1 ‡ y Iy =b Iy 3
are several models of mobility versus electric ®eld;
one particular relation which is commonly used is y2 I x 6
‡  q2 …22†
[23]: 8192b 1 ‡ y Iy =b Iy 4
meff
mˆ  2 1=2 …18†
The output will contain fourth and sixth order terms in
meff Ex
1‡ sat Ix , as well as third and fourth order terms in Iy . The
fundamental of the output (i.e. Ix 2 =8Iy term) will also
where meff is the effective carrier mobility for small be modulated by a weak function of Iy .
transverse ®elds, sat is the saturation velocity and Ex By simple curve ®tting to the simulated character-
is the electric ®eld strength along the channel. istics, the mobility reduction parameter is found to be
Assuming that the device is in saturation, the about 0.07 for the AMS 0.8 mm CMOS technology.
transverse ®eld strength Ex will be proportional to With this value of y, simulations show that the error in
…Vgs ÿ Vth †. For an approximate analysis it is often the fundamental term is relatively unaffected by
suf®cient to simplify equation (18) to a ®rst order changes in Iy , shifting from 2.5% to 2.8% above the
expression [22]: ideal value when Iy is varied between 1 and 100 mA.
For a practical range of input currents, the deviation
meff from the ideal response due to fourth order compo-
mˆ …19†
1 ‡ y…Vgs ÿ Vth † nents of Ix is found to be less than ÿ 40 dB. The sixth
order deviation is less than ÿ 80 dB, and is unlikely to
where y is a mobility reduction parameter. Referring be of any great signi®cance.
to Fig. 6, writing the MTL equation for the loop:
s
q 1 ‡ y…Vgs3 ÿ Vth †p Channel Length Modulation. The variation of
4Iy ˆ I channel length with changes in Vds is generally
1 ‡ y…Vgsy ÿ Vth † d3
s modeled by the equation:
1 ‡ y…Vgs4 ÿ Vth †p
‡ I …20† Id ˆ b…Vgs ÿ Vth †2 …1 ‡ lVds † …23†
1 ‡ y…Vgsy ÿ Vth † d4

where Vgsy is the gate-source voltage of transistors where l is the channel length modulation parameter.
with a drain current Iy . In Fig. 6, the diode-connected devices M1 and M2
Substituting Vgs ÿ Vth ˆ H…Id =b†, equation (20) is have Vds ˆ Vgs , thus channel length modulation will
thus rewritten as: be minimal. Considering the effect of devices M3 and
M4 , the output current can be recalculated as:
p p
1 ‡ y Id3 =b 1 ‡ y Id4 =b  2
q Id3 ‡ q Id4 Id3 Id4
ÿ 1‡lV
1 ‡ y Iy =b 1 ‡ y Iy =b Iout ˆ
1‡lVds3 ds4
…24†
 p p 2 8Iy
1 ‡ y Id4 =b
p Id4 ÿ 1 ‡ y pI
d3 =b
I
1 ‡ y Iy =b 1 ‡ y Iy =b d3 assuming that the sum Id3 ‡ Id4 is largely unaffected
ˆ 2Iy ‡ …21† by channel length modulation effects. With typical
8Iy
operating voltages, the simulated deviation from the
Assuming that the left hand side of equation (21) is ideal characteristic due to channel length modulation
relatively constant, and de®ning Iout ˆ Id3 ‡ Id4 ÿ 2Iy is small (less than ÿ 80 dB for most of the operating
as previously, gives the result: range).

132
 ``Square Root Domain'' Filter Design and Performance 239

Threshold Voltage Mismatch. Assuming that the channel to saturate. This velocity saturation has
devices M5 ÿ M8 are matched, any mismatch in the two main effects:
threshold voltages of M1 ÿ M4 will cause an offset in * The drain current is scaled by a factor
ÿ1
the MTL loop equation as follows: …1 ‡ Vds =…1 ‡ LEc †† (i.e. reduced), where Ec is
s s s the critical transverse ®eld strength.
4Iy X 4
Id3 Id4 * At very short gate lengths it will destroy the square
‡ DVthi ˆ ‡ …25†
b iˆ1
b b law relationship, and leads to a linear dependence
between drain current and gate-source voltage.
where A minimum gate length which largely avoids short
X
4 channel effects due to mobility reduction and velocity
DVthi ˆ DVth1 ‡ DVth2 ÿ DVth3 ÿ DVth4 …26† saturation can be determined by referring to equation
iˆ1 (19). To ensure that mobility stays approximately
Threshold voltage mismatches are represented by a constant with changes in transverse electric ®eld, we
deviation from a mean value Vtho , i.e. Vth ˆ Vtho ‡ require:
DVthi . The effect of threshold voltage mismatches on meff Ex
the circuit of Fig. 6 can be calculated as: 51 …28†
sat
!
Ix2 Ix2 X4
Assuming Ex ˆ …Vgs ÿ Vth †=L, a minimum gate
Iout ˆ ÿ DV
8Iy 8Iy3=2 iˆ1 thi length can be approximated as:
!
X 4
meff …Vgs ÿ Vth †
3=2
‡ 2Iy DVthi …27† Lmin 4 …29†
iˆ1
sat

The threshold voltage mismatch will not cause any With typical values sat ˆ 107 cm/s and meff ˆ
deviation proportional to Ix , but will create new terms 500 cm2 =s we obtain the result:
3=2
proportional to Iy ÿ3=2 and Iy . These ``fractional …Vgs ÿ Vth †
harmonics'' are a result of the non-linear signal Lmin 4 mm …30†
2
processing within square root domain ®lters, and are
not generally encountered in conventional linear This minimum gate length will ultimately limit the
®lters. maximum operating frequency of square-root domain
®lters.
MOSFET Square Law Deviation. At this point it is
instructive to examine whether the MOSFET square
law approximation is a valid one. In the relevant 5. Filter Implementation
literature it has been shown that, for long channel
MOSFETS, the square law approximation agrees with 5.1. Implementation
experimental results to a great extent [22,23].
However these assumptions may no longer apply to Returning to the biquad ®lter circuit of Fig. 3, we are
modern technologies which have increasingly smaller now able to implement a full transistor level circuit by
geometries, driven by power consumption, speed and replacing the high-level non-linear blocks with the
silicon area considerations. geometric mean and current-squarer divider circuits
A reduction in the gate length increases the shown in Sections 4.1 and 4.2. The blocks with current-
importance of second-order ``short channel'' effects sourcing outputs are implemented by PMOS MTL
in the MOSFET characteristic, such as channel length circuits, while blocks with current-sinking outputs are
modulation, mobility reduction, and velocity satura- implemented by NMOS MTL circuits. Aspect ratios of
tion. Channel length modulation and mobility MOSFETs M1-M8 in Fig. 3 are equal to 16 mm/1.2 mm.
reduction have been brie¯y discussed above. For The bias currents Io are used to tune the ®lter cutoff
shorter channel lengths, the increasing transverse frequency oo, while the quality factor Q is set by bias
electric ®eld in the channel further modulates the current Ioq ˆ Io =Q2 . Referring to equation (10), terms
carrier mobility causing the velocity of the carriers in of the form H…Io Ix2 =Iy † ˆ H…Io Iw † need to be

133
240 M. Eskiyerli and A. Payne

generated. The output from the current squarer/divider deviation from the ideal response was seen in the
circuit is Ix2 =8Iy , and so needs to be multiplied by eight bandpass case, in that the low frequency attenuation
before processing by the geometric mean circuit. In was severely degraded. To develop insight into the
practice a current mirror of 1:4 ratio is used to multiply source of the ®lter non-idealities, the state equations
this current by four, while the tuning current term Io is of the ®lter were re-derived from the block diagram of
multiplied by two, to achieve the same net effect. This Fig. 3, this time including two additional resistors R1
has the further advantage of ensuring that the input and R2 connected in parallel with the integrating
currents to the geometric mean circuit are of similar capacitors at nodes V1 and V2 respectively. R1 and R2
magnitude, thus reducing the output error (see Fig. represent the total output impedance of the geometric
5(a)). In addition, the DC levels of the input currents mean and current squarer/divider circuits at these
are scaled so that Iu1 ˆ …1 ‡ 1=Q†Iu2 to ensure a stable nodes; in practice, these values will be dynamic (large
equilibrium condition at DC [6]. signal resistances). Considering the non-linear geo-
The level of distortion at the output is related to the metric mean and current squarer/divider sub-blocks to
magnitude of the voltage swings across the capacitors. have ideal responses, the state equations are modi®ed
The minimum and maximum capacitor voltages are by the presence of R1 and R2 :
restricted by the strong inversion condition and the p
mobility degradation respectively. Thus the gate- p bI1 Coo
2C bI1 V_ 1 ‡ 2 V ˆÿ I ÿ Coo I2 ‡ Coo Iin1
source voltage of transistors connected to the capacitor R1 1 Q 1
nodes (M1 ÿ M8 in Fig. 3) must be limited to between p
p bI2
approximately …Vth ‡ 0:1 V† and …Vth ‡ 0:6 V† for this _
2C bI2 V2 ‡ 2 V ˆ Coo I1 ÿ Coo Iin2 …31†
technology to prevent excessive output distortion. R2 2
Although this factor may seem to limit the usefulness Applying the mappings for I1 and I2 as given in
of square-root domain circuits, it must be remembered equation (8), these state equations are modi®ed to:
that capacitor voltages are a compressed (square-
   p
rooted) version of the circuit currents, and excessive o 2 p 2VT b
output distortion does not arise until the input current I_1 ˆ ÿ o ‡ I1 ÿ oo I2 ‡ oo Iin1 ÿ I1
Q CR1 CR1
modulation is higher than about 80%.    p
2 p 2VT b
I_2 ˆ I1 oo ÿ I2 ÿ oo Iin2 ÿ I2 …32†
CR2 CR2
5.2. Performance Analysis
These state equations are no longer linear, but contain
terms of the form HI 1 and HI 2 . If for the moment we
The circuit was simulated using device parameters
assume that these non-linear terms are very small and
from the AMS 0.8 mm CMOS process; large signal
can be neglected, equation (32) can be rewritten as:
transient simulations were performed at a range of
frequencies to con®rm the response obtained from AC  
(small-signal) analysis. Applying a signal at Iin2 gave _I1 ˆ ÿI1 oo ‡ 2 ÿ I2 oo ‡ Iin1 oo
Q CR1
a lowpass response much as expected, although oo
 
and Q were shifted slightly from the ideal design _I2 ˆ I1 oo ÿ I2 2
values calculated using the expressions derived in ÿ oo Iin2 …33†
CR2
Section 3. With C ˆ 20 pF, Io ˆ 120 mA and
Ioq ˆ 100 mA the ideal calculated values for fo and Combining these two linear state equations and gives
Q were 3.75 MHz and 1.1 respectively, while the the resulting response:
values obtained from simulation were 3.9 MHz and
0.9. Similarly with Io ˆ 180 mA and Ioq ˆ 150 mA the Iout …s†
ideal values of fo and Q were calculated as 4.59 MHz ˆ I1 …s†
and 1.1 respectively, while the values obtained from oo Iin1 …s ‡ 2=CR2 † ‡ oo Iin2
ˆ
simulation were 4.77 MHz and 0.9. s2 ‡ …oo =Q ‡ 2=CR1 ‡ 2=CR2 †s ‡ …o2o ‡ 4=C2 R1 R2 †
The bandpass response obtained by applying an …34†
input signal at Iin1 showed a similar shift in the
simulated values of fo and Q. However a more serious Compared to the ideal response (equations (6) and

134
 ``Square Root Domain'' Filter Design and Performance 241

(10)), the cut-off frequency and quality factor are both 5.3. Measured Results
modi®ed:
p The biquad ®lter circuit of Fig. 3 was implemented
o0oˆ oo …1 ‡ 4=C2 R1 R2 o2o † using AMS 0.8 mm CMOS technology, and a chip
p photograph is shown in Fig. 9. The circuit was
0 …1 ‡ 4=C2 R1 R2 o2o † powered from a 5 V power-supply, and CCII-01
Qo ˆ Qo …35†
1 ‡ …2Qo …R1 ‡ R2 †=oo CR1 R2 † current-conveyor ampli®ers1 were used as high-
frequency transconductors to convert input signal
In addition, the bandpass zero is shifted up in voltages to currents required at the input of the test
frequency from zero to oz ˆ 2=CR2 . circuit. Output currents were measured using a
This approximate linearized analysis predicts that Tektronix CT-2 current probe having a ÿ 3 dB
the ®nite output impedance of the non-linear sub bandwidth of 1 GHz. Fig. 10 compares the measured
circuits will cause a shift in the expected transfer (solid lines) and simulated (dashed lines) bandpass
function. This effect is further illustrated in Fig. 8, frequency responses for two different values of tuning
which shows simulation results for the bandpass currents. In the ®rst case (1), Io ˆ 120 mA and
response in which behavioral models were used to Ioq ˆ 100 mA (i.e. fo ˆ 1:9 MHz and Q ˆ 1:1). The
represent current squarer/divider and geometric mean input signal was an AC current of 120 mA pk on a DC
circuits. The impedances R1 and R2 were assumed to level of 250 mA. In the second case (2), Io ˆ 50 mA
be equal and were varied between 100 kO and 1 MO in and Ioq ˆ 40 mA (i.e. fo ˆ 1:1 MHz and Q ˆ 1:1). The
300 kO steps. The increased attenuation with input signal was an AC current of 50 mA pk on a DC
increasing impedance levels is clearly seen, and level of 100 mA. Fig. 10 shows that in both cases the
suggests that an improvement in performance could simulated and measured results are fairly close, and
be obtained by implementing subcircuit designs the difference is likely to be due to processing
featuring very high output impedance. tolerances (variations in C, b etc.). The low frequency
The non-linear terms introduced into the state attenuation is almost completely destroyed due to the
equations (equation (32)) will introduce ``sub- ®nite output impedance of the MOSFETs, as
harmonic'' non linear terms into the output, similar described in Section 5.2. The ®nite output impedance
to those of equation (22). These additional harmonic also shifts the bandpass zero up in frequency, and
terms can be minimized by minimizing the values of from Fig. 10 the position of this zero is around
Vth b1=2 =CR1 and Vth b1=2 =CR2 . 500 kHz, which from the approximate analysis of

Fig. 8. Simulation results of a behavioral model of the biquad

®lter, demonstrating the degradation in stopband attenuation with
decreasing sub-circuit output resistance. Fig. 9. Micophotograph of the biquad ®lter.

135
242 M. Eskiyerli and A. Payne

response as discussed in Sections 4.3 and 5.1, which

also leads to non-exact cancellation of the harmonic
terms generated internally as part of the non-linear
signal processing.

6. Conclusions

This paper has outlined the CMOS square root domain

®lter synthesis methodology, and has described the
implementation of particular non-linear subcircuits.
Although the circuit designs presented in this paper
verify the methodology presented, the potential for
performance improvement is clearly apparent and will
be the subject of future investigation. The current
Fig. 10. Comparison of simulated and measured biquad bandpass squarer-divider implementation shown here causes
response.
the greatest deviation from the ideal response, and
alternative circuit topologies may prove more suited
to this application. However the authors believe that
Section 5.2 predicts an impedance R2 of around 40 kO
the results presented are encouraging, in that they
shunting the capacitor at node V2 . This conclusion
demonstrate the validity of the proposed approach as
also seems to be con®rmed by reference to Fig. 8.
well as providing avenues for future research in this
For the tuning and input current levels given in (1),
area.
and with input signal frequency at 100 kHz, the
second and third harmonics were measured as
ÿ 50 dB and ÿ 54 dB relative to the fundamental,
respectively. Higher order harmonics were below the Note
noise ¯oor at ÿ 57 dB. In addition, additional
frequency terms occurring between the integer 1. Courtesy of LTP Electronics, Oxford, UK.
harmonics were observed. For an input signal of
100 kHz, the following spectral components were also
observed (levels relative to the fundamental): References

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``A current-mode companding Hx-domain integrator.'' Science, Technology and Medicine, London, UK.
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16. M. Ismail and T. Fiez, Chapter 3 in Analog VLSI: Signal and
Information Processing. McGraw Hill, Singapore, 1994.
Imperial College, London, UK. Her present research
17. J. Fattaruso and R. Meyer, ``MOS analog function synthesis.'' interests include RF bipolar and CMOS analog circuit
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18. H. Wasaki, Y. Horio, and S. Nakamura, ``Current multiplier/ design and circuit synthesis methodologies. Dr. Payne
divider circuit.'' Electronics Letters 27, pp. 504±506, 1991. has published various papers in international journals
19. K. Kimura, ``An MOS four-quadrant analog multiplier based
on the multitail technique using a quadritail call as a multiplier and conferences in the ®eld of analog IC design, and is
core.'' IEEE Transactions. On Circuits and Systems (I) 42, currently president of the IEEE Circuits and Systems
pp. 448±454, a995. Society Analog Signal Processing Technical
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McGraw-Hill, 1987. Murat Eskiyerli received his M.Sc. and Ph.D.
23. D. Neaman, ``Semiconductor Physics and Devices.'' 2nd
degrees in 1993 and 1998 respectively. His Ph.D. from
edition, Irwin, 1997.
24. M. Eskiyerli, Square-Root Domain Filters. Ph.D. Thesis,
Imperial College of Science and Technology, London,
Imperial College, London University, 1998. UK, was in the ®eld of Square Root Domain Filters.
Since 1998 he has been working as an analog
integrated circuit design engineer for Sony
Semiconductor of America, where his interests
include CMOS, BiCMOS and bipolar analog IC
designs, particularly for high speed and low voltage
applications. Murat is a member of the IEEE and IEE.

137