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MIXED  DESIGN 
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Verilog HDL Model Based Thermometer-to-Binary

Encoder with Bubble Error Correction
Zbigniew Jaworski
Institute of Microelectronics and Optoelectronics
Warsaw University of Technology
ul. Koszykowa 75, 00-662 Warszawa, Poland

�bstract—This paper compares several approaches to come mometer code) is large and the complexity of thermometer-
up with the Verilog HDL model of the thermometer-to-binary to-binary encoder grows rapidly. So, in the real-life cases it is
encoder with bubble error correction. It has been demonstrated practically impossible to try out competitive implementations.
that implementations of different ideas to correct bubble errors
yield circuits whose parameters tremendously vary in delay, II. T HE G OAL
area and power consumption. The shortest delay is achieved for
the design synthesized from the model which mimics a human The goal of this work was to investigate which thermometer-
reading temperature on classic liquid-in-glass thermometer. to-binary encoder implementation, encoded as a Verilog HDL
model, yields fastest solution and is resistant to 2nd order
Index Terms—thermometer-to-binary encoder, bubble error bubble error (which is a cluster of two sebsequent ’0’).
correction, FLASH ADC, HDL model, logic synthesis. Several experiments have been carried out to compare cost
of implementation (layout area and power consumption) of
I. I NTRODUCTION different solutions.
Nowadays, the use of automatic logic synthesis of Verilog A. Assumptions
or VHDL model to generate a digital circuit is the preferred
All the implementations discussed in this paper have been
design style, especially when complex algorithms are imple-
developed under the following assumptions concerning the
mented [1]–[6]. The obvious advantages, among the others,
input thermometer code:
are ease of targeting different technologies and simplicity to
• all the bits set to ’1’ are correct,
make changes to constraints in order to obtain fast or low-
• all the bits set to ’0’ above top ’1’ are correct,
power circuit.
• all the bits set to ’0’ below top ’1’ are incorrect.
Modern commercial CAD software are powerful tools
boasting 100+ million gate strength. However, the design It should be noted that the bubble error that modifies the top
performance resulting from HDL code synthesis is highly most ’1’ cannot be detected since there is no way to distinguish
sensitive to modeling style. The Verilog or VHDL statements it from valid ’0’. None of the existing solution [19]–[24] can
and model structures, which appear to an average engineer correct this specific location of BER.
absolutely equivalent, are often processed by the logic synthe- B. Encoder Structure
sis tools in completely different way. As a consequence, the Typical solution to improve performance of a design, either
same CAD tool may infer a completely unalike logic imple- in case of software or hardware, is the divide and conquer
mentation for the exactly the same algorithm but differently approach. In the case of the encoder, a simple decomposition
encoded. technique has been employed [18]. Whenever it made a sense,
A thermometer-to-binary encoder is a standard component the encoder was divided into several segments that indepen-
of flash ADC [7]–[18]. One of the common design problem to dently process a sub-ranges of the input vector. Each segment
be solved there is how to make the circuit resistant to bubble produces a sub-code which are subsequently aggregated to
error [19]–[24]. The bubble error (BER) is defined as a missing produce the final output binary code. The modified encoder
’1’ in input thermometer code. The BER may be a result of structure is shown in the Fig.1.
e.g. switching noise spreading through the comparators of the
FLASH ADC. Whatever is the reason of a BER it results in �
� �� �
� ��
erroneous output binary code. ��������
�����������
The typical approach to encoder implementation is to use � ������������ �
������� ��
a ROM or devise a combinatorial circuit whose structure is ���������
derived directly from Boolean expression [7]–[17], [19]–[24]. � ��������
However, these approaches do not exhibit the flexibility pro- � �����������
vided by automatic logic synthesis. This disadvantage is par-
ticularly burdensome in cases of higher ADC resolutions when Fig. 1. The idea of encoder decomposition.
number of comparators (and thus the number of bits in ther-

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C. Bubble Error Correction The results are shown in Table I. As can be observed, the
The two classic bubble error correction (BEC) approaches fastest and smallest implementation (but most power-hungry)
have been employed. The first one utilizes OR gates to form is obtained for the simplest solution.
logical sum of three neighboring bits: LISTING I
M ODEL OF ”T HE HIGHEST ’1’” DECOMPOSED INTO 2 SEGMENTS .

module t h e r m o 2 b i n ( thermo , b i n ) ;
bcorr [i] = b[i] ∨ b[i � 1] ∨ b[i � 2] (1) input [ 6 2 : 0 ] thermo ;
output [ 5 : 0 ] bin ;
where n = 0 � � � 2n − 3
reg [ 5 : 0 ] bin , bin1 , bin2 ;
The second method utilizes a modified one-hot encoder. It integer i , j ;
takes 3-input AND gate to convert thermometer code into one-
a l w a y s @( t h e r m o )
hot code: begin
bin1 = 0;
bcorr [i] = b[i] ∧ �b[i � 1] ∧ �b[i � 2] (2) f o r ( i = 1 ; i �=32; i = i + 1 )
i f ( t h e r m o [ i −1] == 1 ’ b1 ) b i n 1 = i ;
where n = 0 � � � 2n − 3. end

The side-effect of one-hot encoding is elimination of the a l w a y s @( t h e r m o )

bubble errors. begin
bin2 = 0;
f o r ( j = 1 ; j �=31; j = j + 1 )
D. Logic Synthesis i f ( t h e r m o [ j +3 1 ] == 1 ’ b1 ) b i n 2 = j ;
end
All the proposed encoder implementations have been syn-
thesized with a commercial CAD tool. An industrial 65 nm a l w a y s @( b i n 1 or b i n 2 )
i f ( bin2 > 0)
CMOS process has been chosen as the target technology. bin = bin2 + 32;
Since the FLASH ADCs are used for their speed the synthesis else
bin = bin1 ;
process has been carried out in such a way to determine which
solution yields fastest circuits. In practice, synthesis has been endmodule
performed several times for each model to find out the shortest
timing constraint that yields nonzero worst slack.
TABLE I
Because realistic estimation of delays introduces by inter- R ESULTS OF SYNTHESIS OF ”T HE HIGHEST ’1’” ENCODER .
connects is crucial for design realized in nanometer technolo-
gies the synthesis tool was setup to use topological mode � of segments delay � of sdt. cells sdt. cell area power
[ps] [µm� � [µ� �
to calculate the parameters of nets. In this case, instead of
1 290 267 1467 2406
statistical wire models, placement and routing are performed 2 355 231 1218 1685
in order to obtain detail values of the parasitics R and C of 4 460 230 1156 1479
the wiring. 8 415 246 1258 1586
16 297 295 1510 2666
III. S OLUTION 1: T HE H IGHEST ’1’
The first tested solution mimics the way a human is reading IV. S OLUTION 2: T HE H IGHEST ’1’ WITH BEC
temperature on the classic liquid-in-glass thermometer. It logic This solution is very similar to the previous one. The exam-
terms it means the binary output code equals to the index of ple Verilog model is shown in the Listing II. The additional
the most significant input bit which is set to ’1’. procedural block implements the OR-based BEC.
In practice, it is achieved by scanning the complete range The existence of the BEC pre-processing logic allows to use
of input bits (bottom-up approach) and storing the index of the simpler condition statement thermo[31] == 1’b1 in
each passed bit which is set to ’1’. As scanning does not stop the process responsible for sub-codes aggregation. However,
when examined bit equals ’0’ and this solution is immune additional process (the BEC implementation) may result in
to all kinds of bubble error. The example implementation is longer critical path. It is impossible to predict which effect is
presented in Listing I. dominant. This may depend on parameters of standard cells
Since there may be an erroneous ’0’ present in the input from the particular target library or even algorithms used by
thermometer code the sub-codes aggregation requires usage the particular synthesis tool.
of bin2 > � condition instead of thermo[31] == 1’b1 The five variants (decomposition into 1, 2, 4, 8 and 16
which would be perfectly valid in case of error-free input segments) of this encoder version have been synthesized. The
code. An inevitable disadvantage of this solution is that results are shown in Table II.
the implementation of bin2 > � condition requires a full As can be observed, this time the fastest design is obtained
comparator (6-bit in case of the example shown in Listing I). when encoder is split into 2 segments. This approach yields
This may result in longer critical path as well as larger layout circuit with even shorter critical path than pure ”The Highest
area and power consumption. ’1’” concept. But implementation cost (layout area and total
The five variants (decomposition into 1, 2, 4, 8 and 16 power consumption) is higher. It should be noted that this
segments) of ”The highest ’1’” encoder have been synthesized. approach is resistant to 2nd order bubble error at most.

���
 LISTING II LISTING III
”T HE H IGHEST ’1’ WITH BEC” DECOMPOSED INTO 2 SEGMENTS . O NE - HOT ENCODING

module t h e r m o 2 b i n ( thermob , b i n ) ; module t h e r m o 2 b i n ( thermob , b i n ) ;

input [ 6 2 : 0 ] thermob ; input [ 6 2 : 0 ] thermob ;
output [ 5 : 0 ] bin ; output [ 5 : 0 ] bin ;

reg [ 6 2 : 0 ] thermo ; reg [ 6 2 : 0 ] thermo ;

reg [ 5 : 0 ] bin , bin1 , bin2 ; reg [ 5 : 0 ] bin , bin1 , bin2 ;
integer i , j , k ; integer i , j , k ;

a l w a y s @( t h e r m o b ) a l w a y s @( t h e r m o b )
begin begin
f o r ( k = 0 ; k �=60; k=k + 1 ) f o r ( k = 0 ; k �=60; k=k + 1 )
t h e r m o [ k ] �= t h e r m o b [ k ] | | t h e r m o b [ k + 1 ] | | t h e r m o b [ k + 2 ] ; t h e r m o [ k ] �= t h e r m o b [ k ] �� ˜ t h e r m o b [ k + 1 ] �� ˜ t h e r m o b [ k + 2 ] ;

t h e r m o [ 6 1 ] �= t h e r m o b [ 6 1 ] | | t h e r m o b [ 6 2 ] ; t h e r m o [ 6 1 ] �= t h e r m o b [ 6 1 ] �� ˜ t h e r m o b [ 6 2 ] ;
t h e r m o [ 6 2 ] �= t h e r m o b [ 6 2 ] ; t h e r m o [ 6 2 ] �= t h e r m o b [ 6 2 ] ;
end end

a l w a y s @( t h e r m o ) a l w a y s @( t h e r m o )
begin begin
bin1 = 0; bin1 = 0;
f o r ( i = 1 ; i �=32; i = i + 1 ) f o r ( i = 1 ; i �=32; i = i + 1 )
i f ( t h e r m o [ i −1] == 1 ’ b1 ) b i n 1 = i ; i f ( t h e r m o [ i −1] == 1 ’ b1 ) b i n 1 = i ;
end end

a l w a y s @( t h e r m o ) a l w a y s @( t h e r m o )
begin begin
bin2 = 0; bin2 = 0;
f o r ( j = 1 ; j �=31; j = j + 1 ) f o r ( j = 1 ; j �=31; j = j + 1 )
i f ( t h e r m o [ j + 3 1 ] == 1 ’ b1 ) b i n 2 = j ; i f ( t h e r m o [ j +3 1 ] == 1 ’ b1 ) b i n 2 = j ;
end end

a l w a y s @( b i n 1 or b i n 2 ) a l w a y s @( b i n 1 or b i n 2 )
i f ( t h e r m o [ 3 1 ] == 1 ’ b1 ) i f ( bin2 > 0)
bin = bin2 + 32; bin = bin2 + 32;
else else
bin = bin1 ; bin = bin1 ;

endmodule endmodule

TABLE II TABLE III

R ESULTS OF SYNTHESIS OF ”T HE HIGHEST ’1’ WITH BEC” R ESULTS OF SYNTHESIS OF ”O NE - HOT ENCODING ”

� of segments delay � of sdt. cells sdt. cell area power � of segments delay � of sdt. cells sdt. cell area power
[ps] [µm� � [µ� � [ps] [µm� � [µ� �
1 345 208 1093 1519 1 287 295 1651 2916
2 276 348 2022 4165 2 304 284 1426 2391
4 296 220 1211 2292 4 410 257 1319 1808
8 307 251 1412 2616 8 455 274 1470 1694
16 455 244 1153 1145 16 490 281 1445 1199

V. S OLUTION 3: O NE -H OT E NCODING VI. S OLUTION 4: S UM OF B ITS WITH OR- BASED BEC

The one-hot encoding is a typical approach utilized in The next approach which has been examined is the sum of
the thermometer-to-binary encoder implementations based on all the bits in the input code (a.k.a fat tree). Implementation
ROM usage. The immanent feature of this encoding is elimina- of this idea should results in combinational logic built of
tion of the bubble errors. The proposed solution encodes the adders. The bubble error correction has been realized by means
input thermometer word into one-hot code in the first step. of inserting the OR-based BEC between the input port and
The obtained code contains only one ’1’ in the whole vector, the classic implementation of the encoder. This additional
which is also the highest ’1’. Thus, the binary output can be Verilog procedural block transforms input vector into bubble-
calculated exactly in the same way as previously. The example free internal code which is subsequently used to produce the
implementation is presented in Listing III. binary output simply by summing up all the bits. The example
The five variants (decomposition into 1, 2, 4, 8 and 16 implementation is presented in Listing IV.
segments) of this encoder version have been synthesized. The The five variants (decomposition into 1, 2, 4, 8 and 16
results of are shown in Table III. As can be observed, the segments) of this encoder version have been synthesized.
shortest critical path is obtained for the simplest version, The results are shown in Table IV. As can be seen, the
without segmentation. The delay value is almost identical to shortest critical path is obtained for design decomposed into
the one obtained in the first solution (”the highest ’1’”) and 16 segments. The shortest possible delay value is longer than
slightly greater than attained for the 2nd proposition. those obtained in all the previous solutions.

���
 LISTING IV LISTING V
S UM OF BITS WITH OR M ODEL VERSION C: D IRECT TRUTH TABLE IMPLEMENTATION

module t h e r m o 2 b i n ( thermob , b i n ) ; module t h e r m o 2 b i n ( thermo , b i n ) ;

input [ 6 2 : 0 ] thermob ; input [ 6 2 : 0 ] thermo ;
output [ 5 : 0 ] bin ; output [ 5 : 0 ] bin ;

reg [ 6 2 : 0 ] thermo ; reg [ 5 : 0 ] bin ;

reg [ 5 : 0 ] bin , bin1 , bin2 ; integer k ;
integer i , j , k ; reg [ 6 2 : 0 ] thermo ;

a l w a y s @( t h e r m o b ) a l w a y s @( t h e r m o b )
begin begin
f o r ( k = 0 ; k �=60; k=k + 1 ) f o r ( k = 0 ; k �=60; k=k + 1 )
t h e r m o [ k ] �= t h e r m o b [ k ] | | t h e r m o b [ k + 1 ] | | t h e r m o b [ k + 2 ] ; t h e r m o [ k ] �= t h e r m o b [ k ] | | t h e r m o b [ k + 1] | | t h e r m o b [ k + 2 ] ;

t h e r m o [ 6 1 ] �= t h e r m o b [ 6 1 ] | | t h e r m o b [ 6 2 ] ; t h e r m o [ 6 1 ] �= t h e r m o b [ 6 1 ] | | t h e r m o b [ 6 2 ] ;
t h e r m o [ 6 2 ] �= t h e r m o b [ 6 2 ] ; t h e r m o [ 6 2 ] �= t h e r m o b [ 6 2 ] ;
end end

a l w a y s @( t h e r m o ) a l w a y s @( t h e r m o )
begin casez ( thermo )
bin1 = 0; 63 ’ h0000000000000000 : bin = 0;
f o r ( i = 0 ; i �=31; i = i + 1 ) 63 ’ h0000000000000001 : bin = 1;
bin1 = bin1 + thermo [ i ] ; 63 ’ h0000000000000003 : bin = 2;
end ..................... .. .... .....
..................... .. .... .....
a l w a y s @( t h e r m o ) ..................... .. .... .....
begin 63 ’ h 1 f f f f f f f f f f f f f f f : bin = 61;
bin2 = 0; 63 ’ h 3 f f f f f f f f f f f f f f f : bin = 62;
f o r ( j = 3 2 ; j �=62; j = j + 1 ) 63 ’ h 7 f f f f f f f f f f f f f f f : bin = 63;
bin2 = bin2 + thermo [ j ] ; / / To avoid D-latches default bin value has to be set.
end / / Possible options are: 6’b000000, 6’b111111, 6’bzzzzzz
default : bin = 6 ’ b000000 ;
a l w a y s @( b i n 1 or b i n 2 ) endcase
i f ( bin2 > 0)
bin = bin2 + 32; endmodule
else
bin = bin1 ;
LISTING VI
endmodule M ODEL VERSION D: PRIORITY ENCODER

module t h e r m o 2 b i n ( thermob , b i n ) ;
input [ 6 2 : 0 ] thermob ;
TABLE IV output [ 5 : 0 ] bin ;
R ESULTS OF SYNTHESIS OF ”S UM OF BITS WITH OR”
integer k ;
reg [ 6 2 : 0 ] thermo ;
� of segments delay � of sdt. cells sdt. cell area power
reg [ 5 : 0 ] bin ;
[ps] [µm� � [µ� �
1 1010 1104 6821 4953 a l w a y s @( t h e r m o b )
2 910 1128 6624 4827 begin
4 650 926 5578 5474 f o r ( k = 0 ; k �=60; k=k + 1 )
t h e r m o [ k ] �= t h e r m o b [ k ] | | t h e r m o b [ k + 1] | | t h e r m o b [ k + 2 ] ;
8 470 621 3668 4575
16 325 341 1674 2987 t h e r m o [ 6 1 ] �= t h e r m o b [ 6 1 ] | | t h e r m o b [ 6 2 ] ;
t h e r m o [ 6 2 ] �= t h e r m o b [ 6 2 ] ;
end

VII. S OLUTION 5: T RUTH TABLE a l w a y s @( t h e r m o )

casez ( thermo )
The last attempt to encoder realization was based on the �63 ’ b0 }: bin = 0;
�62 ’ b0 , 1 ’ b1 } : bin = 1;
truth table implementation (Listing V). Since only small subset �61 ’ b0 , 1 ’ b1 , 1 ’ bz } : bin = 2;
of all possible combinations of input bit values are utilized �60 ’ b0 , 1 ’ b1 , 2 ’ bz } : bin = 3;
...................... ..........
there the default binary value has to be set in order to avoid ...................... ..........
D-latches. The possible options of the default output value are: ...................... ..........
� 2 ’ b0 , 1 ’ b1 , 60 ’ bz } : bin = 61;
6’b������, 6’b111111 and 6’bzzzzzz. � 1 ’ b0 , 1 ’ b1 , 61 ’ bz } : bin = 62;
The truth table may be also implemented in the form of � 1 ’ b1 , 62 ’ bz } : bin = 63;
endcase
so called priority encoder (Listing VI). In this case the upper
triangular part of the truth table is filled with 0s while the 1s endmodule
appear on the diagonal. The lower triangular part is filled with
don’t care values (in Verilog represented as ’z’). The three variants of truth table based design and priority
In the both cases the OR-based BEC is to used to transforms encoder based implementations have been synthesized. The
input vector into bubble-free internal code which is then parameters of the obtained circuits are shown in Table V and
subsequently converted into the binary output. Table VI respectively. The results shown there prove that the
priority encoder allow for faster and smaller circuits.

���
 TABLE V particular standard cells from a specific target library. Thus,
R ESULTS OF SYNTHESIS OF TRUTH TABLE IMPLEMENTATION in case of other technologies (or different technology modules
default case delay � of sdt. cells sdt. cell area power e.g. high performance, low-leakage, etc.) it may turn out that
[ps] [µm� � [µ� � shortest delay is achieved for a different model variant than
bin = 6’b000000 401 703 4218 5767 reported in this paper. Analogous effects might be expected
bin = 6’b111111 375 704 4339 6320 when different synthesis tool is used.
bin = 6’bzzzzzz 644 509 2557 2157
IX. C ONCLUSIONS
TABLE VI
R ESULTS OF SYNTHESIS OF PRIORITY ENCODER
As has been demonstrated in this paper, in real-life projects,
when the number of comparators in the FLASH ADC is large,
delay � of sdt. cells sdt. cell area power finding an optimal implementation of thermometer-to-binary
[ps] [µm� � [µ� �
encoder is not so easy.
360 309 1417 2222
A routine task like converting thermometer code into binary
word seems to be a relatively easy to realize. However, with
VIII. S UMMARY OF R ESULTS larger number of the input bits complexity of the resulting
logic grows rapidly, both in therms of the number of used logic
The five different approaches to implement thermometer- gates as well as the length of interconnections. The critical
to-binary encoder with be bubble error correction have been path, layout area and power consumption depends heavily
examined. Whenever it made a sense, a simple decomposition on the actual logic structure and parasitics introduced be the
technique (divide and conquer approach) has been employed. wiring.
All the Verilog models have been synthesized with a com- Evidently, full-custom approach to such a task is burden-
mercial CAD tool. An industrial 65 nm CMOS process has some and automatic logic synthesis seems to be a sensible al-
been used as the target technology. The synthesis procedure ternative. However, there are pitfalls here, too. Various VHDL
has been carried out in such a way that allowed to obtain the or Verilog HDL statements and/or model structures may result
fastest possible circuit for every variant. in completely different parameters of the synthesized circuits.
The Table VII presents parameters of the three best designs: The fact an average engineer is usually not aware of.
”the highest ’1’”, ”the highest ’1’ with BEC” and ”one-hot
In order to get the most from automatic logic synthesis
encoding”.
designers have to understand how CAD tools infer logic. It
should be clear that even most powerful software cannot im-
TABLE VII
R ESULTS OF SYNTHESIS : THE FASTEST MODEL VARIANTS
prove poor algorithms and/or poor encoding. It is the engineer
role to come up with clever ideas and specify it in such way
model variant parts delay cells cell area power that CAD tools can generate optimal implementation.
[ps] [µm� � [µ� �
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