Digital Electronics

Author: Dr. Himanshu Gupta, Associate Professor, AIIT, Amity University, Noida Page 1
 Digital Electronics

Analog and Digital are the different forms of signals. Signals are used to carry information from one
device to another. Analog signal is a continuous wave that keeps on changing over a time period. Digital
signal is discrete in nature. The fundamental difference between analog and digital signal is that analog
signal is represented by the sine waves whereas, the digital signal is represented by square waves.

Comparison Chart

BASIS FOR
ANALOG SIGNAL DIGITAL SIGNAL
COMPARISON

Basic An analog signal is a continuous wave that A digital signal is a discrete wave that

changes over a time period. carries information in binary form.

Representation An analog signal is represented by a sine A digital signal is represented by square

wave. waves.

Description An analog signal is described by the A digital signal is described by bit rate and

amplitude, period or frequency, and phase. bit intervals.

Range Analog signal has no fixed range. Digital signal has a finite numbers i.e. 0

and 1.

Distortion An analog signal is more prone to distortion. A digital signal is less prone to distortion.

Transmit An analog signal transmit data in the form of A digital signal carries data in the binary

a wave. form i.e. 0 nad 1.

Author: Dr. Himanshu Gupta, Associate Professor, AIIT, Amity University, Noida Page 2
 Digital Electronics

BASIS FOR
ANALOG SIGNAL DIGITAL SIGNAL
COMPARISON

Example The human voice is the best example of an Signals used for transmission in a

analog signal. computer are the digital signal.

DeMorgan’s Theorem is mainly used to solve the various Boolean algebra expressions. The
Demorgan’s theorem defines the uniformity between the gate with same inverted input and
output. It is used for implementing the basic gate operation likes NAND gate and NOR gate.
The Demorgan’s theorem mostly used in digital programming and for making digital circuit
diagrams. There are two DeMorgan’s Theorems. They are described below in detail.

DeMorgan’s First Theorem

According to DeMorgan’s first theorem, a NOR gate is equivalent to a bubbled AND gate.
The Boolean expressions for the bubbled AND gate can be expressed by the equation shown
below.

For NOR gate, the equation is

For the bubbled AND gate the equation is

As the NOR and bubbled gates are interchangeable, i.e., both gates have exactly identical
outputs for the same set of inputs.

Author: Dr. Himanshu Gupta, Associate Professor, AIIT, Amity University, Noida Page 3
 Digital Electronics

Therefore, the equation can be written as shown below.

This equation (1) or identity shown above is known as DeMorgan’s Theorem. The symbolic
representation of the theorem is shown in the figure below.

DeMorgan’s Second Theorem

DeMorgan’s Second Theorem states that the NAND gate is equivalent to a bubbled OR gate.

The Boolean expression for the NAND gate is given by the equation shown below.

The Boolean expression for the bubbled OR gate is given by the equation shown below.

Since NAND and bubbled OR gates are interchangeable, i.e., both gates have identical
outputs for the same set of inputs. Therefore, the equations become as given below.

This identity or equation (2) shown above is known as DeMorgan’s Second Theorem.

Author: Dr. Himanshu Gupta, Associate Professor, AIIT, Amity University, Noida Page 4
 Digital Electronics

The symbolic representation of the theorem is shown in the figure below.

The Bubbled OR Gate

The logic circuit of the bubbled OR gate is shown below.

The truth table for bubbled OR gate is shown below.

A B Z

0 0 1

0 1 1

1 0 1

1 1 0

Author: Dr. Himanshu Gupta, Associate Professor, AIIT, Amity University, Noida Page 5
 Digital Electronics

In this, both the inputs are inverted before they are applied to an OR gate. The output of a
bubbled OR gate can be derived from its logic circuit and can be expressed by the equation
shown below.

Here are the results when the logic circuit of bubbled OR gate when all the possible sets of
inputs are applied such as 00, 01, 10 or 11.

For AB: 00

For AB: 01

For AB: 10

For AB: 11

The truth table for the bubbled AND gate is exactly identical to the truth table of a NAND
gate. Hence, NAND and bubbled OR gate is interchangeable.

Author: Dr. Himanshu Gupta, Associate Professor, AIIT, Amity University, Noida Page 6
 Digital Electronics

1’s and 2’s complement of a Binary Number

1’s complement of a binary number is another binary number obtained by toggling all bits in it,
i.e., transforming the 0 bit to 1 and the 1 bit to 0.
Examples:
1's complement of "0111" is "1000"

1's complement of "1100" is "0011"

2’s complement of a binary number is 1 added to the 1’s complement of the binary number.
Examples:
2's complement of "0111" is "1001"

2's complement of "1100" is "0100"

For one’s complement, we simply need to flip all bits.

For 2’s complement, we first find one’s complement. We traverse the one’s complement
starting from LSB (least significant bit), and look for 0. We flip all 1’s (change to 0) until we
find a 0. Finally, we flip the found 0. For example, 2’s complement of “01000” is “11000”
(Note that we first find one’s complement of 01000 as 10111). If there are all 1’s (in one’s
complement), we add an extra 1 in the string. For example, 2’s complement of “000” is “1000”
(1’s complement of “000” is “111”).

BCD Subtraction using 9’s Complement and 10s complement

Decimal BCD Subtractor – Addition of signed BCD numbers can be performed by using 9’s
or 10’s complement methods. A negative BCD number can be expressed by taking the 9’s or
10’s complement.

9’s Complement

The 9’s complement of a decimal number is found by subtracting each digit in the number
from 9. The 9’s complement of each of the decimal digits is as follows:

Author: Dr. Himanshu Gupta, Associate Professor, AIIT, Amity University, Noida Page 7
 Digital Electronics

9’s Complement Subtraction:

In 9’s complement subtraction when 9’s complement of smaller number is added to the larger
number carry is generated. It is necessary to add this carry to the result. (This is called an end-
around carry). When larger number is subtracted from smaller one, there is no carry, and the

Author: Dr. Himanshu Gupta, Associate Professor, AIIT, Amity University, Noida Page 8
 Digital Electronics

result is in 9’s complement form and negative. This is illustrated in following examples

10’s Complement Subtraction

The 10’s complement of a decimal number is equal to the 9’s complement plus 1. The 10’s
complement can be used to perform subtraction by adding the minuend to the 10’s
complement of the subtrahend and dropping the carry. This is illustrated in following
examples.

Author: Dr. Himanshu Gupta, Associate Professor, AIIT, Amity University, Noida Page 9
 Digital Electronics

From the above examples we can summarize steps for 9’s complement BCD subtraction as
follows:

1. Find the 9’s complement of a negative number

2. Add two numbers using BCD addition
3. If carry is generated add carry to the result otherwise find the 9’s complement of the
result.

From the above examples we can summarize steps for 10’s complement BCD subtraction as
follows.

1. Find the 10’s complement of a negative number

2. Add two numbers using BCD addition
3. If carry is not generated find the 10’s complement of the result.

Weighted and Non-Weighted Code

The weighted codes are those that obey the position weighting principle, which states that the
position of each number represents a specific weight. In these codes each decimal digit is
represented by a group of four bits. In weighted codes, each digit is assigned a specific weight
according to its position. For example, in 8421/BCD code, 1001 the weights of 1, 1, 0, 1 (from
left to right) are 8, 4, 2 and 1 respectively. There are millions of weighted codes. The most
common one is 8421/BCD Code.

Examples: 8421, 2421, 84-2-1 are all weighted codes.

The non-weighted codes are not positionally weighted. In other words codes that are not
assigned with any weight to each digit position.

Examples: Excess-3(XS-3) and Gray Codes.

Author: Dr. Himanshu Gupta, Associate Professor, AIIT, Amity University, Noida Page 10
 Digital Electronics

Difference between Weighted and Non-Weighted Codes

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 Digital Electronics

Standard Representation of Logical Functions (SOP and POS Form)

The main difference between SOP and POS is that the SOP is a way of representing a
Boolean expression using min terms or product terms while the POS is a way of
representing a Boolean expression using max terms or sum terms.

Digital circuits use digital signals to operate. These signals have binary values; they can be
either one or zero. Zero represents false or low state whereas one represents true or high state.
Boolean algebra helps to describe the binary numbers and binary variables. To be more
specific, a Boolean function is an algebraic form of Boolean expression. It is also possible to
simplify Boolean functions of digital circuits using Boolean laws and theorems. Furthermore,
SOP and POS are two methods of representing Boolean expressions.

SOP

SOP stands for Sum of Products. Writing a Boolean expression using product terms is called
Sum of Products form. The product terms are also known as min-terms. An example is as
follows.

Author: Dr. Himanshu Gupta, Associate Professor, AIIT, Amity University, Noida Page 12
 Digital Electronics

For instance, assume that P and Q are input variables and F is the output variable. We take
the complement of the variable for 0 and take the variable for 1. Then we can write the
minterms by writing the product terms.

P Q F Minterms

0 0 0 P’Q’

0 1 1 P’Q

1 0 1 PQ’

1 1 1 PQ

Finally, we can take the sum of all the minterms that has 1 for F. Therefore; the final
expression is as follows.

F = P’Q + PQ’ + PQ

POS

POS stands for Product of Sums. Writing a Boolean expression using sum terms is called
Product of Sum form. We also call the sum terms as max-terms.

For example, assume that P and Q are input variables and F is the output variable. Here, we
take the variable for 0 and take the complement of the variable for 1. Then we can write the
max terms by writing the sum terms.

P Q F Maxterms

0 0 0 P+Q

0 1 1 P+ Q’

1 0 1 P’+Q

1 1 0 P’+Q’

Finally, we can take the product of all max terms that has 0 for F. Thus; the final expression
is as follows.

F = (P+Q). (P’ + Q’)

Author: Dr. Himanshu Gupta, Associate Professor, AIIT, Amity University, Noida Page 13
 Digital Electronics

SOP to POS Conversion

Let x = ab'c + bc'

x' = (ab'c + bc')'

By DeMorgan's theorem, x' = (a' + b + c')(b' + c)

x' = a'b' + a'c + bb' + bc + c'b' + c'c

x' = a'b' + a'c + bc + c'b'

Employing DeMorgan's theorem again, x = (a'b' + a'c + bc + c'b')'

x = (a + b)(a + c')(b' + c')(c + b)

Karnaugh Map (K-Map)

The Karnaugh map (KM or K-map) is a method of simplifying Boolean algebra expressions.
Maurice Karnaugh introduced it in 1953 as a refinement of Edward Veitch's 1952 Veitch chart,
Karnaugh maps are therefore also known as Karnaugh–Veitch maps (KV maps).

The required Boolean results are transferred from a truth table onto a two-dimensional grid
where, in Karnaugh maps, the cells are ordered in Gray Code, and each cell position
represents one combination of input conditions, while each cell value represents the
corresponding output value. Optimal groups of 1s or 0s are identified, which represent the
terms of a canonical form of the logic in the original truth table. These terms can be used to
write a minimal Boolean expression representing the required logic.

Example:

Karnaugh maps are used to facilitate the simplification of Boolean algebra functions. For
example, consider the Boolean function described by the following truth table.

Author: Dr. Himanshu Gupta, Associate Professor, AIIT, Amity University, Noida Page 14
 Digital Electronics

Truth table of a function

A B C D

0 0 0 0 0 0

1 0 0 0 1 0

2 0 0 1 0 0

3 0 0 1 1 0

4 0 1 0 0 0

5 0 1 0 1 0

6 0 1 1 0 1

7 0 1 1 1 0

8 1 0 0 0 1

9 1 0 0 1 1

10 1 0 1 0 1

11 1 0 1 1 1

12 1 1 0 0 1

13 1 1 0 1 1

14 1 1 1 0 1

15 1 1 1 1 0

Following are two different notations describing the same function in unsimplified Boolean
algebra, using the Boolean variables A, B, C, D, and their inverses.

f(A,B,C,D)=∑mi, i€ {6,8,9,10,11,12,13,14} where mi are the minterms to map (i.e., rows that
have output 1 in the truth table).

Solution:

Diagram showing two K-maps. The K-map for the function f (A, B, C, D) is shown as colored
rectangles which correspond to minterms. The brown region is an overlap of the red 2×2

Author: Dr. Himanshu Gupta, Associate Professor, AIIT, Amity University, Noida Page 15
 Digital Electronics

square and the green 4×1 rectangle. The K-map for the inverse of f is shown as gray rectangles,
which correspond to maxterms.

Author: Dr. Himanshu Gupta, Associate Professor, AIIT, Amity University, Noida Page 16
 Digital Electronics

5-Variables K-Map Simplification

Larger Karnaugh maps reduce larger logic designs. That depends on the number of inputs, to
the logic circuit under consideration. The answer is no more than six inputs for most all
designs, and five inputs for the average logic design. The five variable Karnaugh map follows.

The older version of the five variable K-map, a Gray Code map or reflection map, is shown
above. The top (and side for a 6-variable map) of the map is numbered in full Gray code. The
Gray code reflects about the middle of the code. This style map is found in older texts. The
newer preferred style is below.

Author: Dr. Himanshu Gupta, Associate Professor, AIIT, Amity University, Noida Page 17
 Digital Electronics

The overlay version of the Karnaugh map, shown above, is simply two (four for a 6-variable
map) identical maps except for the most significant bit of the 3-bit address across the top. If we
look at the top of the map, we will see that the numbering is different from the previous Gray
code map. If we ignore the most significant digit of the 3-digit numbers, the sequence 00, 01,
11, 10 is at the heading of both sub maps of the overlay map. The sequence of eight 3-digit
numbers is not Gray code. Though the sequence of four of the least significant two bits is.

Let’s put our 5-variable Karnaugh Map to use. Design a circuit which has a 5-bit binary input
(A, B, C, D, E), with A being the MSB (Most Significant Bit). It must produce an output logic
High for any prime number detected in the input data.

We show the solution above on the older Gray code (reflection) map for reference. The prime
numbers are (1,2,3,5,7,11,13,17,19,23,29,31). Plot a 1 in each corresponding cell. Then,
proceed with grouping of the cells. Finish by writing the simplified result. Note that 4-cell group
A’B’E consists of two pairs of cell on both sides of the mirror line. The same is true of the 2-
cell group AB’DE. It is a group of 2-cells by being reflected about the mirror line. When using
this version of the K-map look for mirror images in the other half of the map.

Out = A’B’E + B’C’E + A’C’DE + A’CD’E + ABCE + AB’DE + A’B’C’D

Below we show the more common version of the 5-variable map, the overlay map. If we
compare the patterns in the two maps, some of the cells in the right half of the map are moved
around since the addressing across the top of the map is different. We also need to take a
different approach at spotting commonality between the two halves of the map. Overlay one
half of the map atop the other half. Any overlap from the top map to the lower map is a

Author: Dr. Himanshu Gupta, Associate Professor, AIIT, Amity University, Noida Page 18
 Digital Electronics

potential group. The figure below shows that group AB’DE is composed of two stacked cells.
Group A’B’E consists of two stacked pairs of cells.

For the A’B’E group of 4-cells ABCDE = 00xx1 for the group. That is A,B,E are the same 001
respectively for the group. And, CD=xx that is it varies, no commonality in CD=xx for the
group of 4-cells. Since ABCDE = 00xx1, the group of 4-cells is covered by A’B’XXE = A’B’E.

Example: Given function, F = Σ (4, 9, 10, 11, 12, 14, 20, 28)

Example 1 of 5-Variable K-Map

Given function, F = Σ (1, 3, 4, 5, 11, 12, 14, 16, 20, 21, 30)
Since, the biggest number is 30, we need to have 5 variables to define this function.

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 Digital Electronics

Let’s draw K-Map for this function by writing 1 in cells that are present in function and 0 in rest
of the cells.

Applying rules of simplifying K-Map, there is no octet. There is one quad that is obtained by
visualizing second square on first, there are 4 adjacent cells – 4,5,20 and 21. The octet is
highlighted by a blue connecting line. There are 5 pairs. Similar to quad, there is one pair
between two squares which is highlighted by the blue connecting line.

(4, 5, 20, 21) – B’CD’ (Since A & E are the changing variables, it is eliminated)

(12, 14) – A’BCE’ (Since D is the changing variable, it is eliminated)

(14, 30) – BCDE’ (Since A is the changing variable, it is eliminated)

(3, 11) – A’C'DE (Since B is the changing variable, it is eliminated)

(16, 20) – AB’D'E’ (Since C is the changing variable, it is eliminated)

(1, 3) – A’B'C’E (Since D is the changing variable, it is eliminated)

Thus, F = B’CD’ + A’BCE’ + BCDE’ + A’C'DE + AB’D'E’ + A’B'C’E

Example 2 of 5-Variable K-Map

Given function, F = Σ (0, 2, 3, 5, 7, 8, 11, 13, 17, 19, 23, 24, 29, 30)
Since, the biggest number is 30, we need to have 5 variables to define this function.

Let’s draw K-Map for this function by writing 1 in cells that are present in function and 0 in rest
of the cells.

Author: Dr. Himanshu Gupta, Associate Professor, AIIT, Amity University, Noida Page 20
 Digital Electronics

Applying rules of simplifying K-Map, there is no octet. First we need to look for quads within
each of the squares. There are none but there is a quad between two squares that is obtained by
visualizing second square on first, there are 4 adjacent cells – 3, 7, 19 and 23. This quad is
highlighted by blue connecting line. There are 6 pairs, out of which two are between two
squares, highlighted by blue connecting line.
(3, 7, 19, 23) - B’DE (Since A & C are the changing variables, they are eliminated)

(3, 11) – A’C'DE (Since B is the changing variables, it is eliminated)

(1, 2) – A’B'C’E’ (Since D is the changing variables, it is eliminated)

(5, 7) – A’B'CE (Since D is the changing variables, it is eliminated)

(17, 19) – AB’C'E (Since D is the changing variables, it is eliminated)

(13, 29) – BCD’E (Since A is the changing variables, it is eliminated)

(8, 24) – BC’D'E’ (Since A is the changing variables, it is eliminated)

There is 1 in cell 30, which can not be looped with any adjacent cell, hence it can not be
simplified further and left as it is.

30 – ABCDE’

Thus, F = B’DE + A’C'DE + A’B'C’E’ + A’B'CE + AB’C'E + BCD’E + BC’D'E’ + ABCDE’

Author: Dr. Himanshu Gupta, Associate Professor, AIIT, Amity University, Noida Page 21
 Digital Electronics

K-Map for XOR and XNOR Gates

The truth table of XOR gate is given below,

The binary operation of above truth table is known as exclusive OR operation and it is
represented as, A ⊕ B. The symbol of exclusive OR operation is represented by a plus ring
surrounded by a circle ⊕.

XNOR gate is a NOT gate followed by an XOR gate. As we know that XOR operation of
inputs A and B is A ⊕ B, therefore XNOR operation those inputs will be complement of (A +
B). That means, output of XOR gate is inverted in XNOR gate.

The truth table of the XNOR gate is shown below,

The logical XNOR operation is represented by ⊙. That is a dot surrounded by circle. The
expression of XNOR operation between variable A and B is represented as A ⊙ B.

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 Digital Electronics

The XOR and XNOR of 4 variables A, B, C, D are similarly defined as:

Representation of both expressions using K-map can be illustrated as:

Author: Dr. Himanshu Gupta, Associate Professor, AIIT, Amity University, Noida Page 23