LTC1863/LTC1867

12-/16-Bit, 8-Channel
200ksps ADCs

Features Description
n Sample Rate: 200ksps The LTC®1863/LTC1867 are pin-compatible, 8-channel
n 16-Bit No Missing Codes and ±2LSB Max INL 12-/16-bit A/D converters with serial I/O, and an internal
n 8-Channel Multiplexer with: reference. The ADCs typically draw only 1.3mA from a
Single Ended or Differential Inputs and single 5V supply.
Unipolar or Bipolar Conversion Modes
n SPI/MICROWIRE™ Serial I/O
The 8-channel input multiplexer can be configured for
n Signal-to-Noise Ratio: 89dB
either single-ended or differential inputs and unipolar
or bipolar conversions (or combinations thereof). The
n Single 5V Operation
n On-Chip or External Reference
automatic nap and sleep modes benefit power sensitive
n Low Power: 1.3mA at 200ksps, 0.76mA at 100ksps
applications.
n Sleep Mode The LTC1867’s DC performance is outstanding with a
n Automatic Nap Mode Between Conversions ±2LSB INL specification and no missing codes over tem-
n 16-Pin Narrow SSOP Package perature. The signal-to-noise ratio (SNR) for the LTC1867
is typically 89dB, with the internal reference.

Applications Housed in a compact, narrow 16-pin SSOP package, the

LTC1863/LTC1867 can be used in space-sensitive as well
n Industrial Process Control as low-power applications.
n High Speed Data Acquisition L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
n Battery Operated Systems Technology Corporation. All other trademarks are the property of their respective owners.

n Multiplexed Data Acquisition Systems

n Imaging Systems

Block Diagram
Integral Nonlinearity vs Output Code
(LTC1867)
2.0

1 LTC1863/LTC1867 16 1.5
CH0 VDD
2 15
CH1 GND 1.0
3 14
CH2 SDI
4 13
CH3 ANALOG + 12-/16-BIT SERIAL SDO 0.5
5 200ksps 12
INL (LSB)

CH4 INPUT – PORT SCK

6 MUX ADC 11
CH5 CS/CONV 0
7 10
CH6 VREF
8 INTERNAL –0.5
CH7/COM
2.5V REF
–1.0
9
REFCOMP –1.5
18637 BD
–2.0
0 16384 32768 49152 65536
OUTPUT CODE
18637 GO1

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LTC1863/LTC1867
Absolute Maximum Ratings Pin Configuration
(Note 1, 2)
Supply Voltage (VDD).................................... –0.3V to 6V TOP VIEW
Analog Input Voltage
CH0 1 16 VDD
CH0-CH7/COM (Note 3)............– 0.3V to (VDD + 0.3V)
CH1 2 15 GND
VREF, REFCOMP (Note 4).......... –0.3V to (VDD + 0.3V)
CH2 3 14 SDI
Digital Input Voltage (SDI, SCK, CS/CONV)
CH3 4 13 SDO
(Note 4).................................................. –0.3V to 10V 12 SCK
CH4 5
Digital Output Voltage (SDO)........ –0.3V to (VDD + 0.3V) CH5 6 11 CS/CONV
Power Dissipation............................................... 500mW CH6 7 10 VREF
Operating Temperature Range CH7/COM 8 9 REFCOMP
LTC1863C/LTC1867C/LTC1867AC............. 0°C to 70°C
GN PACKAGE
LTC1863I/LTC1867I/LTC1867AI............–40°C to 85°C 16-LEAD NARROW PLASTIC SSOP
Storage Temperature Range................... –65°C to 150°C TJMAX = 110°C, θJA = 95°C/W
Lead Temperature (Soldering, 10 sec).................... 300°C

Order Information
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC1863CGN#PBF LTC1863CGN#TRPBF 1863 16-Lead Narrow Plastic SSOP 0°C to 70°C
LTC1863IGN#PBF LTC1863IGN#TRPBF 1863 16-Lead Narrow Plastic SSOP –40°C to 85°C
LTC1867CGN#PBF LTC1867CGN#TRPBF 1867 16-Lead Narrow Plastic SSOP 0°C to 70°C
LTC1867IGN#PBF LTC1867IGN#TRPBF 1867 16-Lead Narrow Plastic SSOP –40°C to 85°C
LTC1867ACGN#PBF LTC1867ACGN#TRPBF 1867 16-Lead Narrow Plastic SSOP 0°C to 70°C
LTC1867AIGN #PBF LTC1867AIGN#TRPBF 1867 16-Lead Narrow Plastic SSOP –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

Converter Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. With external reference (Notes 5, 6)
LTC1863 LTC1867 LTC1867A
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
Resolution l 12 16 16 Bits
No Missing Codes l 12 15 16 Bits
Integral Linearity Error Unipolar (Note 7) l ±1 ±4 ±2 LSB
Bipolar l ±1 ±4 ±2.5 LSB
Differential Linearity Error l ±1 –2 3 –1 1.75 LSB
Transition Noise 0.1 0.74 0.74 LSBRMS
Offset Error Unipolar (Note 8) l ±3 ±32 ±32 LSB
Bipolar l ±4 ±64 ±64 LSB
Offset Error Match Unipolar ±1 ±2 ±2 LSB
Bipolar ±1 ±2 ±2 LSB

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 LTC1863/LTC1867
CONVERTER Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. With external reference (Notes 5, 6)
LTC1863 LTC1867 LTC1867A
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
Offset Error Drift ±0.5 ±0.5 ±0.5 ppm/°C
Gain Error Unipolar ±6 ±96 ±64 LSB
Bipolar ±6 ±96 ±64 LSB
Gain Error Match ±1 ±4 ±2 LSB
Gain Error Tempco Internal Reference ±15 ±15 ±15 ppm/°C
External Reference ±2.7 ±2.7 ±2.7 ppm/°C
Power Supply Sensitivity VDD = 4.75V – 5.25V ±1 ±5 ±5 LSB

Dynamic Accuracy (Note 5)

LTC1863 LTC1867/LTC1867A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
SNR Signal-to-Noise Ratio 1kHz Input Signal 73.6 89 dB
S/(N+D) Signal-to-(Noise + Distortion) Ratio 1kHz Input Signal 73.5 88 dB
THD Total Harmonic Distortion 1kHz Input Signal, Up to 5th Harmonic –94.5 –95 dB
Peak Harmonic or Spurious Noise 1kHz Input Signal –94.5 –95 dB
Channel-to-Channel Isolation 100kHz Input Signal –100 –117 dB
Full Power Bandwidth –3dB Point 1.25 1.25 MHz

Analog Input The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
LTC1863/LTC1867/LTC1867A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Analog Input Range Unipolar Mode (Note 9) l 0-4.096 V
Bipolar Mode l ±2.048 V
CIN Analog Input Capacitance for CH0 to Between Conversions (Sample Mode) 32 pF
CH7/COM During Conversions (Hold Mode) 4 pF
tACQ Sample-and-Hold Acquisition Time l 1.5 1.1 µs
Input Leakage Current On Channels, CHX = 0V or VDD l ±1 µA

Internal Reference Characteristics

(Note 5)
LTC1863/LTC1867/LTC1867A
PARAMETER CONDITIONS MIN TYP MAX UNITS
VREF Output Voltage IOUT = 0 2.48 2.5 2.52 V
VREF Output Tempco IOUT = 0 ±15 ppm/°C
VREF Line Regulation 4.75V ≤ VDD ≤ 5.25V 0.43 mV/V
VREF Output Resistance IOUT  ≤0.1mA 6 kΩ
REFCOMP Output Voltage IOUT = 0 4.096 V

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LTC1863/LTC1867
Digital Inputs and Digital Outputs The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
LTC1863/LTC1867/LTC1867A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage VDD = 5.25V l 2.4 V
VIL Low Level Input Voltage VDD = 4.75V l 0.8 V
IIN Digital Input Current VIN = 0V to VDD l ±10 µA
CIN Digital Input Capacitance 2 pF
VOH High Level Output Voltage (SDO) VDD = 4.75V, IO = –10µA 4.75 V
VDD = 4.75V, IO = –200µA l 4 4.74 V
VOL Low Level Output Voltage (SDO) VDD = 4.75V, IO = 160µA 0.05 V
VDD = 4.75V, IO = 1.6mA l 0.1 0.4 V
ISOURCE Output Source Current SDO = 0V –32 mA
ISINK Output Sink Current SDO = VDD 19 mA
Hi-Z Output Leakage CS/CONV = High, SDO = 0V or VDD l ±10 µA
Hi-Z Output Capacitance CS/CONV = High (Note 10) l 15 pF
Data Format Unipolar Straight Binary
Bipolar Two’s Complement

Power Requirements The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
LTC1863/LTC1867/LTC1867A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage (Note 9) 4.75 5.25 V
IDD Supply Current fSAMPLE = 200ksps l 1.3 1.8 mA
NAP Mode 150 µA
SLEEP Mode l 0.2 3 µA
PDISS Power Dissipation l 6.5 9 mW

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 LTC1863/LTC1867
Timing Characteristics The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
LTC1863/LTC1867/LTC1867A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE Maximum Sampling Frequency l 200 kHz
tCONV Conversion Time l 3 3.5 µs
tACQ Acquisition Time l 1.5 1.1 µs
fSCK SCK Frequency 40 MHz
t1 CS/CONV High Time Short CS/CONV Pulse Mode l 40 100 ns
t2 SDO Valid After SCK↓ CL = 25pF (Note 11) l 13 22 ns
t3 SDO Valid Hold Time After SCK↓ CL = 25pF l 5 11 ns
t4 SDO Valid After CS/CONV↓ CL = 25pF l 10 30 ns
t5 SDI Setup Time Before SCK↑ l 15 –6 ns
t6 SDI Hold Time After SCK↑ l 10 4 ns
t7 SLEEP Mode Wake-Up Time CREFCOMP = 10µF, CVREF = 2.2µF 60 ms
t8 Bus Relinquish Time After CS/CONV↑ CL = 25pF l 20 40 ns

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 7: Integral nonlinearity is defined as the deviation of a code from a
may cause permanent damage to the device. Exposure to any Absolute straight line passing through the actual endpoints of the transfer curve.
Maximum Rating condition for extended periods may affect device The deviation is measured from the center of the quantization band.
reliability and lifetime Note 8: Unipolar offset is the offset voltage measured from +1/2LSB
Note 2: All voltage values are with respect to GND (unless otherwise noted). when the output code flickers between 0000 0000 0000 0000 and
Note 3: When these pin voltages are taken below GND or above VDD, they 0000 0000 0000 0001 for LTC1867 and between 0000 0000 0000 and
will be clamped by internal diodes. This product can handle input currents 0000 0000 0001 for LTC1863. Bipolar offset is the offset voltage measured
of greater than 100mA without latchup. from –1/2LSB when output code flickers between 0000 0000 0000 0000
Note 4: When these pin voltages are taken below GND, they will be and 1111 1111 1111 1111 for LTC1867, and between
clamped by internal diodes. This product can handle input currents of 0000 0000 0000 and 1111 1111 1111 for LTC1863.
greater than 100mA below GND without latchup. These pins are not Note 9: Recommended operating conditions. The input range of ±2.048V
clamped to VDD. for bipolar mode is measured with respect to VIN– = 2.5V.
Note 5: VDD = 5V, fSAMPLE = 200ksps at 25°C, t r = tf = 5ns and Note 10: Guaranteed by design, not subject to test.
VIN– = 2.5V for bipolar mode unless otherwise specified. Note 11: t2 of 25ns maximum allows fSCK up to 20MHz for rising capture
Note 6: Linearity, offset and gain error specifications apply for both with 50% duty cycle and fSCK up to 40MHz for falling capture (with 3ns
unipolar and bipolar modes. The INL and DNL are tested in bipolar mode. setup time for the receiving logic).

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LTC1863/LTC1867
Typical Performance Characteristics
(LTC1867)
Integral Nonlinearity vs Differential Nonlinearity vs
Output Code Output Code Histogram for 4096 Conversions
2.0 2.0 2500

1.5 2152
1.5
2000
1.0 1.0

0.5 0.5
1500

DNL (LSB)
INL (LBS)

COUNTS
0 0
1000 935
– 0.5 –0.5

– 1.0 –1.0 579

500
– 1.5 –1.5 276
122
1 26 5 0
– 2.0 –2.0 0
0 16384 32768 49152 65536 0 16384 32768 49152 65536 –4 –3 –2 –1 0 1 2 3 4
OUTPUT CODE OUTPUT CODE CODE
18637 GO1 18637 GO2 18637 GO3

4096 Points FFT Plot (fIN = 1kHz,

4096 Points FFT Plot (fIN = 1kHz) REFCOMP = External 5V) Crosstalk vs Input Frequency
0 0 –80
SNR = 88.8dB SNR = 90dB
SINAD = 87.9dB SINAD = 88.5dB
–20 –20 –90
THD = 95dB THD = 94dB
fSAMPLE = 200ksps fSAMPLE = 200ksps
RESULTING AMPLITUDE ON
SELECTED CHANNEL (dB)
–40 INTERNAL REFERENCE –40 VREF = 0V
–100
AMPLITUDE (dB)

AMPLITUDE (dB)

REFCOMP = EXT 5V
–60 –60
–110 ADJACENT PAIR
–80 –80
–120
–100 –100
NONADJACENT PAIR

–120 –120 –130

–140 –140 –140

0 25 50 75 100 0 25 50 75 100 1 10 100 1000
FREQUENCY (kHz) FREQUENCY (kHz) ACTIVE CHANNEL INPUT FREQUENCY (kHz)
18637 G04 18637 G05 18637 G06

Signal-to-Noise Ratio vs Signal-to-(Noise + Distortion) vs Total Harmonic Distortion vs

Frequency Input Frequency Input Frequency
100 100 –20

90 90 –30

80 80 –40
AMPLITUDE (dB)

AMPLITUDE (dB)

AMPLITUDE (dB)

70 70 –50

60 60 –60

50 50 –70

40 40 –80

30 30 –90

20 20 –100
1 10 100 1 10 100 1 10 100
INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz)
18637 G07 18637 G08 18637 G09

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 LTC1863/LTC1867
Typical Performance Characteristics
(LTC1863/LTC1867)

Supply Current vs fSAMPLE Supply Current vs Supply Voltage Supply Current vs Temperature
2.0 1.5 1.5
VDD = 5V VDD = 5V VDD = 5V
fSAMPLE = 200ksps fSAMPLE = 200ksps
1.4 1.4
1.5
SUPPLY CURRENT (mA)

SUPPLY CURRENT (mA)

SUPPLY CURRENT (mA)
1.3 1.3
1.0

1.2 1.2

0.5
1.1 1.1

0 1.0 1.0
1 10 100 1000 4.5 4.75 5.0 5.25 5.5 –50 –25 0 25 50 75 100
fSAMPLE (ksps) SUPPLY VOLTAGE (V) TEMPERATURE (°C)
18637 G10 18637 G11 18637 G12

Integral Nonlinearity vs Output Differential Nonlinearity vs

Code (LTC1863) Output Code (LTC1863)
1.0 1.0

0.8 0.8

0.6 0.6

0.4 0.4

0.2 0.2
DNL (LBS)
INL (LBS)

0 0

–0.2 –0.2

–0.4 –0.4

–0.6 –0.6

–0.8 –0.8

–1.0 –1.0
0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE OUTPUT CODE
18637 G13 18637 G14

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LTC1863/LTC1867
Pin Functions
CHO-CH7/COM (Pins 1-8): Analog Input Pins. Analog SCK (Pin 12): Shift Clock. This clock synchronizes the
inputs must be free of noise with respect to GND. CH7/ serial data transfer.
COM can be either a separate channel or the common
SDO (Pin 13): Digital Data Output. The A/D conversion
minus input for the other channels.
result is shifted out of this output. Straight binary format
REFCOMP (Pin 9): Reference Buffer Output Pin. Bypass for unipolar mode and two’s complement format for
to GND with 10µF tantalum capacitor in parallel with bipolar mode.
0.1µF ceramic capacitor (4.096V Nominal). To overdrive
SDI (Pin 14): Digital Data Input Pin. The A/D configuration
REFCOMP, tie VREF to GND.
word is shifted into this input.
VREF (Pin 10): 2.5V Reference Output. This pin can also
GND (Pin 15): Analog and Digital GND.
be used as an external reference buffer input for improved
accuracy and drift. Bypass to GND with 2.2µF tantalum VDD (Pin 16): Analog and Digital Power Supply. Bypass to
capacitor in parallel with 0.1µF ceramic capacitor. GND with 10µF tantalum capacitor in parallel with 0.1µF
ceramic capacitor.
CS/CONV (Pin 11): This input provides the dual function
of initiating conversions on the ADC and also frames the
serial data transfer.

Typical Connection Diagram

±2.048V + CH0 VDD 5V
DIFFERENTIAL
INPUTS – CH1 GND

CH2 SDI

LTC1863/
CH3 SDO
LTC1867 DIGITAL
4.096V I/O
SINGLE-ENDED + CH4 SCK
INPUT
CH5 CS/CONV

CH6 VREF 2.5V

2.2µF
CH7/COM REFCOMP 4.096V
10µF
18637 TCD

Test Circuits
Load Circuits for Access Timing Load Circuits for Output Float Delay
5V 5V

3k 3k

DN DN DN DN

3k CL CL 3k CL CL

(A) Hi-Z TO VOH AND VOL TO VOH (B) Hi-Z TO VOL AND VOH TO VOL (A) VOH TO Hi-Z (B) VOL TO Hi-Z
18637 TC01 18637 TC02

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 LTC1863/LTC1867
Timing Diagrams
t1 (For Short Pulse Mode) t2 (SDO Valid Before SCK↑),
t1
t3 (SDO Valid Hold Time After SCK↓)
t2

CS/CONV 50% 50%

SCK 0.4V
t3

2.4V
SDO
0.4V

t5 (SDI Setup Time Before SCK↑),

t4 (SDO Valid After CONV↓) t6 (SDI Hold Time After SCK↑)
t4 t5 t6

2.4V
CS/CONV SCK
0.4V

Hi-Z 2.4V 2.4V 2.4V

SDO SDI
0.4V 0.4V 0.4V

t7 (SLEEP Mode Wake-Up Time) t8 (BUS Relinquish Time)

t7 t8

2.4V
SCK 50% CS/CONV

SLEEP BIT (SLP = 0)

READ-IN
90% Hi-Z
CS/CONV 50% SDO
10% 1867 TD

Applications Information
Overview
The LTC1863/LTC1867 are complete, low power multi- During the conversion, the internal differential 16-bit
plexed ADCs. They consist of a 12-/16-bit, 200ksps capaci- capacitive DAC output is sequenced by the SAR from
tive successive approximation A/D converter, a precision the most significant bit (MSB) to the least significant bit
internal reference, a configurable 8-channel analog input (LSB). The input is successively compared with the binary
multiplexer (MUX) and a serial port for data transfer. weighted charges supplied by the differential capacitive
Conversions are started by a rising edge on the CS/CONV DAC. Bit decisions are made by a low-power, differential
input. Once a conversion cycle has begun, it cannot be comparator. At the end of a conversion, the DAC output
restarted. Between conversions, the ADCs receive an input balances the analog input. The SAR contents (a 12-/16-bit
word for channel selection and output the conversion data word) that represent the analog input are loaded into
result, and the analog input is acquired in preparation for the 12-/16-bit output latches.
the next conversion. In the acquire phase, a minimum time
of 1.5µs will provide enough time for the sample-and-hold
capacitors to acquire the analog signal.
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LTC1863/LTC1867
Applications Information
Analog Input Multiplexer Changing the MUX Assignment “On the Fly”
1st Conversion 2nd Conversion
The analog input multiplexer is controlled by a 7-bit input
data word. The input data word is defined as follows:
+ –
–{
CH2
SD OS S1 S0 COM UNI SLP CH3 + { CH2
CH3

SD = SINGLE/DIFFERENTIAL BIT + CH4 + CH4

–{ CH5 + { CH5

OS = ODD/SIGN BIT CH7/COM

(UNUSED)
CH7/COM (–)

S1 = ADDRESS SELECT BIT 1 18637 AI02

S0 = ADDRESS SELECT BIT 0 Tables 1 and 2 show the configurations when COM = 0,
COM = CH7/COM CONFIGURATION BIT and COM = 1.
UNI = UNIPOLAR/BIPOLAR BIT Table 1. Channel Configuration (When COM = 0, CH7/COM Pin
Is Used as CH7)
SLP = SLEEP MODE BIT Channel Configuration
SD OS S1 S0 COM “+” “–”
0 0 0 0 0 CH0 CH1
Examples of Multiplexer Options
0 0 0 1 0 CH2 CH3
4 Differential 8 Single-Ended 0 0 1 0 0 CH4 CH5
+ (–) CH0 + CH0 0 0 1 1 0 CH6 CH7
– (+) { CH1 + CH1
+ CH2 0 1 0 0 0 CH1 CH0
+ (–) CH2 +
– (+) {
CH3 0 1 0 1 0 CH3 CH2
CH3 + CH4
+ CH5 0 1 1 0 0 CH5 CH4
+ (–) CH4
– (+) { CH5 + CH6
0 1 1 1 0 CH7 CH6
+ CH7/COM
+ (–) CH6 1 0 0 0 0 CH0 GND
– (+) { CH7/COM GND (–)
1 0 0 1 0 CH2 GND
1 0 1 0 0 CH4 GND
7 Single-Ended Combinations of Differential 1 0 1 1 0 CH6 GND
to CH7/COM and Single-Ended
1 1 0 0 0 CH1 GND
+ CH0 + CH0
–{
1 1 0 1 0 CH3 GND
+ CH1 CH1
+ CH2 1 1 1 0 0 CH5 GND
+ – CH2
+{
CH3
CH3 1 1 1 1 0 CH7 GND
+ CH4
+ CH5 + CH4
+ CH6 + CH5 Table 2. Channel Configuration (When COM = 1, CH7/COM Pin
+ CH6 Is Used as COMMON)
+ CH7/COM
CH7/COM (–) GND (–) Channel Configuration
18637 AI01 SD OS S1 S0 COM “+” “–”
1 0 0 0 1 CH0 CH7/COM
1 0 0 1 1 CH2 CH7/COM
1 0 1 0 1 CH4 CH7/COM
1 0 1 1 1 CH6 CH7/COM
1 1 0 0 1 CH1 CH7/COM
1 1 0 1 1 CH3 CH7/COM
1 1 1 0 1 CH5 CH7/COM
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 LTC1863/LTC1867
Applications Information
Driving the Analog Inputs LT1360 - 37MHz voltage feedback amplifier. 3.8mA supply
The analog inputs of the LTC1863/LTC1867 are easy to current. ±5V to ±15V supplies. Good AC/DC specs.
drive. Each of the analog inputs can be used as a single- LT1363 - 50MHz voltage feedback amplifier. 6.3mA supply
ended input relative to the GND pin (CH0-GND, CH1-GND, current. Good AC/DC specs.
etc) or in pairs (CH0 and CH1, CH2 and CH3, CH4 and CH5,
LT1364/LT1365 - Dual and quad 50MHz voltage feedback
CH6 and CH7) for differential inputs. In addition, CH7 can
amplifiers. 6.3mA supply current per amplifier. Good
act as a COM pin for both single-ended and differential AC/DC specs.
modes if the COM bit in the input word is high. Regard-
less of the MUX configuration, the “+” and “–” inputs are LT1468 - 90MHz, 22V/µs 16-bit accurate amplifier
sampled at the same instant. Any unwanted signal that is LT1469 - Dual LT1468
common mode to both inputs will be reduced by the com-
mon mode rejection of the sample-and-hold circuit. The Input Filtering
inputs draw only one small current spike while charging
the sample-and-hold capacitors during the acquire mode. The noise and the distortion of the input amplifier and
In conversion mode, the analog inputs draw only a small other circuitry must be considered since they will add to
leakage current. If the source impedance of the driving the LTC1863/LTC1867 noise and distortion. Noisy input
circuit is low then the LTC1863/LTC1867 inputs can be circuitry should be filtered prior to the analog inputs to
driven directly. More acquisition time should be allowed minimize noise. A simple 1-pole RC filter is sufficient for
for a higher impedance source. many applications. For instance, Figure 1 shows a 50Ω
source resistor and a 2000pF capacitor to ground on the
The following list is a summary of the op amps that are input will limit the input bandwidth to 1.6MHz. The source
suitable for driving the LTC1863/LTC1867. More detailed impedance has to be kept low to avoid gain error and
information is available in the Linear Technology data books degradation in the AC performance. The capacitor also
or Linear Technology website. acts as a charge reservoir for the input sample-and-hold
LT1007 - Low noise precision amplifier. 2.7mA supply and isolates the ADC input from sampling glitch sensitive
current ± 5V to ±15V supplies. Gain bandwidth product circuitry. High quality capacitors and resistors should be
8MHz. DC applications. used since these components can add distortion. NPO
and silver mica type dielectric capacitors have excellent
LT1097 - Low cost, low power precision amplifier. 300µA linearity. Carbon surface mount resistors can also generate
supply current. ±5V to ± 15V supplies. Gain bandwidth distortion from self heating and from damage that may
product 0.7MHz. DC applications. occur during soldering. Metal film surface mount resistors
LT1227 - 140MHz video current feedback amplifier. 10mA are much less susceptible to both problems.
supply current. ±5V to ±15V supplies. Low noise and low
distortion.

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LTC1863/LTC1867
Applications Information
ANALOG 50Ω Dynamic Performance
CH0
INPUT
2000pF LTC1863/ FFT (Fast Fourier Transform) test techniques are used to
LTC1867
GND test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion
REFCOMP
sine wave and analyzing the digital output using an FFT
10µF
1867 F01a
algorithm, the ADC’s spectral content can be examined
for frequencies outside the fundamental.
Figure 1a. Optional RC Input Filtering for Single-Ended Input
Signal-to-Noise Ratio
The Signal-to-Noise and Distortion Ratio (SINAD) is the
1000pF ratio between the RMS amplitude of the fundamental input
50Ω
CH0 frequency to the RMS amplitude of all other frequency
DIFFERENTIAL
ANALOG 1000pF LTC1863/ components at the A/D output. The output is band limited
INPUTS 50Ω LTC1867
CH1 to frequencies from above DC and below half the sampling
1000pF frequency. Figure 3 shows a typical SINAD of 87.9dB
REFCOMP
with a 200kHz sampling rate and a 1kHz input. When an
10µF
1867 F01b
external 5V is applied to REFCOMP (tie VREF to GND), a
signal-to-noise ratio of 90dB can be achieved.
Figure 1b. Optional RC Input Filtering for Differential Inputs
0
SNR = 88.8dB
SINAD = 87.9dB
–20
DC Performance THD = 95dB
fSAMPLE = 200ksps
–40 INTERNAL REFERENCE
One way of measuring the transition noise associated
AMPLITUDE (dB)

with a high resolution ADC is to use a technique where –60

a DC signal is applied to the input of the ADC and the –80

resulting output codes are collected over a large number
–100
of conversions. For example, in Figure 2 the distribution
of output codes is shown for a DC input that had been –120

digitized 4096 times. The distribution is Gaussian and the –140

RMS code transition noise is about 0.74LSB. 0 25 50 75 100
FREQUENCY (kHz)
2500 18637 G04

2152
Figure 3. LTC1867 Nonaveraged 4096 Point FFT Plot
2000

1500
Total Harmonic Distortion
COUNTS

Total Harmonic Distortion (THD) is the ratio of the RMS

1000 935
sum of all harmonics of the input signal to the fundamental
579 itself. The out-of-band harmonics alias into the frequency
500
276 band between DC and half the sampling frequency. THD
1 26
122
5 0 is expressed as:
0
–4 –3 –2 –1 0 1 2 3 4
CODE V2 2 + V3 2 + V4 2 ...+ VN 2
THD = 20log
V1
18637 GO3

Figure 2. LTC1867 Histogram for 4096 Conversions

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12 For more information www.linear.com/LTC1863

 LTC1863/LTC1867
Applications Information
where V1 is the RMS amplitude of the fundamental fre- Digital Interface
quency and V2 through VN are the amplitudes of the second The LTC1863/LTC1867 have a very simple digital interface
through Nth harmonics. that is enabled by the control input, CS/CONV. A logic rising
edge applied to the CS/CONV input will initiate a conversion.
Internal Reference
After the conversion, taking CS/CONV low will enable the
The LTC1863/LTC1867 has an on-chip, temperature serial port and the ADC will present digital data in two’s
compensated, curvature corrected, bandgap reference complement format in bipolar mode or straight binary
that is factory trimmed to 2.5V. It is internally connected format in unipolar mode, through the SCK/SDO serial port.
to a reference amplifier and is available at VREF (Pin 10).
A 6k resistor is in series with the output so that it can be Internal Clock
easily overdriven by an external reference if better drift The internal clock is factory trimmed to achieve a typical
and/or accuracy are required as shown in Figure 4. The conversion time of 3µs and a maximum conversion time,
reference amplifier gains the VREF voltage by 1.638V/V 3.5µs, over the full operating temperature range. The typi-
to 4.096V at REFCOMP (Pin 9). This reference amplifier cal acquisition time is 1.1µs, and a throughput sampling
compensation pin, REFCOMP, must be bypassed with a rate of 200ksps is tested and guaranteed.
10µF ceramic or tantalum in parallel with a 0.1µF ceramic
for best noise performance. Automatic Nap Mode

R1
The LTC1863/LTC1867 go into automatic nap mode when
2.5V
10 VREF 6k BANDGAP CS/CONV is held high after the conversion is complete
REFERENCE
(see Figure 6). With a typical operating current of 1.3mA
2.2µF
and automatic 150µA nap mode between conversions, the
4.096V
9 REFCOMP REFERENCE power dissipation drops with reduced sample rate. The
AMP
ADC only keeps the VREF and REFCOMP voltages active
10µF
when the part is in the automatic nap mode. The slower the
R2
sample rate allows the power dissipation to be lower (see
15 GND R3 Figure 5).
LTC1863/LTC1867
1867 F04a

2.0
Figure 4a. LTC1867 Reference Circuit VDD = 5V

5V 1.5
SUPPLY CURRENT (mA)

VIN

LT1019A-2.5 1.0
10
VOUT VREF
2.2µF LTC1863/
LTC1867
9 0.5
REFCOMP
+
10µF 0.1µF
15 0
GND
1 10 100 1000
1867 F04b fSAMPLE (ksps)
18637 G10

Figure 4b. Using the LT1019-2.5 as an External Reference

Figure 5. Supply Current vs fSAMPLE

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For more information www.linear.com/LTC1863 13

LTC1863/LTC1867
Applications Information
If the CS/CONV returns low during a bit decision, it can of the common return for these bypass capacitors is es-
create a small error. For best performance ensure that sential to the low noise operation of the ADC. The width
the CS/CONV returns low either within 100ns after the for these tracks should be as wide as possible.
conversion starts (i.e. before the first bit decision) or
after the conversion ends. If CS/CONV is low when the Timing and Control
conversion ends, the MSB bit will appear on SDO at the Conversion start is controlled by the CS/CONV digital in-
end of the conversion and the ADC will remain powered put. The rising edge transition of the CS/CONV will start a
up (see Figure 7). conversion. Once initiated, it cannot be restarted until the
conversion is complete. Figures 6 and 7 show the timing
Sleep Mode
diagrams for two types of CS/CONV pulses.
If the SLP = 1 is selected in the input word, the ADC
Example 1 (Figure 6) shows the LTC1863/LTC1867 operat-
will enter SLEEP mode and draw only leakage current
ing in automatic nap mode with CS/CONV signal staying
(provided that all the digital inputs stay at GND or VDD).
HIGH after the conversion. Automatic nap mode provides
After release from the SLEEP mode, the ADC need 60ms
power reduction at reduced sample rate. The ADCs can also
to wake up (2.2µF/10µF bypass capacitors on VREF/
operate with the CS/CONV signal returning LOW before
REFCOMP pins).
the conversion ends. In this mode (Example 2, Figure 7),
Board Layout and Bypassing the ADCs remain powered up.

To obtain the best performance, a printed circuit board For best performance, it is recommended to keep SCK, SDI,
with a ground plane is required. Layout for the printed and SDO at a constant logic high or low during acquisition
circuit board should ensure digital and analog signal lines and conversion, even though these signals may be ignored
are separated as much as possible. In particular, care by the serial interface (DON’T CARE). Communication
should be taken not to run any digital signal alongside with other devices on the bus should not coincide with
an analog signal. the conversion period (tCONV).

All analog inputs should be screened by GND. VREF, Figures 8 and 9 are the transfer characteristics for the
REFCOMP and VDD should be bypassed to this ground bipolar and unipolar mode.
plane as close to the pin as possible; the low impedance

tACQ

1/fSCK
CS/CONV
tCONV NAP MODE
NOT NEEDED FOR LTC1863
SCK DON'T CARE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DON'T CARE

SDI DON'T CARE SD 0S S1 S0 COM UNI SLP DON'T CARE

Hi-Z MSB
SDO D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(LTC1863)
Hi-Z MSB
SDO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(LTC1867) 1867 F06

Figure 6. Example 1, CS/CONV Starts a Conversion and Remains HIGH Until Next Data Transfer. With CS/CONV Remaining HIGH After
the Conversion, Automatic Nap Modes Provides Power Reduction at Reduced Sample Rate.

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14 For more information www.linear.com/LTC1863

 LTC1863/LTC1867
Applications Information

CS/CONV tACQ
NOT NEEDED FOR LTC1863

SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DON'T CARE

SDI DON'T CARE SD 0S S1 S0 COM UNI SLP DON'T CARE

tCONV
SDO MSB = D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(LTC1863) Hi-Z
tCONV
SDO MSB = D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(LTC1867) Hi-Z 1867 F07

Figure 7. Example 2, CS/CONV Starts a Conversion With Short Active HIGH Pulse.
With CS/CONV Returning LOW Before the Conversion, the ADC Remains Powered Up.

011...111 111...111
OUTPUT CODE (TWO’S COMPLEMENT)

011...110 BIPOLAR 111...110

ZERO

100...001
OUTPUT CODE
000...001
000...000 100...000

111...111 011...111 UNIPOLAR

ZERO
111...110 011...110

FS = 4.096 FS = 4.096
100...001 1LSB = FS/2n
000...001 1LSB = FS/2n
1LSB = (LTC1863) = 1mV 000...000 1LSB = (LTC1863) = 1mV
100...000 1LSB = (LTC1867) = 62.5µV
1LSB = (LTC1867) = 62.5µV

–FS/2 –1 0V 1 FS/2 – 1LSB 0V FS – 1LSB

LSB LSB
INPUT VOLTAGE (V) INPUT VOLTAGE (V)
1867 F08 1867 F09

Figure 8. LTC1863/LTC1867 Bipolar Transfer Figure 9. LTC1863/LTC1867 Unipolar Transfer

Characteristics (Two’s Complement) Characteristics (Straight Binary)

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For more information www.linear.com/LTC1863 15

LTC1863/LTC1867
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

GN Package
16-Lead Plastic
GNSSOP (Narrow .150 Inch)
Package
(Reference LTC DWG # 05-08-1641 Rev B)
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)

.045 ±.005 .189 – .196*

(4.801 – 4.978)
.009
(0.229)
16 15 14 13 12 11 10 9 REF

.254 MIN .150 – .165

.229 – .244 .150 – .157**

(5.817 – 6.198) (3.810 – 3.988)

.0165 ±.0015 .0250 BSC

RECOMMENDED SOLDER PAD LAYOUT
1 2 3 4 5 6 7 8

.015 ±.004
× 45° .0532 – .0688 .004 – .0098
(0.38 ±0.10)
(1.35 – 1.75) (0.102 – 0.249)
.007 – .0098
0° – 8° TYP
(0.178 – 0.249)

.016 – .050 .008 – .012 .0250

(0.406 – 1.270) (0.203 – 0.305) (0.635) GN16 REV B 0212

NOTE: TYP BSC

1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

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16 For more information www.linear.com/LTC1863

 LTC1863/LTC1867
Revision History (Revision history begins at Rev B)

REV DATE DESCRIPTION PAGE NUMBER

B 6/14 Fixed the Order Information. 2

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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
For more
tion that the interconnection information
of its circuits www.linear.com/LTC1863
as described herein will not infringe on existing patent rights. 17
LTC1863/LTC1867
Related Parts
PART NUMBER DESCRIPTION COMMENTS
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LTC1864/LTC1865 16-Bit, 1-/2-Channel 250ksps ADC in MSOP 850µA at 250ksps, 2µA at 1ksps, SO-8 and MSOP Packages
LTC1864L/LTC1865L 3V, 16-Bit, 1-/2-Channel 150ksps ADC in MSOP 450µA at 150ksps, 10µA at 1ksps, SO-8 and MSOP Packages

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18 Linear Technology Corporation

LT 0614 REV B • PRINTED IN USA

1630 McCarthy Blvd., Milpitas, CA 95035-7417

For more information www.linear.com/LTC1863
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC1863  LINEAR TECHNOLOGY CORPORATION 2008