15011A0423 Page No: 1

J.N.T.U.H. COLLEGE OF ENGINEERING

KUKATPALLY, HYDERABAD-500 085

Certificate
Certified that this is the bonafide record of the practical work done during
the academic year 2018-2019 by

Name Japala Navya _____________________________________________________

Roll Number 15011A0423 Class IVth B-Tech E.C.E. (Reg)_____

in the Laboratory of VLSI and e-CAD ________________________
of the Department of Electronics And Communication Engineering______________

Signature of the Staff Member Signature of the Head of the Department

Date of Examination ___________________

Signature of the Examiner/s

Internal Examiner External Examiner

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15011A0423 Page No: 2

J.N.T.U.H. COLLEGE OF ENGINEERING

KUKATPALLY, HYDERABAD-500 085

Name Japala Navya Roll Number 15011A0423_______

Class E.C.E. (Reg) Year 2018-2019 Laboratory VLSI and e-CAD_______

List of Experiments
S.No. Name of the Date of Page Marks Remarks
Experiment Experiment Number
1. Design of half adder 08-08-18 03

2. Design of fuller adder 08-08-18 07

3. 3 – 8 Decoders 22-08-18 12
4. 8 – 3 Encoders 22-08-18 19
5. 8 – 1 Multiplexer 22-08-18 22
6. 1 – 4 De-Multiplexer 29-08-18 27
7. JK Flip flop 19-09-18 33
8. D Flip flop 19-09-18 36
9. SR Flip flop 19-09-18 39
10. T Flip flop 19-09-18 42
11. 4- bit Comparator 29-08-18 45
12. Binary to Gray convertor 29-08-18 49
13. CMOS NOT Gate 10-10-18 52

14. CMOS NAND Gate 10-10-18 54

15. CMOS NOR Gate 10-10-18 57

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1. DESIGN OF HALF ADDER

AIM:
To write Verilog code for half adder and simulate the results using gate level,data
flow and behavior model.
APPARATUS:
XILINX’S Vivado
THEORY:
A combinational circuit that performs the addition of two bits is called a half-adder.
This circuit needs two binary inputs and produces two binary outputs. One of the
input variables designates the augend and other is the addend. . The output variables
produce the sum and the carry. The simplified Boolean functions of the two outputs
can be obtained as below:
Sum S = x^y
Carry C = x.y
Where x, y are the two input variables.
CODE:
Gatelevel:
module hagl(a,b,c,s);
input a,b;
output c,s;
xor(s,a,b);
and(c,a,b);
endmodule

Dataflow Model:
module hadf(a,b,c,s);
input a,b;
output c,s;
assign{c,s}=a+b;

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endmodule

Behaviour model:
module habm(a,c,s);
input [1:0]a;
output reg c,s;
always@(a)
begin
case(a)
2'b00:
begin
c=0;
s=0;
end
2'b01:
begin
c=0;
s=1;
end
2'b10:
begin
c=0;
s=1;
end
2'b11:
begin
c=1;
s=0;
end
endcase
end
endmodule

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TESTBENCH:
Gate level:
module hagl_tb;
reg a,b;
wire c,s;
hagl h(a,b,c,s);
initial
begin
a=0;b=0;
#10;
a=0;b=1;
#20;
a=1;b=0;
#30;
a=1;b=1;
#40;
end
endmodule

Data flow model:

module hadf_tb;
reg a,b;
wire c,s;
hadf h1(a,b,c,s);
initial
begin
a=0;b=0;
#10;
a=0;b=1;
#20;
a=1;b=0;
#30;
a=1;b=1;
#40;
end
endmodule

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Behavioral model:
module habm_tb;
reg [1:0]a;
wire c,s;
habm h1(a,c,s);
initial
begin
a=2'b00;
#10;
a=2'b01;
#20;
a=2'b10;
#30;
a=2'b11;
#40;
end
endmodule

OUTPUT WAVEFORMS:

RESULT:
Hence, Half adder is designed in Gate level, dataflow model and behavior model and
results are simulated.

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2. DESIGN OF FULL ADDER

AIM:
To write Verilog code for full adder and simulate the results using gate level,data
flow and behavior model.
APPARATUS:
XILINX’S Vivado
THEORY:
A combinational circuit that performs the addition of three bits is called a full-adder.
This circuit needs three binary inputs and produces two binary outputs. One of the
input variables designates the augend and other designates the addend. Mostly, the
third input represents the carry from the previous lower significant position. The
output variables produce the sum and the carry. The simplified Boolean functions of
the two outputs can be obtained as below:
Sum S = x^y^z
Carry C = xy + xz + yz
Where x, y & z are the three input variables.
CODE:
Gate level:
module fagl(a,b,c,c0,s);
input a,b,c;
output c0,s;
wire x,y,z;
and(x,a,b);
and(y,b,c);
and(z,c,a);
xor(s,a,b,c);
or(c0,x,y,z);
endmodule

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Data flow model:

module fa(a,b,c,co,s);
input a,b,c;
output co,s;
assign {co,s}=a+b+c;
endmodule

Behavioural Model:

module fa1(a,s,c);
input [2:0]a;
output reg s,c;
always@(a)
begin
case(a)
3'b000:
begin
s=0;
c=0;
end
3'b001:
begin
s=1;
c=0;
end
3'b010:
begin
s=1;
c=0;
end
3'b011:
begin
s=0;
c=1;
end
3'b100:
begin

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s=1;
c=0;
end
3'b110:
begin
s=0;
c=1;
end
3'b101:
begin
s=0;
c=1;
end
3'b111:
begin
s=1;
c=1;
end
endcase
end
endmodule

TSET BENCH

Gate level:

module fagl_tb;
reg a,b,c;
wire s,c0;
fagl f1(a,b,c,c0,s);
initial
begin
a=0;b=0;c=0;
#10;
a=0;b=0;c=1;
#20;
a=0;b=1;c=0;
#30;
a=0;b=1;c=1;

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#40;
a=1;b=0;c=0;
#50;
a=1;b=0;c=1;
#60;
a=1;b=1;c=0;
#70;
a=1;b=1;c=1;
#80;
end
endmodule

Data flow model:

module fadf_tb;
reg a,b,c;
wire s,co;
fa f1(a,b,c,co,s);
initial
begin
a=0;b=0;c=0;
#10;
a=0;b=0;c=1;
#20;
a=0;b=1;c=0;
#30;
a=0;b=1;c=1;
#40;
a=1;b=0;c=0;
#50;
a=1;b=0;c=1;
#60;
a=1;b=1;c=0;
#70;
a=1;b=1;c=1;
#80;
end
endmodule

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Behaviour model:

module fabm_tb;
reg [2:0]a;
wire s,co;
fa1 f1(a,s,co);
initial
begin
a=3'b000;
#10;
a=3'b001;
#50;
a=3'b111;
#50;
a=3'b101;
#50;
a=3'b011;
#50;
end
endmodule

Output Waveforms:

RESULT:
Hence, Full adder is designed in Gate level,dataflow model and behavior model and
results are simulated.

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3. 3 to 8 DECODER

AIM:
To design a 3 to 8 Decoder using Verilog.
APPARATUS:
Xilinx Vivado
THEORY:
A Decoder is a combinational logic circuit which is used to change the code into a
set of signals.It uses all AND gates and therefore the outputs are active high.For
active low outputs,Nand gates are used.It can be called 3 to 8 line decoder because
it has 3 input lines and 8 output lines.It is also called binary to octal decoder
because it takes a binary 3 bit input code and activates one of the 8 outputs
corresponding to that code.
Truth Table:

CODE:
Gate level Model
module DEC38GL(a,b,c,out);
input a,b,c;
output [7:0]out;

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wire d,e,f;
not(d,a);
not(e,b);
not(f,c);
and(out[0],d,e,f);
and(out[1],d,e,c);
and(out[2],d,b,f);
and(out[3],d,b,c);
and(out[4],a,e,f);
and(out[5],a,e,c);
and(out[6],a,b,f);
and(out[7],a,b,c);
endmodule

Test bench:
module dec38gl_tb;
reg a,b,c;
wire [7:0]out;
DEC38GL d(a,b,c,out);
initial
begin
a=0;b=0;c=0;
#10;
a=0;b=0;c=1;
#20;
a=0;b=1;c=0;

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#30;
a=0;b=1;c=1;
#40;
a=1;b=0;c=0;
#50;
a=1;b=0;c=1;
#60;
a=1;b=1;c=0;
#70;
a=1;b=1;c=1;
#80;
end
endmodule

2) Data flow model:

module DEC38GL(a,b,c,out);
input a,b,c;
output [7:0]out;
wire d,e,f;
not(d,a);
not(e,b);
not(f,c);
and(out[0],d,e,f);
and(out[1],d,e,c);
and(out[2],d,b,f);
and(out[3],d,b,c);
and(out[4],a,e,f);

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and(out[5],a,e,c);
and(out[6],a,b,f);
and(out[7],a,b,c);
endmodule

Test bench:
module dec38gl_tb;
reg a,b,c;
wire [7:0]out;
DEC38GL d(a,b,c,out);
initial
begin
a=0;b=0;c=0;
#10;
a=0;b=0;c=1;
#20;
a=0;b=1;c=0;
#30;
a=0;b=1;c=1;
#40;
a=1;b=0;c=0;
#50;
a=1;b=0;c=1;
#60;
a=1;b=1;c=0;
#70;
a=1;b=1;c=1;

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#80;
end
endmodule

3) Behavioral model:
module dec38bm(a,out);
input [2:0]a;
output reg [7:0]out;
always@(a)
begin
case(a)
3'b000:
begin
out=1;
end
3'b001:
begin
out<=2;
end
3'b010:
begin
out<=4;
end
3'b011:
begin
out<=8;
end

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3'b100:
begin
out<=16;
end
3'b110:
begin
out<=64;
end
3'b101:
begin
out<=32;
end
3'b111:
begin
out<=128;
end
endcase
end
endmodule

Test bench:
module dec38bm_tb;
reg [2:0]a;
wire [7:0]out;
dec38bm d(a,out);
initial
begin

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a=3'b000;
#10;
a=3'b001;
#20;
a=3'b010;
#30;
a=3'b011;
#40;
a=3'b100;
#50;
a=3'b101;
#60;
a=3'b110;
#70;
a=3'b111;
#80;
end
endmodule

OUTPUT WAVEFORMS:

RESULT:
A 3 to 8 Decoder was designed and its operation was verified.

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4. 8 TO 3 ENCODER

AIM:
To write Verilog code for 8 to 3 encoder and simulate the results in verilog.
APPARATUS:
XILINX’S Vivado
THEORY:
An encoder is a device which converts familiar numbers or characters or
symbols into a coded format. It accepts the alphabetic characters and decimal
numbers as inputs and produces the outputs as a coded representation of the inputs.
It encodes the given information into a more compact form. These are mainly used
to reduce the number of bits needed to represent given information. In digital
systems, encoders are used for transmitting the information.
The 8 to 3 Encoder or octal to Binary encoder consists of 8 inputs: Y7 to Y0
and 3 outputs: A2, A1 & A0. Each input line corresponds to each octal digit and
three outputs generate corresponding binary code.
The truth table for 8 to 3 encoder is as follows:

Logical expressions for A2, A1 and A0 :

A2 = Y7 + Y6 + Y5 + Y4
A1 = Y7 + Y6 + Y3 + Y2

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A0 = Y7 + Y5 + Y3 + Y1

CODE:
Gate level model:
module en8to3(o1,o2,o3,i);
input [7:0]i;
output o1,o2,o3;
or(o1,i[1],i[3],i[5],i[7]);
or(o2,i[2],i[3],i[6],i[7]);
or(o3,i[4],i[5],i[6],i[7]);
endmodule
Test Bench:
module testen8to3;
reg [7:0]i;
wire o1,o2,o3;
en8to3 E(o1,o2,o3,i);
initial
begin
i=8'b00000001;
#10;
i=8'b00000010;
#20;
i=8'b10000000;
#40;
end

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endmodule

OUTPUT WAVEFORM:

RESULT:
Hence, 8 to 3 encoder is designed and results are simulated.

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5. 8-1 MULTIPLEXER

AIM: To design an 8 to 1 Multiplexer

APPARATUS:
Xilinx Vivado
THEORY:
Mux means Sharing.There are two types of multiplexing.They are Time
multiplexing and Frequency Multiplexing.A Multiplexer is a logic circuit
that accepts several data inputs and allows any one of them at a time to
get through to the output.The routing of the desired data input to the output
is controlled by select inputs.Normally there are 2^n input lines and n slect
lines whose bit combinations determine whch input is selected.
TRUTH TABLE:

CODE:
1. Gate level Model:
module g8to1MUX(a,b,c,d,e,f,g,h,o,s1,s2,s3);
input a,b,c,d,e,f,g,h,s1,s2,s3;

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output o;
wire n1,n2,n3,A,B,C,D,E,F,G,H;
not(n1,s1);
not(n2,s2);
not(n3,s3);
and(A,a,n1,n2,n3);
and(B,b,n1,n2,s3);
and(C,c,n1,s2,n3);
and(D,d,n1,s2,s3);
and(E,e,s1,n2,n3);
and(F,f,s1,n2,s3);
and(G,g,s1,s2,n3);
and(H,h,s1,s2,s3);
or(o,A,B,C,D,E,F,G,H);
endmodule

Test bench:
module tb_g8to1MUX;
reg a,b,c,d,e,f,g,h,s1,s2,s3;
wire o;
g8to1MUX I(a,b,c,d,e,f,g,h,o,s1,s2,s3);
initial
begin
a=1;b=0;c=1;d=0;e=0;f=0;g=0;h=0;s1=0;s2=0;s3=0;
#10;
a=1;b=0;c=1;d=0;e=0;f=0;g=0;h=0;s1=0;s2=0;s3=1;
#20;

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a=1;b=0;c=1;d=0;e=0;f=0;g=0;h=0;s1=0;s2=1;s3=0;
#50;
end
endmodule

2. Data flow Model

Code:
module d8to1MUX(a,b,c,d,e,f,g,h,o,s1,s2,s3);
input a,b,c,d,e,f,g,h,s1,s2,s3;
output o;
assign o=s1?(s2?(s3?h:g):(s3?f:e)):(s2?(s3?d:c):(s3?b:a));
endmodule

Test bench:
module tb_d8to1MUX;
reg a,b,c,d,e,f,g,h,s1,s2,s3;
wire o;
d8to1MUX I(a,b,c,d,e,f,g,h,o,s1,s2,s3);
initial
begin
a=1;b=0;c=1;d=0;e=0;f=0;g=0;h=0;s1=0;s2=0;s3=0;
#10;
a=1;b=0;c=1;d=0;e=0;f=0;g=0;h=0;s1=0;s2=0;s3=1;
#20;
a=1;b=0;c=1;d=0;e=0;f=0;g=0;h=0;s1=0;s2=1;s3=0;
#50;
end

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endmodule

3. Behavioural Model
Code:
module b8to1MUX(a,b,c,d,e,f,g,h,o,s1,s2,s3);
input a,b,c,d,e,f,g,h,s1,s2,s3;
output o;
reg o;
always@(a or b or c or d or e or f or g or h or s1 or s2 or s3)
begin
case({s1,s2,s3})
2'b000:o=a;
2'b001:o=b;
2'b010:o=c;
2'b011:o=d;
2'b100:o=e;
2'b101:o=f;
2'b110:o=g;
2'b111:o=h;
default:o=1'bx;
endcase
end
endmodule

Test bench:
module tb_b8to1MUX;
reg a,b,c,d,e,f,g,h,s1,s2,s3;

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wire o;
b8to1MUX I(a,b,c,d,e,f,g,h,o,s1,s2,s3);
initial
begin
a=1;b=0;c=1;d=0;e=0;f=0;g=0;h=0;s1=0;s2=0;s3=0;
#10;
a=1;b=0;c=1;d=0;e=0;f=0;g=0;h=0;s1=0;s2=0;s3=1;
#20;
a=1;b=0;c=1;d=0;e=0;f=0;g=0;h=0;s1=0;s2=1;s3=0;
#50;
end
endmodule

OUTPUT WAVEFORMS:

RESULT:
An 8 to 1 Multiplexer was designed and its operation was verified.

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6. 1-4 DEMULTIPLEXER
AIM:
To design a 1 to 4 Demultiplexer
APPARATUS:
Xilinx Vivado
THEORY:
A Demultiplexer performs the reverse operation of multipler.It takes a single input
and distributes it to several outputs.So,a demultiplexer can be thought as a
distributor since it transmits the same data to different destinations.Demultiplexer
is a 1 to N(2^n) device.The select input code determines the output to which input
data will be transmitted.

CODE:
1) Gate level Model
module demux14(i,s1,s2,o);
input i,s1,s2;
output [3:0]o;
wire s1n,s2n;
not(s1n,s1);
not(s2n,s2);
and(o[0],s2n,s1n,i);
and(o[1],s2n,s1,i);

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and(o[2],s2,s1n,i);
and(o[3],s2,s1,i);
endmodule

Test bench:
module tb;
reg i,s1,s2;
wire [3:0]o;
demux14 d(i,s1,s2,o);
initial
begin
i=1;s1=0;s2=0;
#10;
i=1;s1=0;s2=0;
#10;
i=1;s1=0;s2=1;
#10;
i=1;s1=1;s2=0;
#10;
i=1;s1=1;s2=1;
#50;
end
endmodule

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2) Data flow model

module demux14(i,s1,s2,o);
input i,s1,s2;
output [3:0]o;
assign o[0]=~s2&~s1&i;
assign o[1]=~s2&s1&i;
assign o[2]=s2&~s1&i;
assign o[3]=s2&s1&i;
endmodule

Test bench:
module tb;
reg i,s1,s2;
wire [3:0]o;
demux14 d(i,s1,s2,o);
initial
begin
i=1;s1=0;s2=0;
#10;
i=1;s1=0;s2=0;
#10;
i=1;s1=0;s2=1;
#10;
i=1;s1=1;s2=0;
#10;
i=1;s1=1;s2=1;
#50;

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end
endmodule

3) Behavioral model
module demux14(i,s1,s2,o);
input i,s1,s2;
output reg [3:0]o;
always@(i or s1 or s2)
begin
casex({i,s2,s1})
3'b0xx:
begin
o<=0;
end
3'b100:
begin
o<=1;
end
3'b101:
begin
o<=2;
end
3'b110:
begin
o<=4;
end
3'b111:

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begin
o<=8;
end
endcase
end
endmodule

TEST BENCH:
module tb;
reg i,s1,s2;
wire [3:0]o;
demux14 d(i,s1,s2,o);
initial
begin
i=1;s1=0;s2=0;
#10;
i=0;s1=0;s2=0;
#10;
i=1;s1=1;s2=0;
#10;
i=1;s1=0;s2=1;
#10;
i=1;s1=1;s2=1;
#60;
end
endmodule

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OUTPUT WAVEFORMS:

RESULT:
A 1 to 4 De-multiplexer was designed and its operation was verified.

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7. JK-FLIPFLOP

AIM:
To write Verilog code for JK-flipflop and simulate the results in verilog.
APPARATUS:
XILINX’S Vivado
THEORY:
A flipflop known more formally as a bi-stable multivibrator has two stable states.
It can remain in either of the states indefinitely. Its states can be changed by applying
the proper triggering signal. It is also called a binary or one bit memory. The flipflop
has two outputs, labelled Q and Q1. The Q output is the normal output of the flipflop
and Q1 is the inverted output.
The JK flipflop is very versatile and also most widely used. The J and K inputs
of the JK flipflop are called synchronous control inputs because data on these inputs
affect the flipflop’s output only on the triggering[positive going] edge of the clock
pulse. Without a clock pulse the J and K inputs cannot effect the output. When J is
high and K is LOW, the Q output goes HIGH on the positive going edge of the clock
pulse and the flipflop is SET. When J is LOW and K is HIGH, the Q output goes
LOW and the filpflop is RESET. When both inputs are LOW then the output Q does
not change from its prior state. When both inputs are HIGH, then the output Q
toggles.
CODE:
module jk_ff(q,q1,j,k,c);
output q,q1;
input j,k,c;
reg q,q1;
initial
begin
q=1'b0;

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15011A0423 Page No: 34

q1=1'b1;
end
always@(posedge c)
begin
case({j,k})
{1'b0,1'b0}:begin q=q;q1=q1;end
{1'b0,1'b1}:begin q=1'b0;q1=1'b1;end
{1'b1,1'b0}:begin q=1'b1;q1=1'b0;end
{1'b1,1'b1}:begin q=~q;q1=~q1;end
endcase
end
endmodule

TEST BENCH:
module jkff_tb;
reg j,k,c;
wire q,q1;
jk_ff j1(q,q1,j,k,c);
initial
begin
c=1'b0;
#5 j=0;k=0;
#15 j=0;k=1;
#25 j=1;k=0;
#35 j=1;k=1;
#100;

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15011A0423 Page No: 35

end
always #5 c=~c;
endmodule

OUTUT WAVEFORMS:

RESULT:
Hence, JK-FlipFlop is designed and results are simulated.

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15011A0423 Page No: 36

8. D-FLIPFLOP

AIM:
To write Verilog code for D-Flipflop and simulate the results in verilog.
APPARATUS:
XILINX’S Vivado
THEORY:
A flipflop known more formally as a bi-stable multivibrator has two stable states.
It can remain in either of the states indefinitely. Its states can be changed by applying
the proper triggering signal. It is also called a binary or one bit memory. The flipflop
has two outputs, labelled Q and Q1. The Q output is the normal output of the flipflop
and Q1 is the inverted output.
This flipflop has only one synchronous control input in addition to the clock
input.This is called D(data) input. The output Q will go to the same state that is
present on the D input at the positive going edge of the clock pulse. In other words
the level present at D will be stored in the flipflop at the instant the positive-going
transition occurs i,e. if D is 1 and the clock is applied, Q goes to1. If D is 0 and the
clock is applied, Q goes to 0 and thereafter remains so.

CODE:
module D_ff(q,q1,d,c);
output q,q1;
input d,c;
reg q,q1;
initial
begin
q=1'b0;q1=1'b1;
end

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15011A0423 Page No: 37

always@(posedge c)
begin
q=d;
q1=~d;
end
endmodule

TESTBENCH:
module dff_tb;
reg d,c;
wire q,q1;
D_ff d1(q,q1,d,c);
initial
begin
c=1'b0;
#5 d=1'b0;
#10 d=1'b1;
#100;
end
always #5 c=~c;
endmodule

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15011A0423 Page No: 38

OUTPUT WAVEFORMS:

RESULT:
Hence, D-FlipFlop is designed and results are simulated.

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15011A0423 Page No: 39

9. SR-FLIPFLOP

AIM:
To write Verilog code for SR-Flipflop and simulate the results in verilog.
APPARATUS:
XILINX’S Vivado
THEORY:
A flipflop known more formally as a bi-stable multivibrator has two stable
states. It can remain in either of the states indefinitely. Its states can be changed by
applying the proper triggering signal. It is also called a binary or one bit memory.
The flipflop has two outputs, labelled Q and Q1. The Q output is the normal output
of the flipflop and Q1 is the inverted output.
The S and R inputs of the SR flipflop are called synchronous control inputs
because data on these inputs affect the flipflop’s output only on the
triggering[positive going] edge of the clock pulse. Without a clock pulse the S and
R inputs cannot effect the output. When S is high and R is LOW, the Q output goes
HIGH on the positive going edge of the clock pulse and the flipflop is SET. When S
is LOW and R is HIGH, the Q output goes LOW and the filpflop is RESET. When
both inputs are LOW then the output Q does not change from its prior state. When
both inputs are HIGH, an invalid condition exists.

CODE:
module sr_ff(q,q1,s,r,c);
input s,r,c;
output q,q1;
reg q,q1;
initial
begin

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15011A0423 Page No: 40

q=1'b0;
q1=1'b1;
end
always@(posedge c)
begin
case({s,r})
{1'b0,1'b0}:begin q=q;q1=q1;end
{1'b0,1'b1}:begin q=1'b0;q1=1'b1;end
{1'b1,1'b0}:begin q=1'b1;q1=1'b0;end
{1'b1,1'b1}:begin q=1'bx;q1=1'bx;end
endcase
end
endmodule
TESTBENCH:
module srff_tb;
reg s,r,c;
wire q,q1;
sr_ff s1(q,q1,s,r,c);
initial
begin
c=1'b0;
#5 s=0;r=0;
#15 s=0;r=1;
#25 s=1;r=0;
#35 s=1;r=1;

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15011A0423 Page No: 41

#50;
end
always #5 c=~c;
endmodule

OUTPUT WAVEFORMS:

RESULT:
Hence, SR- FlipFlop is designed and results are simulated.

JNTUHCEH
15011A0423 Page No: 42

10. T- FLIPFLOP

AIM:
To write Verilog code for T- Flipflop and simulate the results in verilog.
APPARATUS:
XILINX’S Vivado
THEORY:
A flipflop known more formally as a bi-stable multivibrator has two stable states.
It can remain in either of the states indefinitely. Its states can be changed by applying
the proper triggering signal. It is also called a binary or one bit memory. The flipflop
has two outputs, labelled Q and Q1. The Q output is the normal output of the flipflop
and Q1 is the inverted output.
A T fliflop has a single control input, labelled T for toggle. When T is HIGH, the
flpflop toggles on every new clock pulse. When T is LOW, the flipflop remain in
whatever state it was before. Although T flipflops are not widely available
commercially, it is easy to convert a JK flipflop to functional equivalent of T flipflop
by just connecting J and K together and labelling the common connection as T. Thus
when T is 1, we have J=K=1 and the flipflop toggles. When T is 0, we have J=K=0
so there is no change of state.

CODE:
module t_ff(q,q1,t,c );
output q,q1;
input t,c;
reg q,q1;
initial
begin
q=1'b0;q1=1'b1;

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15011A0423 Page No: 43

end
always@(posedge c)
begin
q=~t;
q1=t;
end
endmodule

TESTBENCH:
module tff_tb;
reg t,c;
wire q,q1;
t_ff t1(q,q1,t,c);
initial
begin
c=1'b0;
#5 t=1'b0;
#10 t=1'b1;
#100;
end
always #5 c=~c;
endmodule

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15011A0423 Page No: 44

OUTPUT WAVEFORMS:

RESULT:
Hence, T- FlipFlop is designed and results are simulated.

JNTUHCEH
15011A0423 Page No: 45

11. 4-BIT COMPARATOR

AIM:
To write Verilog code for 4-bit comparator and simulate the results in verilog.
APPARATUS:
XILINX’S Vivado
THEORY:

A magnitude digital Comparator is a combinational circuit that compares two

digital or binary numbers in order to find out whether one binary number is equal,
less than or greater than the other binary number. We logically design a circuit for
which we will have two inputs one for A and other for B and have three output
terminals, one for A > B condition, one for A = B condition and one for A < B
condition.
In a 4-bit comparator the condition of A>B can be possible in the following
four cases:
1. If A3 = 1 and B3 = 0
2. If A3 = B3 and A2 = 1 and B2 = 0
3. If A3 = B3, A2 = B2 and A1 = 1 and B1 = 0
4. If A3 = B3, A2 = B2, A1 = B1 and A0 = 1 and B0 = 0

Similarly the condition for A<B can be possible in the following four cases:
1. If A3 = 0 and B3 = 1
2. If A3 = B3 and A2 = 0 and B2 = 1
3. If A3 = B3, A2 = B2 and A1 = 0 and B1 = 1
4. If A3 = B3, A2 = B2, A1 = B1 and A0 = 0 and B0 = 1

The condition of A=B is possible only when all the individual bits of one number
exactly coincide with corresponding bits of another number.
The logic expression for A>B can be written as

̅̅̅̅+(A3ʘ𝐵3)A2𝐵2
A3.𝐵3 ̅̅̅̅+((A3ʘ𝐵3)(A2ʘ𝐵2)A1𝐵1
̅̅̅̅+(A3ʘ𝐵3)(A2ʘ𝐵2)(A1ʘB1)
̅̅̅̅.
A0𝐵0

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15011A0423 Page No: 46

The logic expression for A<B can be written as

̅̅̅̅ ̅̅̅̅B2+(A3ʘ𝐵3)(A2ʘ𝐵2)𝐴1
𝐴3𝐵3+(A3ʘ𝐵3)𝐴2 ̅̅̅̅B1+(A3ʘ𝐵3)(A2ʘ𝐵2)(A1ʘB1)
̅̅̅̅
𝐴0𝐵0
The expression for A=B can be written as
(A3ʘ𝐵3)(A2ʘ𝐵2)(A1ʘB1) (A0ʘ𝐵0)

CODE:
Gatelevel Model:
module fourbitcomp(G,L,E,a,b);
input [3:0]a;
input [3:0]b;
output G,L,E;
wire b3b,b2b,b1b,b0b,a0b,a1b,a2b,a3b,G0,G1,G2,G3,L0,L1,L2,L3,X3,X2,X1,X0;
not(b3b,b[3]);
not(b2b,b[2]);
not(b1b,b[1]);
not(b0b,b[0]);
not(a3b,a[3]);
not(a2b,a[2]);
not(a1b,a[1]);
not(a0b,a[0]);
xnor(X3,a[3],b[3]);
xnor(X2,a[2],b[2]);
xnor(X1,a[1],b[1]);
xnor(X0,a[0],b[0]);
and(G0,a[3],b3b);

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15011A0423 Page No: 47

and(G1,X3,a[2],b2b);
and(G2,X3,X2,a[1],b1b);
and(G3,X3,X2,X1,a[0],b0b);
or(G,G0,G1,G2,G3);
and(L0,a3b,b[3]);
and(L1,X3,a2b,b[2]);
and(L2,X3,X2,a1b,b[1]);
and(L3,X3,X2,X1,a0b,b[0]);
or(L,L0,L1,L2,L3);
and(E,X1,X2,X3,X0);
endmodule
Data Flow Model:
module fourbitcomp(G,L,E,a,b);
output G,L,E;
input [3:0]a;
input [3:0]b;
assign G=(a>b);
assign L=(a<b);
assign E=(a==b);
endmodule
TESTBENCH:
module test_fourbit;
reg [3:0]a;
reg [3:0]b;
wire G,L,E;

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15011A0423 Page No: 48

fourbitcomp F(G,L,E,a,b);
initial
begin
a<=10;
b<=12;
#20;
a<=12;
b<=12;
#10;
a<=12;
b<=10;
#40;
end
endmodule
OUTPUT WAVEFORMS:

RESULT:
Hence, 4-bit comparator is designed and results are simulated.

JNTUHCEH
15011A0423 Page No: 49

12. BINARY-TO-GRAY CODE CONVERTER

AIM:
To write Verilog code for binary-to-gray code converter and simulate the results
in verilog.
APPARATUS:
XILINX’S Vivado
THEORY:

The input to the 4-bit binary-to-gray code converter circuit is a 4-bit binary and the
output is a 4-bit Gray code.There are 16 possible combinations of 4-bit binary input
and all of them are valid.

The minimal expressions for the outputs G4,G3,G2 and G1 are:

G4=B4
̅̅̅̅
̅̅̅̅ B3+B4𝐵3
G3=𝐵4
̅̅̅̅ B2+B3 𝐵2
G2=𝐵3 ̅̅̅̅
̅̅̅̅ B1+B2 𝐵1
G1=𝐵2 ̅̅̅̅

The conversion can be achieved by using three X-OR gates in the logic diagram.

CODE:
Gatelevel Model:
module bin2gray(g,b);
input [3:0]b;
output [3:0]g;
buf(g[3],b[3]);
xor(g[2],b[3],b[2]);

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15011A0423 Page No: 50

xor(g[1],b[2],b[1]);
xor(g[0],b[1],b[0]);
endmodule
Behavioral model:
module bin2gray(g,b);
input [3:0]b;
output reg [3:0]g;
always@(b)
begin
g[3]<=b[3];
g[2]<=b[3]^b[2];
g[1]<=b[2]^b[1];
g[0]<=b[1]^b[0];
end
endmodule
DataFlow Model:
module bin2gray(g,b);
input [3:0]b;
output [3:0]g;
assign g[3]=b[3];
assign g[2]=b[3]^b[2];
assign g[1]=b[2]^b[1];
assign g[0]=b[1]^b[0];
endmodule

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15011A0423 Page No: 51

TESTBENCH:
module test_bin2gray;
reg [3:0]b;
wire [3:0]g;
bin2gray B(g,b);
initial
begin
b=4'b0001;
#10; b=4'b1010;
#20; b=4'b1111;
#40;
end
endmodule
OUTPUT WAVEFORMS:

RESULT:
Hence,binary-to-gray code converter is designed and results are
simulated.

JNTUHCEH
15011A0423 Page No: 52

13. CMOS NOT GATE

AIM:
To write Verilog code for CMOS NOT gate and simulate the results in verilog.
APPARATUS:
XILINX’S Vivado
THEORY:
CMOS Inverter
The inverter circuit as shown in the figure below. It consists of PMOS and NMOS
FET. The input A serves as the gate voltage for both
transistors.

The NMOS transistor has an input from Vss (ground) and

PMOS transistor has an input from Vdd. The terminal Y is
output. When a high voltage (~ Vdd) is given at input
terminal (A) of the inverter, the PMOS becomes open
circuit and NMOS switched OFF so the output will be
pulled down to Vss.

When a low-level voltage (<Vdd, ~0v) applied to the

inverter, the NMOS switched OFF and PMOS switched ON. So the output becomes
Vdd or the circuit is pulled up to Vdd.

CODE:
module cmos_not(x,y);
input x;
output y;
supply1 vdd;
supply0 gnd;
pmos p1(y,vdd,x);

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15011A0423 Page No: 53

nmos n1(y,gnd,x);
endmodule
TESTBENCH:
module cmos_not_tb;
reg x;
wire y;
cmos_not c1(x,y);
initial
begin
#5 x=1;
#10 x=0;
end
endmodule

OUTPUT WAVEFORM:

RESULT:
Hence CMOS NOT gate is designed and the results are simulated using verilog.

JNTUHCEH
15011A0423 Page No: 54

14. CMOS NAND GATE

AIM:
To write Verilog code for CMOS NAND gate and simulate the results in verilog.
APPARATUS:
XILINX’S Vivado
THEORY:
CMOS NAND gate is one of the
important and simple realizations. CMOS is
the combination of PMOS and NMOS. The
circuit shows the realization of CMOS NAND
gate which consists of two PMOS and two
NMOS gates.
Operation in this circuit is when Va and
Vb are high i.e. at 5V then the two PMOS will
be open circuited and two NMOS will be
Short circuited. The output Vout will be
shorted to ground and produces zero output. If
any of the input is low (0 V) corresponding
PMOS will be shorted and NMOS will opened
the Vout is shorted to Vdd which provides
high output. The truth table shows all the possible operation of NAND gate using
CMOS.

CODE:
module cmos_nand(x,y,f);
input x,y;
output f;
supply1 vdd;

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15011A0423 Page No: 55

supply0 gnd;
wire a;
pmos p1(f,vdd,x);
pmos p2(f,vdd,y);
nmos n1(f,a,x);
nmos n2(a,gnd,y);
endmodule
TESTBENCH:
module cmos_nand_tb;
reg x,y;
wire f;
cmos_nand n1(x,y,f);
initial
begin
#5 x=0;y=0;
#5 x=1;y=0;
#5 x=0;y=1;
#5 x=1;y=1;
#10;
end
endmodule

JNTUHCEH
15011A0423 Page No: 56

OUTPUT WAVEFORM:

RESULT:
Hence CMOS NAND gate is designed and the results are simulated using verilog.

JNTUHCEH
15011A0423 Page No: 57

15. CMOS NOR GATE

AIM:
To write Verilog code for CMOS NOR gate and simulate the results in verilog.
APPARATUS:
XILINX’S Vivado
THEORY:
A 2-input NOR gate is shown in the figure below.
The NMOS transistors are in parallel to pull the
output low when either input is high. The PMOS
transistors are in series to pull the output high
when both inputs are low, as given in below table.
The output is never left floating.

The truth table of NOR logic gate given in below table.

A B Y
0 0 1
0 1 0
1 0 0
1 1 0

CODE:
module cmos_nor(x,y,f);
input x,y;
output f;

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15011A0423 Page No: 58

supply1 vdd;
supply0 gnd;
wire a;
pmos p1(a,vdd,x);
pmos p2(f,a,y);
nmos n1(f,gnd,x);
nmos n2(f,gnd,y);
endmodule

TESTBENCH:

module cmosnor_tb;
reg x,y;
wire f;
cmos_nor n2(x,y,f);
initial
begin
#5 x=0;y=0;
#5 x=1;y=0;
#5 x=0;y=1;
#5 x=1;y=1;
#10;
end
endmodule

JNTUHCEH
15011A0423 Page No: 59

OUTPUT WAVEFORM:

RESULT:
Hence CMOS NOR gate is designed and the results are simulated using verilog.

JNTUHCEH