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    Open Ended Experiment Basic Electronics Engineering (Es201) 3CSE-9Y

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    Kush
    This document assigns 6 groups of students to open-ended electronics experiments. Group 1 is assigned to design a voltage regulator using a Zener diode. Group 2 is assigned to design a voltage divider biasing circuit for a BJT amplifier. Group 3 is assigned to design a two-stage transistor amplifier. Group 4 is assigned to design a common-source amplifier. Group 5 is assigned to design and implement clipper circuits using an op-amp. Group 6 is assigned to design and implement a full subtractor using logic gates.

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    Open Ended Experiment Basic Electronics Engineering (Es201) 3CSE-9Y

    Uploaded by

    Kush
    324 views2 pages
    This document assigns 6 groups of students to open-ended electronics experiments. Group 1 is assigned to design a voltage regulator using a Zener diode. Group 2 is assigned to design a voltage divider biasing circuit for a BJT amplifier. Group 3 is assigned to design a two-stage transistor amplifier. Group 4 is assigned to design a common-source amplifier. Group 5 is assigned to design and implement clipper circuits using an op-amp. Group 6 is assigned to design and implement a full subtractor using logic gates.

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    open ended expt. 3CSE 9Y.docx

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    This document assigns 6 groups of students to open-ended electronics experiments. Group 1 is assigned to design a voltage regulator using a Zener diode. Group 2 is assigned to design a voltage divider biasing circuit for a BJT amplifier. Group 3 is assigned to design a two-stage transistor amplifier. Group 4 is assigned to design a common-source amplifier. Group 5 is assigned to design and implement clipper circuits using an op-amp. Group 6 is assigned to design and implement a full subtractor using logic gates.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    324 views2 pages

    Open Ended Experiment Basic Electronics Engineering (Es201) 3CSE-9Y

    Uploaded by

    Kush
    This document assigns 6 groups of students to open-ended electronics experiments. Group 1 is assigned to design a voltage regulator using a Zener diode. Group 2 is assigned to design a voltage divider biasing circuit for a BJT amplifier. Group 3 is assigned to design a two-stage transistor amplifier. Group 4 is assigned to design a common-source amplifier. Group 5 is assigned to design and implement clipper circuits using an op-amp. Group 6 is assigned to design and implement a full subtractor using logic gates.

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    OPEN ENDED EXPERIMENT

    BASIC ELECTRONICS ENGINEERING (ES201)


    3CSE-9Y

    GROUP ENROLLMENT NAME EXPERIMENT


    NUMBER
    1 A2305218575 JALAJ AGARWAL To design a voltage
    A2305218576 LAVNEESH SAINI regulator using Zener
    A2305218579 VARSHA AGRAWAL diode that will
    A2305218580 VABHAV SHARMA maintain a constant
    output across load
    resistor with a
    variable dc input
    voltage. Also
    calculate maximum
    Zener current and
    power.
    2 A2305218581 HIMANSHU VERMA To design voltage
    A2305218584 SUNIDHI divider biasing circuit
    A2305218586 RAHUL YADAV for BJT as an amplifier
    A2305218587 ATUL CHAUDHARY to obtain the
    frequency response
    curve and determine
    the mid frequency
    gain, lower and
    higher cutoff
    frequency of the
    amplifier circuit.
    3 A2305218589 TANYA GOYAL Design a two stage
    A2305218590 DIGANT CHANDELA transistor amplifier
    A2305218591 SAURABH which employs
    A2305218592 HEMANYA MEHTA emitter follower
    configuration prior to
    common base
    configuration to
    ensure that the
    maximum percentage
    of applied signal
    appears at the input
    terminals of
    common base
    amplifier. The
    following information
    is given:
    Emitter Follower: Z i
    =10K Ω, Zo = 12Ω, A V
    =1. Common Base: Z i
    =26 Ω, Zo = 5.1KΩ, A
    V =240.
    R S = 1K Ω, R L = 8.2K
    Ω
    4 A2305218595 KARAN MALIK Design of common
    A2305218597 VANSH GOYAL source amplifier for
    A2305218598 CHANDAN SHARMA desired ac voltage
    A2305218601 KSHITIZ SHARMA gain using self-biasing
    circuit and determine
    various parameters
    and draw drain
    characteristics.
    5 A2305218602 SIDDHARTH MAKOL Design and
    A2305218603 VANDIT JAIN implement clippers
    A2305218604 AYUSH GUPTA (biased and unbiased)
    A2305218605 SAKSHI NIMJE using OP-AMP IC 741
    and other necessary
    components.
    6 A2305218606 GUNJAN SAINI Design and
    A2305218737 ABHINAV SAXENA implement full
    A2305218738 RAJ THAKUR subtractor by using
    A2305218037 PRERIT RAJPUT minimum number of
    A2305218065 YUGANSH PREET Universal gates.

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