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Repetitive Algorithm Loop

Loop statements in Verilog include the forever, repeat, while, and for loops. There are 4 types: 1) forever loops continuously repeat a statement, 2) repeat loops repeat a statement a specified number of times, 3) while loops repeat a statement until an expression is true, and 4) for loops allow modeling procedural statements with initial, conditional, and step assignments.

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22 views

Repetitive Algorithm Loop

Loop statements in Verilog include the forever, repeat, while, and for loops. There are 4 types: 1) forever loops continuously repeat a statement, 2) repeat loops repeat a statement a specified number of times, 3) while loops repeat a statement until an expression is true, and 4) for loops allow modeling procedural statements with initial, conditional, and step assignments.

Uploaded by

kiran
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Loop statements

Loop statements are used to control repeated


execution of one or more statements. There are
4 types of looping stetements in Verilog:
• forever statement;
• repeat(expression) statement;
• while(expression) statement;
• for(initial_assignment; expression; step_assignment)
statement;
forever Loop:

The forever instruction continuously repeats the statement that


follows it. Therefore, it should be used with procedural timing
controls (otherwise it hangs the simulation). Consider this
example:
initial
begin
clk = 0;
forever #5 clk = ~clk;
end
repeat Loop:

Repeats the following instruction for specified times. The number of


executions is set by the expression or constant value. If expression
evaluates to high impedance or un-known, then statement will not be
executed.
initial
begin
x = 0;
repeat( 16 )
begin
#2 $display(“reg1= ", reg1);
x = x + 1;
end
end
while Loop:

while loop repeats the statement until the expression returns true.
If starts with false value, high impedance or unknown value,
statement will not be executed.
initial
begin
x = 0;
while( x <= 10 )
begin
#2 $display("y= ", y);
x = x + 1;
end
end
FOR LOOP:

Loop statements provide a means of modeling blocks of


procedural statements.

for (assignment; expression; assignment) statement;


Initial
begin
for (index=0; index < 10; index = index + 2)
mem[index] = index;
end
Clock generator with 75 percent duty cycle

Initial
clk=1’b1;
Always
begin
#75 clk=1’b0;
#25 clk=1’b1;
end

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