10/13/2019 Steps to root cause clock latency / insertion delay QOR post CCopt CTS

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Steps to root cause clock latency / insertion delay QOR post View Attachments | i
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How To...
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Following "How To" are covered in this article:

1. Grep commands to fetch the Clock QOR each sub stage wise from the CCOpt Log
2. Find out the longest clock ID/latency path 
3. Highlight top worst clock paths
4. Find out the geometrically farthest sink
5. Find out the stage based delay for a particular clock path

FEEDBACK
6. Find out the NDR and the layer adherence for a particular clock path

Answer
To debug the clock latency qor, a user needs to find in which substage there is a jump in the Clock
latency.
Following parameters will provide the substage information and the clock QOR values at those sub-
stages:

Fetching the clock DAG will help to understand the substage, cell count and area of
clock tree network
Fetching the “Primary reporting skew group” pattern will help user to get the
Clock QOR for that specific stage.
Use the following unix command to generate the above information :grep -E -A2 "Clock
DAG|Primary reporting" <LogFileName> | grep -v "\-\-"

The grep pattern may need slight modification per tool version, however, the same keywords can be
grepped.

Output:

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10/13/2019 Steps to root cause clock latency / insertion delay QOR post CCopt CTS

If the user finds out that the target insertion delay/latency is not met at clustering stage, then
he needs to debug the max clock ID path to understand the delay numbers, placement topology
and route topology. Analyzing these parameters helps to assess if there is any scope of
improvement to achieve the desired insertion delay/latency.

Incase user wants to stop CTS at different intermediate stages of clock implementation for debugging
purpose, he can refer to the below article:
How to stop CCOpt-CTS at different stages for debugging

How to find the longest clock ID/latency path:

The longest Clock ID/latency path is defined as the clock path which have the highest clock latency
from the clock root to the sink (flop/ sequential pin).
It is recommended to perform this analyses at the clustering stage.

Below command dumps the longest clock ID (max) path of a particular skew group:
Legacy: get_ccopt_skew_group_path -skew_group <skew_group_name> -longest
Common UI: get skew group path -skew group <skew group name> -longest
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10/13/2019 Steps to root cause clock latency / insertion delay QOR post CCopt CTS
Common UI: get_skew_group_path skew_group <skew_group_name> longest

Below command will trace the max path in GUI:

Legacy: ctd_win
ctd_trace -from [lindex [get_ccopt_skew_group_path -skew_group
<skewGroupName> -longest] 0] -to [lindex [get_ccopt_skew_group_path -
skew_group <skewGroupName> -longest] end] -color red

Common UI: gui_ctd_open

gui_ctd_highlight -from [lindex [get_ccopt_skew_group_path -
skew_group <skewGroupName> -longest] 0] -to [lindex
[get_ccopt_skew_group_path -skew_group <skewGroupName> -longest] end] -color
red

Fig 1: Snippet displaying the max path in the design

Note: “ctd_win” command is a prerequisite command which needs to run once before executing the
ctd_trace command.

Clustering stage will only add clock buffers/inverters to fix the DRV violations and it will not add any
buffers/inverters in the clock network to balance the clock tree.
However, tool will try to have more common path so that there will be less on chip variations and due to
this sometimes the max path can have some loops and detours. Hence it is recommended to look at a
few more top paths to determine the longest path seen by the tool.

Attached with this article are two scripts (zipped) - one for legacy mode and another for CUI mode,
which contain useful scripts to help debug the clock latency/insertion delay problems.

Highlighting top worst clock paths

Below script helps in highlighting top worst max paths of the design to avoid this ambiguity.
This script [highlighting_worst_ID_paths.tcl] will take “skew_group” and “number_of_paths” as
inputs from user and it will highlight the worst path in the design with different colors.
Colors used for highlighting the paths will start repeating from path number 33.

Usage:
source highlighting worst ID paths tcl
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10/13/2019 Steps to root cause clock latency / insertion delay QOR post CCopt CTS
source highlighting_worst_ID_paths.tcl
highlightingWorstIDpaths -skew_group <skewGroupName> -number_of_paths
<value>

Example:
source highlighting_worst_ID_paths.tcl
highlightingWorstIDpaths -skew_group my_clk/functional_func_slow_max -
number_of_paths 10

Output:

Fig 2: Snippet displaying top 10 worst Clock ID paths highlighted in the design

Finding out the geometrically farthest clock ID/latency path:

Geometrically farthest sink is defined as the farthest sinks from the root based on its Manhattan
distance.
Below script will help the user to get and trace the geometrically farthest sink from the clock root.

The usage of the script [finding_geometrically_farthest_sinks.tcl] is as follows:

Usage:
source finding_geometrically_farthest_sinks.tcl
findingFarthestSink -in_clock_tree <clock_tree_name> -root <Port/Pin Name> -
skew_group <skewGroupName>

Example:
source finding_geometrically_farthest_sinks.tcl
findingFarthestSink -in_clock_tree my_clk -root clk -skew_group
my_clk/functional_func_slow_max

Output:
proc0/cmem0/dtags0/u0/id0/CK1 956.13

Output of the script will trace the farthest sink from the root in the gui and will print the geometrically
farthest sink and the Manhattan distance of the sink pin from the root.
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10/13/2019 Steps to root cause clock latency / insertion delay QOR post CCopt CTS

Fig 3: Highlighting the geometrically farthest sink in the full cts run

Usually the geometrically farthest path should not be detoured.However, if the path is detoured then
user can check the below reasons for detouring:

Check for any fixed clock logic

Command to check: get_db [get_db clock_trees .insts -if {
.place_status == fixed }] .name
Command to make it status as placed: set_db [get_db clock_trees .insts -
if { .place_status == placed }] .place_status placed
Note: This command will work in both CUI and legacy from 17.x version
Check for clock gates movement
Legacy: get_ccopt_property cts_clock_gate_movement_limit [default value
is 10]
Common UI: get_db cts_clock_gate_movement_limit [default value is 10]
Floorplan issues
Power Domain setup
If the longest path (geometrically farthest sink) appears to be un-detoured, then the following procs
can be used to describe detailed parameters of the clock path.

Clock Path Based Stage Delay:

Following parameters can be checked by the user using the below script
[clock_path_based_stage_delay.tcl]:

1. Types of cells used in the clock path

2. Arrival Time for each stage
3. Actual Net Delay of each stage
4 Actual Cell Delay of each cell used
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10/13/2019 Steps to root cause clock latency / insertion delay QOR post CCopt CTS
4. Actual Cell Delay of each cell used
Usage:

source clock_path_based_stage_delay.tcl
stageDelaywithCellList -skew_group <skew_group_name> -sink <sinkName>

Example:
source clock_path_based_stage_delay.tcl
stageDelaywithCellList -skew_group my_clk/functional_func_slow_max -sink
proc0/rf0/u0/u1/rfd_reg_119_28/DFF/CK

Output when imported to excel:

Clock Path Based NDR and Layer Adherence

Following parameters can be inferred by the user from the above data:

1. Clock net type assigned on each clock net

2. NDR assigned on each clock net [Should follow the route rule on each net as per their route type]
3. Layer wise wirelength of each clock net [Maximum wirelength should be present in the specified
preferred layer of each route type]
4. Total wirelength of each clock net
5. Layer wise total wirelength of the complete clock path
6. Total wirelength of the complete clock path
Below script [calculate_path_net_length_layer_wise.tcl] can be used to understand the NDR and
layer adherence of a particular clock path.

Usage:
source calculate_path_net_length_layer_wise.tcl
calculatePathNetLengthLayerWise -skew_group <skewGroupName> -sink <sinkName>

Example:
source calculate_path_net_length_layer_wise.tcl
calculatePathNetLengthLayerWise -skew_group my_clk/functional_func_slow_max
-sink proc0/rf0/u0/u0/rfd_reg_75_25/DFF/C

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10/13/2019 Steps to root cause clock latency / insertion delay QOR post CCopt CTS

Attachments:

CUI_Scripts.zip (/sfc/servlet.shepherd/version/download/0680V000005rEgpQAE)

Legacy_Scripts.zip (/sfc/servlet.shepherd/version/download/0680V000005rEguQAE)

Related Solutions:

How to evaluate the QOR of flexible H-Tree and a case study of comparison between single source
v/s multi-source CTS
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Script to determine the metal layer adherence on all types of clock nets
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