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Risc

RISC processors have simpler instructions that take one clock cycle to execute, with an average of 1.5 clock cycles per instruction. They focus more on software optimization and do not have memory units, using separate hardware to implement instructions. CISC processors have more complex instructions that take multiple clock cycles, with an average of 2-15 clock cycles per instruction. They focus more on hardware optimization and have memory units to implement complex instructions. Examples of RISC processors include Alpha, ARM, and MIPS, while examples of CISC processors include x86 CPUs and older systems like VAX and PDP-11.

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110 views1 page

Risc

RISC processors have simpler instructions that take one clock cycle to execute, with an average of 1.5 clock cycles per instruction. They focus more on software optimization and do not have memory units, using separate hardware to implement instructions. CISC processors have more complex instructions that take multiple clock cycles, with an average of 2-15 clock cycles per instruction. They focus more on hardware optimization and have memory units to implement complex instructions. Examples of RISC processors include Alpha, ARM, and MIPS, while examples of CISC processors include x86 CPUs and older systems like VAX and PDP-11.

Uploaded by

Sreekrishna Das
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© © All Rights Reserved
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RISC CISC

1. RISC stands for Reduced Instruction1. CISC stands for Complex Instruction Set
Set Computer. Computer.
2. RISC processors have simple2. CSIC processor has complex instructions
instructions taking about one clock that take up multiple clocks for execution.
cycle. The average clock cycle perThe average clock cycle per instruction (CPI)
instruction (CPI) is 1.5 is in the range of 2 and 15.
3. Performance is optimized with more 3. Performance is optimized with more focus
focus on software on hardware.
4. It has no memory unit and uses a
separate hardware to implement4. It has a memory unit to implement
instructions.. complex instructions.
5. It has a hard-wired unit of
programming. 5. It has a microprogramming unit.
6. The instruction set is reduced i.e. it
has only a few instructions in the6. The instruction set has a variety of
instruction set. Many of thesedifferent instructions that can be used for
instructions are very primitive. complex operations.
7. CISC has many different addressing
7. The instruction set has a variety ofmodes and can thus be used to represent
different instructions that can be usedhigher-level programming language
for complex operations. statements more efficiently.
8. Complex addressing modes are8. CISC already supports complex
synthesized using the software. addressing modes
9. Multiple register sets are present 9. Only has a single register set
10. RISC processors are highly10. They are normally not pipelined or less
pipelined pipelined
11. The complexity of RISC lies with
the compiler that executes the
program 11. The complexity lies in the microprogram
12. Execution time is very less 12. Execution time is very high
13. Code expansion can be a problem 13. Code expansion is not a problem
14. Decoding of instructions is simple. 14. Decoding of instructions is complex
15. It does not require external15. It requires external memory for
memory for calculations calculations
16. The most common RISC
microprocessors are Alpha, ARC, ARM, 16. Examples of CISC processors are the
AVR, MIPS, PA-RISC, PIC, PowerSystem/360, VAX, PDP-11, Motorola 68000
Architecture, and SPARC. family, AMD and Intel x86 CPUs.
17. RISC architecture is used in high-
end applications such as video17. CISC architecture is used in low-end
processing, telecommunications andapplications such as security systems, home
image processing. automation, etc.

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