Verilog Ia

This document contains exam questions for an academic year 2019-20 Digital Electronics and Communication Engineering course. It is divided into two modules. For each module, students must choose one full question from the options given. The questions cover topics related to digital system design methodology, Verilog HDL, and concepts like data types, system tasks, compiler directives, modules and hierarchical naming. Students are asked to write code examples, explain concepts, draw block diagrams, and differentiate between terms.

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Verilog Ia

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raj

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ACA/R / 46 Department of Electronics & Academic Year: 2019-20

Communication Engineering

NOTE: Answer any two FULL Questions choosing one full questions from each module
Module 1
1a. Discuss in brief about the evolution of CAD tools and HDLs used in digital system design (7 Marks)

1b. Explain the typical VLSI IC design flow with the help of flow chart (8 Marks)

Or
2a. Why Verilog HDL has evolved as popular HDL in digital circuit design. (3 Marks)

2b. Explain the advantages of using HDLs over traditional schematic based design. (4 Marks)

2c. Describe the digital system design using hierarchical methodologies. (8 Marks)

Module 1
3a. Write Verilog HDL program to describe the 4-bit ripple counter. (7 Marks)

3b. Define Module and an Instance. Describe 4 different description styles of HDL. (8 Marks)

Or
4a. Apply the top-down design methodology to demonstrate the design of ripple counter. (8 Marks)

4b. Differentiate simulation and synthesis. What is stimulus? (7 Marks)

NOTE: Answer any two FULL Questions choosing one full questions from each module
Module 2

1a. Describe the lexical conventions used in Verilog HDL with examples. (7 Marks)

1b. Explain different data types of Verilog HDL with examples. (8 Marks)

2a. What are system tasks and compiler directives? (7 Marks)

2b. What are the uses of $monitor, $display and $finish system tasks? Explain with examples.
(8 Marks)

Module 2

3a. Explain Define, timescale and include compiler directives. (7 Marks)

3b. With neat block diagram, explain the components of Verilog HDL module. (8 Marks)

4a. What are the components of SR latch? Write Verilog HDL module for SR latch. (8 Marks)

4b. How hierarchical names helps in addressing any identifier used in the design from any other level of
hierarchy? Explain with examples. (7 Marks)

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Verilog Ia

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Verilog Ia

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ACA/R / 46 Department of Electronics & Academic Year: 2019-20

4b. Differentiate simulation and synthesis. What is stimulus? (7 Marks)

2a. What are system tasks and compiler directives? (7 Marks)

3a. Explain Define, timescale and include compiler directives. (7 Marks)

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