FPGA Verification Methodology for SiSoC Based SoC Design

Xu Huang, LinTao Liu, YuJing Li, LunCai Liu, XiaoZong Huang

Sichuan Institute of Solid State Circuits, Chongqing, 400060​ˈ​P.R. China

Abstract — ​ This paper proposes an efficient FPGA verification

methodology for SiSoC-based SoC design. FPGA-based
verification platform is an effective way to verify the SoC design,
and it is becoming very important to build a prototype of the SoC
design in FPGA. SiSoC is a high-performance and low-power
processor. The SiSoC-based SoC design adopts AMBA bus to
connect SiSoC processor to peripheral IPs and external memory
system. FPGA-based verification platform can improve the
time-to-market and help avoid costly re-spins by enabling early
embedded software development and allowing hardware and
software co-verification well ahead of chip fabrication. ​Index
Terms ​— FPGA, SoC, Verification

I. INTRODUCTION

The increasing SoC design complexity makes traditional The FPGA implementation is based Look-Up-Table (LUT)
simulation approach, based on Register Transfer Language architecture is different from the ASIC implementation, so use
(RTL) testbenches, not applicable due to their extremely high FPGA prototyping to verification the ASIC design, it must edit
time consuming. In fact, the SoC verification is far different the ASIC design code to map the ASIC design to FPGA. The
from ASIC verification, because the SoCs integrate CPUs and code in the following aspects of the ASIC design should be
memory, the system must has software based on CPU, thus the edited, include:
verification cooperated with this software is also necessary in (1) Storage Unit: Storage unit in ASIC is usually
SoC verification, this is the main difference between them, customized by foundry using Memory Complier tools. These
named HardWare/SoftWare (HW/SW) co-verification [​ 1]​. The units in ASIC are non-synthesized units. These storage units
FPGA verification technology offers an opportunity for SoC should be mapped into their counterparts in FPGA.
HW/SW co-verification and validation at high speed. It can (2) Clock Unit: Clock unit in ASIC usually consists
achieve 300MHz speed on real-time applications with scalable of clock tree and PLL. Clock unit in FPGA usually consists of
capacity. Therefore, it has become a more practical several PLLs and some special resources.
methodology for SoC development. (3) Integration of other IPs: Some analog IPs are
SiSoC is a high-performance and low-power processor. The needed in the design phase of SoC. These analog IPs can not
SiSoC is a 32-bit scalar RISC with Harvard architecture, 8 be implemented with FPGA. So, some external chips which
stage pipeline, virtual memory support (MMU) and support have the same function as those analog IPs are need to
AMBA bus interface specification, those IP cores which cooperate with FPGA to fulfill their function.
compatible with AMBA bus interface can integrate to the The system adopts Xilinx’s ML510 Embedded
SiSoC platform.
Development Platform as the FPGA prototyping system. There
is a Xilinx Virtex-5 FPGA, XC5VFX130T-2FFG1738C, is
II. SOC ARCHITECTURE installed on the ML510 board. In addition to the more than
130,000 logic cells, over 10,700 kb of block RAM, dual IBM
The architecture of SiSoC-based SoC design is shown in Fig.1. PowerPC 440 processors available in the FPGA [​ 2]​. The
The SoC design adopts AMBA bus to connect SiSoC synthesis results of the SiSoC processor to the XC5VFX130T
processor to peripherals and external memory subsystem. It FPGA are presented in Table 1.
consists of several modules: SiSoC Processor, DDR2 Memory
Controller, External Memory Controller, DMA, Ethernet
MAC, AHB To APB Bridge, USB, UART, RTC, GPIO,
ICTL, I2C, I2S.
Figure.1. SoC architecture

III. HARDWARE VERIFICATION

 The Bootloader program is a small piece of software that
executes soon after powering up the SoC, it will initialize the
processors, memory controllers, and other board specific
hardware varies from board to board and CPU to CPU.
Unfortunately, SiSoC processor is not in the support list of
U-Boot. In order to let the U-Boot to support the SiSoC
processor, we must edit the source code of the U-Boot, add the
low-level hardware description of the SiSoC processor to the
source code of the U-Boot, that’s the major work of
developing a processor-specific U-Boot Bootloader program.
Use the cross-compiling environment of the SiSoC platform to
compile the SiSoC processor-specified U-Boot program. The
start-up information of the U-Boot is printed in the serial
interface terminal program is shown in fig.2.
Fig.2. Start-up information of the U-Boot ​Linux is a kind of open
source operating system that is widely adopted, which kernel
may support a lot of processor architecture, such as ARM,
978-1-4577-1997-4/11/$26.00 ©2011 IEEE strongARM, MIPs, XScale, etc [​ 3]​. The kernel downloaded
Table 1. Synthesis result from the official website can not run directly in the SiSoC
hardware platform, because the SiSoC processor is not in the
Used Total %
support list of Linux. In order to transplant Linux, you need to
Slice LUTs 41783 81920 51% edit the architecture file of the CPU and add peripheral drivers
according to the SiSoC processor.
Slice Register 25383 81920 31%
The start-up information of the Linux operating
Slice 15620 20480 76% system is printed in the serial interface terminal program is
Memory (KB) 4853 10728 45% shown in fig.3.

Block RAM/FIFO 141 298 47%

The verification process of the SoC design which is

implemented in the FPGA is divided into the following three
steps:
(1) Module level verification: In order to verify the DDR2
controller, various writing and reading operations are done to
the DDR2 memory; To verify the function of peripherals,
continuous writing and reading operations are done on UART,
GPIO, and Interrupt controller logic.
Fig.3. Start-up information of the Linux OS.
(2) System level verification: In order to verify the function and
performance of the SoC design, a special code is run on the
SiSoC-based SoC design to verify the cooperation of the V.CONCLUSION
SiSoC processor, memory unit, peripherals and interrupt In this paper, we presented the methodology to
controller. verify the functionality and performance of the SiSoC-based
(3) Application level verification: Example program performing SoC design completely in a short time. Through the Xilinx’s
FFT, MUSIC are runned on the SiSoC-based SoC design to ML510 as the co-verification platform, we achieve hardware
verify the function and performance of the SoC design and software co-verification well ahead of chip fabrication and
completely. time-to-market goal.

IV. HW/SW CO-VERIFICATION REFERENCES

The best solution for hardware verification and software [1] Chen Wenwei, Li Jiao. Study On a Mixed Verification Strategy
verification is to adopt FPGA prototyping to implement for IP-Based SoC Design. 2005 Conference on High Density
HardWare/SoftWare (HW/SW) co-verification, HW/SW Microsystem Design and Packaging and Component Failure
co-verification makes the verifications run simultaneously, and Analysis. [2] Xilinx, ML510 Embedded Development Platform User
they are in the same verification platform so the two Guide, Dec.2008. [3] Rick Lehrbaum. Why
verifications are consistent, besides, the design period is embedded-linux.
shortened. http://www.li