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Aim: - Tool Used: Theory:: Experiment-5

The document describes an experiment to model a 4x1 multiplexer using Verilog. It includes: 1) Creating a data flow model and behavioral model of a 4x1 multiplexer in Verilog code. 2) Generating the RTL schematic for each model. 3) Simulating the behavioral model using a test bench and observing the output waveforms. 4) Concluding that both models successfully implemented a hardware description of a 4x1 multiplexer.

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38 views4 pages

Aim: - Tool Used: Theory:: Experiment-5

The document describes an experiment to model a 4x1 multiplexer using Verilog. It includes: 1) Creating a data flow model and behavioral model of a 4x1 multiplexer in Verilog code. 2) Generating the RTL schematic for each model. 3) Simulating the behavioral model using a test bench and observing the output waveforms. 4) Concluding that both models successfully implemented a hardware description of a 4x1 multiplexer.

Uploaded by

uday
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Experiment-5

Aim:
To write a hardware description of 4 X 1 multiplexer using data flow and behavioural
modelling.

Tool used: Xilinx simulator ISE

Theory:
The multiplexer, shortened to “MUX” or “MPX”, is a combinational logic circuit designed to
switch one of several input lines through to a single common output line by the application of
a control signal. Multiplexers operate like very fast acting multiple position rotary switches
connecting or controlling multiple input lines called “channels” one at a time to the output.

Fig. 5.1: Circuit for a 4 X 1 MUX

S1 S0 Output

0 0 I0

0 1 I1

1 0 I2

1 1 I3

Table 5.1:Truth Table for 4 X 1 MUX


Verilog Code:
1.Data Flow Modelling

module mux4(
input s0,
input s1,
input i0,
input i1,
input i2,
input i3,
output y
);
assign y = ((~s0)&(~s1)& i0)|((s0)&(~s1)& i1)|((~s0)&(s1)& i2)|((s0)&(s1)& i3);
endmodule

2.Behavioral Modelling

module mux4(
input s0,
input s1,
input i0,
input i1,
input i2,
input i3,
output reg y
);
always @(s1,s0,y)
begin
case({s1,s0})
2'b00:y=i0;
2'b01:y=i1;
2'b10:y=i2;
2'b11:y=i3;
endcase
end
endmodule

3.Test Bench

module muxtest;
reg s0;
reg s1;
reg i0;
reg i1;
reg i2;
reg i3;
wire y;
mux4 uut (
.s0(s0),
.s1(s1),
.i0(i0),
.i1(i1),
.i2(i2),
.i3(i3),
.y(y)
);
initial begin
i0 = 0;
i1 = 1;
i2 = 0;
i3 = 1;
s1=0; s0=0; #100;
s1=0; s0=1; #100;
s1=1; s0=0; #100;
s1=1; s0=1; #100;
end
endmodule

RTLs:

Fig. 5.2 RTL for 4 X 1 Mux for Data Flow Modelling


Fig 5.3: RTL for 4 X 1 MUX for Behavioral Modelling

Waveforms:

Fig 5.4 Waveform for 4 X 1 MUX

Result:

The hardware description of 4 X 1 multiplexer(MUX) was successfully implemented


using the data flow model and behavioural model.

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