AVR Timers

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TIMERS AND COUNTERS OF ATMEGA 16
D.BALAKRISHNA,
Research Assistant, IIIT-H
CHAPTER 1:
1:- Introduction.
In this lesson we will know about the introduction to timers/counters.
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Timers:-
Timers:-
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These timers are used to provide accurate delays. Secondly, it can be used to repeat
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or initiate an action after/at a known period of time. This feature is very commonly
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used in several applications. An example could be setting up an alarm which triggers
at a point of time or after a period of time.
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Counters:-
Counters:-
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The counters are used to count number of events it has occurred. We connect the
external event source to the clock pin of the counter register. Then, when an event
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occurs externally, the content of the register counter increments. In this way the
a
counter represents how many times an event has occurred..

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One thing about ATMEGA16 timers is that they can run parallel to the micro
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controller’s source code. This is possible because, Timers/counters are separate

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chips on ATMEGA 16 micro controller chip which can run independent of the
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main program, interacting via the control and counter registers, and the timer
interrupts. Timers can be configured to produce outputs directly to pre-determined
pins, reducing the processing load on ATMEGA16 micro controller.
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Timer Resolution:-
Resolution:-
Timer Resolution = (1 / Input Frequency).

Frequency).
The smallest amount of time that a timer can measure is determined by the
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frequency of the clock source which the microcontroller uses. For example, if the
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microcontroller uses a 16MHz crystal as the clock source, then the smallest time it
can measure is 1/16000000th of a second. Therefore if we measure 40 timer periods
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we would be covering a time of 1/400000 sec.
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How the time delays can be generated using Timers?
First method:-
method:-
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When we want to generate time delays, we connect the oscillator to the clock pin of
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the counter. So, when the oscillator ticks the content of the counter is incremented.
As a result, the content of the counter register represents how many ticks have
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occurred from the time we have cleared the counter. Since the speed of the
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oscillator in a microcontroller is known, we can calculate the tick period, and from
the content of the counter register we will know how much time has elapsed.
a
.s
So, one way to generate a time delay is to clear the counter at the start time and wait
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until
until the counter reaches a certain number.
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For Example:-
Example:-
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Consider a microcontroller with an oscillator with frequency of 1 MHz; in the

microcontroller, the content of the counter register increments once per
microsecond. So, if we want a time delay of 100 microseconds, we should clear the
counter and wait until it becomes equal to 100. In the microcontrollers, there is a
2
flag for each of the counters. The flag is set when the counter overflows, and it is
cleared by software.
Second method:-
method:-
The second method to generate a time delay is to load the counter register and wait
until the counter overflows and the flag is set.
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For Example:-
Example:-
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In a microcontroller with a frequency of 1 MHz, with an 8-bit counter register, if we
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want a time delay of 3 microseconds, we can load the counter register with 0xFD and
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wait until the flag is set after 3 ticks. After the first tick, the content of the register
increments to 0xFE; after the second tick it becomes 0xFF and after the third tick it
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overflows and flag is set. The content of register is 00.
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The ATMEGA16 micro controllers provide both 8bit and 16 bit timers and
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counters. So the important issue is irrespective of whether the timer/counter is in

timer or counter mode, the terms like maximum and rolls over of a timer is
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important. So in case of 8 bit counter, roll over occurs when the count reaches to
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255. In case of 16 bit counter, roll over occurs when the count reaches to 65535.
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Because of this roll over,

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• The interrupt may be provided from the timer.

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• The results in the timer register can be read for further use in the application.
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General view of timers and counters:-

counters:-
Oscillator
Counter register
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External source
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Flag
Timers / counters
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Figure 1.1:
1.1:-
.1:-General view of timers and counters
The clock source can be internal or external. If the clock source is from internal the
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frequency of the crystal oscillator is fed into the timer. So, the timer/counter is called
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timer. By choosing the external clock option the pulses can be fed into the timer so
that it can act as a counter002E
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Pins corresponding to the timers/counters:-

timers/counters:-
T0—PB0 1
T1---PB1 2
OC0 4
A
T
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0C1B--PD4
A
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0C1A—PD5 1
18
ICP1---PD6
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19 6 21 PD7—0C2
Figure 1.2:-
.2:-Pins Related To Timer Concept
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• T0 = timer0/counter0 counter source.

•
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T1 = timer1/counter1 counter source.

• OC2 = Timer/Counter2 Output Compare Match Output.
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• OC0 = Timer/Counter0 Output Compare Match Output.

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• OC1A = Timer/Counter1 Output Compare A Match Output.

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• OC1B = Timer/counter1 output compare B match output.

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• ICP1 = Input Capture Pin: The PD6 pin can act as an Input Capture pin for
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Timer/Counter1.
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CHAPTER 2:
2: Timers/Counters.
Timers/Counters.
Lesson 1 Introduction
In ATMEGA16, we have three different kinds of timers:-
Timer/Counter Type Capacity Counting capacity
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Timer0 8 Bit Timer. 0-255
Timer1 16Bit Timer. 0-65535
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Timer2 8Bit Timer. 0-255
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Depending upon the processor type the capacity of the registers varies.
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There are some basic timer registers, for the control of timers and to know the status
of timers.
Topic 2
at Timer Registers
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The basic timer registers for Timer 0 and Timer1 and Timer2 are,
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Register Type Name Description

TCNT(x) register. Timer/counter register The timer/counter
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contents can be accessed

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from this register.

a
TCCR(x) register. Timer /counter control This register is used to

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register control the function of

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Timer(x)
OCR(x) registers. Output compare register Contents of OCR(x)
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register are compared

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with the TCNT(x). When

they are equal the OCF(x)
flag will be set.
1. TCNT(x) registers:-
registers:-
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• This register is a counter. Upon reset the registers contains zero.

• It counts up with each pulse.
• The contents of the timer/counter can be accessed from this register
TCNTX).
(TCNT
• You can load the value into this register or read the value from the
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register.
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Example:-
Example:-
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TCNT0 Register (8 Bit):-
Bit):-
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7bit 6bit 5 bit
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Count value can be stored from 0 to 255 for TIMER 0 and TIMER 2
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(8 bit timers).
Count value can be stored from 0 to 65535 for TIMER 1(16 bit
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timers).
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2. TOVX flag bit:-

bit: (Timer
Timer Overflow Flag Bit)
Bit
• If the timer registers value overflows (FF TO 00) then the TOVx flag in
a
TIFR register (timer

(timer interrupt flag register) is set to 1.
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3. TCCRN Regi
Register:-
ster:- (Timer/Counter Control Register)
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Generally the timer can operate in three modes,

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• Normal mode.
• CTC mode.
• PWM mode.
i) This register is used to set the modes of operation of the timer.
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ii) This register is used to select the clock source with selected prescalar
value.
iii) This register is used to control the waveform generated by timer.
For example, to specify the timer0 to work as a timer/counter by loading

proper values into the register TCCR0.
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4. OCRx Register:
Register:- Output Compare Register
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The contents of output compare register (OCRx) are compared with the
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TCNTx. When they are equal the OCFx will be set.
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Lesson 3 Timer Concepts
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We the know the basic relation,
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hi
ks
Example:-
Example:-
a
Now suppose, we need to flash an LED eve

every
ry 10ms.This implies that its frequency is
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1/10ms = 100 Hz. Now let’s assume that we have an external crystal XTAL of 4
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MHz Hence, the CPU clock frequency is 4 MHz now, as I said that the timer counts
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from 0 to TOP. For an 8-bit timer, it counts from 0 to 255 whereas for a 16-bit timer
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it counts from 0 to 65535. After that, they overflow. This value changes at every
clock pulse.
Let’s say the timer’s value is zero now. To go from 0 to 1, it takes one clock pulse.
To go from 1 to 2, it takes another clock pu
pulse.
lse. To go from 2 to 3, it takes one more
8
clock pulse. And so on. For F_CPU = 4 MHz, time period T = 1/4M = 0.00025
msec. Thus for every transition (0 to 1, 1 to 2, etc), it takes only 0.00025 ms!
Now, as stated above, we need a delay of 10 msec. This mayb

maybee a very short delay,
but for the microcontroller which has a resolution of 0.00025 ms, its quite a long
delay! To get an idea of how long it takes, let’s calculate the timer count from the
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following formula:
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Substitute Required Delay = 10 ms and Clock Time Period = 0.00025 ms, and you
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get Timer Count = 39999. Can you imagine that? The clock has already ticked
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39999 times to give a delay of only 10 ms!
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Now, to achieve this, we definitely cannot use an 8-bit timer (as it has an upper limit
of 255, after which it overflows). Hence, we use a 16-bit timer (which is capable of
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counting up to 65535) to achieve this delay.

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The Prescalar:-
Prescalar:-
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Assuming F_CPU = 4 MHz and a 16-bit timer (MAX = 65535), and substituting in
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the above formula, we can get a maximum delay of 16.384 ms. Now what if we need
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a greater delay, say 20 ms? We are stuck?!

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Well hopefully, there lies a solution to this. Suppose if we decrease the F_CPU from
4 MHz to 0.5 MHz (i.e. 500 kHz), then the clock time period increases to 1/500k =
0.002 ms. Now if we substitute Required Delay = 20 ms and Clock Time Period =
0.002 ms, we get Timer Count = 9999. As we can see, this can easily be achieved
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using a 16-bit timer. At this frequency, a maximum delay of 131.072 ms can be

achieved. Now, the question is how do we actually reduce the frequency? This
technique of frequency division is called pre-
pre-scaling.
scaling We do not reduce the actual
F_CPU. The actual F_CPU remains the same (at 4 MHz in this case). So basically,
we derive a frequency from it to run the timer. Thus, while doing so, we divide the
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frequency and use it. There is a provision to do so in AVR by setting some bits
which we will discuss later.
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But don’t think that you can use prescalar freely. It comes at a cost. There is a trade-
trade-
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off between resolution and duration.
duration As you must have seen above, the overall
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duration of measurement has increased from a mere 16.384 ms to 131.072 ms. so
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has the resolution. The resolution has also increased from 0.00025 ms to 0.002
ms.This means each tick will take 0.002 ms. So, what’s the problem with this? The
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problem is that the accuracy has decreased. Earlier, you were able to measure
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duration like 0.1125 ms accurately (0.1125/0.00025 = 450), but now you cannot
(0.1125/0.002 = 56.25). The new timer can measure 0.112 ms and then 0.114 ms.
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No other value in between.

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So, we have to select the best prescalar,

a
.s
How to choos
choose
hoose type of Timer according to the delay required:-
required:-
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Let’s take an example. We need a delay of 184 ms (I have chosen any random
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number). We have F_CPU = 4 MHz the AVR offers us the following prescalar
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values to choose from: 8, 64, 256 and 1024. A prescalar of 8 means the effective
clock frequency will be F_CPU/8. Now substituting each of these values into the
above formula, we get different values of timer value. The results are summarized as
below:
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Required delay = 184 msec; F_CPU = 4MHZ.
Prescalar Clock frequency Timer count

8 500khz 91999
64 62.5khz 11499
256 15.625khz 2874
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1024 3906.25hz 717.25
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Now out of these four prescalar, 8 cannot be used as the timer value exceeds the
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limit of 65535. Also, since the timer always takes up integer values, we cannot
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choose 1024 as the timer count is a decimal digit. Hence, we see that prescalar
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values of 64 and 256 are feasible. But out of these two, we choose 64 as it provides
us with greater resolution. We can choose 256 if we need the timer for a greater
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duration elsewhere.
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Thus, we always choose prescalar which gives the counter value within the feasible
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limit (255 or 65535) and the counter value should always be an integer.
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• If we select the prescalar value 64 then the count value to be stored in the
a
timer register is 11499. So, here in this case 8 bit timer cannot be used and
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only the choice in ATmega 16 timer registers is 16 bit registers. So, therefore
we should consider timer register which has only 16 bit capacity that is Timer
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1 is eligible for this case.

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• According to the above example considered the 8 bit register cannot be taken
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because timer count value in all cases is above 255 values.
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Lesson 4 AVR Timers
Timer
Timer 0:-
0:-
Timer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter

module.
Features:-
Features:-
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Main features are:-
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• Single Compare Unit Counter.
• Clear Timer on Compare Match (Auto Reload).
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• Glitch-free, Phase Correct Pulse Width Modulator (PWM).
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• Frequency Generator.
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• External Event Counter.
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• 10-bit Clock Prescalar.
• Overflow and Compare Match Interrupt Sources (TOV0 and OCF0).
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Since timer is a peripheral, it can be activated by setting some bits in some

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registers.
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TCNT0 Register:
The Timer/Counter Register,

Register, shown in figure below
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Bit 7 6 5 4 3 2 1 0
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Read R/W R/W R/W R/W R/W R/W R/W R/W

/write
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Initial 0 0 0 0 0 0 0 0
value
Figure 2.4.1:
.4.1: TCNT0 Register
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The value of the counter is stored here and increases/decreases automatically.

Data can be both read/written from this register.
Now we know where the counter value lies. But this register won’t be activated
unless we activate the timer! Thus we need to set the timer up by using Timer
Counter Control Register.
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TCCR0 Register:
Register:-
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The Timer/Counter Control Register, shown in figure below
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Bit 7 6 5 4 3 2 1 0
FO W CO CO WG CS0 CS CS0
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C0 GM M0 M00 M01 2 01 0
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00 1
Read W R/W R/W R/W R/W R/W R/W R/W
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/write
Initial 0 0 0 0 0 0 0 0
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value
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Figure 4.4.2:
4.4.2: TCCR0 Register
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Clock
Clock Select Bits (CS 02: 00):-
00):-
a
Used to set the timer up by choosing proper prescalar. The possible combinations
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are shown below.

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CS02 CS01 CS00 Description

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0 0 0 No clock source (Timer/Counter stopped)

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0 0 1 ClkI/O/1 (No prescaling)

0 1 0 ClkI/O/8 (From prescaler)
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1 1 0 External clock source on T0 pin. Clock on falling
edge.
1 1 1 External clock source on T0 pin. Clock on rising
edge.
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Figure4.4.3
Figure4.4.3:
4.4.3: TCCR0 Prescalar Definitions
Example code:
code:-
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TCCR0 |= (1 << CS00); // Initializing the counter in No precaling.
precaling.
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TCCR0 |= (1 << CS02)|(1 << CS00); // set up timer with prescalar = 1024.
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Bit 6, 3 – Wgm01:00 – Wave Generation Mode:-
Mode
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We choose the type of wave mode from here as follows
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Mode WGM01 WGM00 Timer/Counter TOP Update of TOV0 Flag

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(CTC0) (PWM0) Mode of operation OCR0 Set-

Set-on
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0 0 0 Normal 0xFF Immediate MAX

1 0 1 PWM, Phase 0xFF TOP BOTTOM
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correct
2 1 0 CTC OCR0 Immediate MAX
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3 1 1 Fast PWM 0xFF TOP MAX

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Figure2
Figure2.4.4:
.4.4: - Wave Generation Mode Bit Description
Bit 5:4 – COM01:00 – Compare Match Output Mode:-

Mode:-
Controls the behavior of the OC0 (PB3) pin depending upon the WGM mode –
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Non-PWM,
Phase Correct PWM mode and
Fast PWM mode.
The selection options of non-PWM mode are as follows.
COM01 COM00 Description

0 0 Normal port operation, OC0 disconnected
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0 1 Toggle OC0 on compare match
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1 0 Clear OC0 on compare match
1 1 Set OC0 on compare match
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Figure
Figure 2.4.5:
.4.5: Compare Output Mode, non-
non-PWM
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Bit 7 – FOC0 – Force Output Compare:-
Compare:-
When set to ‘1’
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Forces an immediate compare match and affects the
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behavior of OC0 pin.

o When clear to ‘0’
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To ensure compatibility with future devices, this bit must

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be set to ‘0’.
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OCR0 Register:-
Register:-
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The Output Compare Register–

Register OCR0 Register is shown in figure below.
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Bit 7 6 5 4 3 2 1 0
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/write
Initial 0 0 0 0 0 0 0 0
value
Figure2
Figure2.4.6:
.4.6: OCR0 Register
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The value to be compared (max 255) is stored in this register.
TIMSK
TIMSK Register:-
Register:-
The Timer/Counter Interrupt Mask Register, shown in figure below:
Bi 7 6 5 4 3 2 1 0
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OC T TI OCI OCI TO O T
IE0 OI CI E1A E1B IE1 CI OI
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E2 E1 E1 E0
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/write
Initial 0 0 0 0 0 0 0 0
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value
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Figure
Figure2
ure2.4.7:
.4.7: - TIMSK Register
It is a common register for all the three timers.
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Bits (1:0):-
(1:0):
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• Correspond to TIMER0
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• Bit 0:
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o Setting the bit TOIE0 to ’1′ enables the TIMER0 overflow

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interrupt.
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o
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• Bit 1:
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o OCIE0 – Timer/Counter0 Output Compare Match Interrupt

Enable
Enables the firing of interrupt whenever a compare
match occurs.
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Bits (5:2):-
(5:2):-
• Correspond to TIMER1.
• Bit 2 – TOIE1 – Timer/Counter1 Overflow Interrupt Enable bit
o Enables the overflow interrupt of TIMER1.
• Other bits are related to CTC mode
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o Bit 4:3 – OCIE1A:
OCIE1A: B – Timer/Counter1, Output Compare
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A/B Match Interrupt Enable bits.
Enabling it ensures that an interrupt is fired whenever a
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match occurs.
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Since there are two CTC channels, we have two
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different bits OCIE1A and OCIE1B for them.
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Bit 5-
5- TICIE1 Timer 1 Input Capture Interrupt Enable
TICIE1= 0 Disables Timer l input capture interrupt
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TICIE1= I Enables Timer 1 input capture interrupt

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Bits (7:6):
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• Setting the bit TOIE2 to ’1′ enables the TIMER0 overflow
a
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interrupt.
• OCIE0 – Timer/Counter0
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Timer/Counter0 Output Compare Match Interrupt

Enable
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o Enables the firing of interrupt whenever a compare match

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occurs.
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TIFR Register:-
Register:-
The Timer/Counter Interrupt Flag Register, shown in figure below.
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Bi 7 6 5 4 3 2 1 0
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OC TO IC OCF OCF TO O TO
F2 V2 F1 1A 1B V1 CF V0
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0
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/writ
ed
e
Initia 0 0 0 0 0 0 0 0
l
hi
value
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Figure 2.4.8:
.4.8: TIFR Register
a
.s
This is also a register shared by all the timers.

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Bits (1:0):
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• Bit 0:
o TOV0 (Timer/Counter1
Timer/Counter1 Overflow Flag
Flag)
lag bit is set (one)
whenever TIMER0 overflows.
This bit is reset (zero) whenever the Interrupt Service
Routine (ISR) is executed.
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If there is no ISR to execute, we can clear it manually

by writing one to it.
• Bit 1:
1
o OCF0 – Output Compare Flag 0
Sets whenever a compare match occurs.
It is cleared automatically whenever the corresponding
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ISR is executed.
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Alternatively it is cleared by writing ‘1’ to it.
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Bits (5:2):
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• Correspond to TIMER1.
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• Bit 2 – TOV1 – Timer/Counter1 Overflow Flag bit is set to 1
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whenever the timer overflows
o This bit is reset (zero) whenever the Interrupt Service Routine
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(ISR) is executed.
o If there is no ISR to execute, we can clear it manually by
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writing one to it.

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• Bit 4:3 – OCF1A: B – Timer/Counter1, Output Compare A/B

a
Match Flag Bit.

Bit
.s
o This bit is set (one) by the AVR whenever a match occurs

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TCNT1 becomes equal to OCR1A (or OCR1B).

It is cleared automatically whenever the corresponding
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Interrupt Service Routine (ISR) is executed.

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Alternatively, it can be cleared by writing ’1′ to it!
Bits (7:6):
• TOV2 bit is set (one) whenever TIMER2 overflows.
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o This bit is reset (zero) whenever the Interrupt Service Routine

(ISR) is executed.
o If there is no ISR to execute, we can clear it manually by
writing one to it.
Example:
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Flash an LED every 8 ms and we have an XTAL of 16 MHz
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We can use a prescalar of 1024. Now refer to the descriptions of clock select
bits as shown in the TCCR0 register.
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#include <avr/io.h>
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void timer0_init()
at
{
// set up timer with prescalar = 1024
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TCCR0 |= (1 << CS02)|(1 << CS00);
// initialize counter
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TCNT0 = 0;
}
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int main(void)
{
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// connect led to pin PC0

DDRC |= (1 << 0);
a
// initialize timer
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timer0_init();
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// loop forever
while(1)
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{
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// check if the timer count reaches 124

if (TCNT0 >= 124)
{
PORTC ^= (1 << 0); // toggles the
led
TCNT0 = 0; // reset counter
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}
}
}
TIMER1:-
TIMER1:-
The 16-bit Timer/Counter unit allows accurate program execution timing (event
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management),
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Wave generation, and signal timing measurement.
Features:-
Features:-
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The main features are:
• True 16-bit Design (i.e., allows 16-bit PWM).
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• Two Independent Output Compare Units.
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• Double Buffered Output Compare Registers.
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• One Input Capture Unit.

• Input Capture Noise Canceller.
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• Clear Timer on Compare Match (Auto Reload).

ks
• Glitch-free, Phase Correct Pulse Width Modulator (PWM).

• Variable PWM Period.
a
.s
• Frequency Generator.
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• External Event Counter.

• Four Independent Interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1).
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In addition to the usual timer/counter, Timer 1 contains one 16 bit input capture
register and two 16-bit outputs compare registers.
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The input capture register is used for measuring pulse widths or capturing
times. The output compare registers are used for producing frequencies or pulses
from the timer/counter to an output pin on the microcontroller.
TCNT1 Register:
The Timer/Counter1 Register, shown in figure below.
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Bit 7 6 5 4 3 2 1 0
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TCNT
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1
[15:8]
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TCNT
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1
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[7:0]
Read R/W R/W R/W R/W R/W R/W R/W R/
ed
/write W
Initial 0 0 0 0 0 0 0 0
hi
value
ks
Figure2
Figure2.4.9:
.4.9: - TCNT1 Register.
It is 16 bits wide since the TIMER1 is a 16-bit register. TCNT1H represents the
a
HIGH byte whereas TCNT1L represents the LOW byte. The timer/counter value
.s
is stored in these bytes.

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Timer/counter control register 1 (TCCR1):-

(TCCR1):-
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The ATMegal6 timer /control register for Timer 1 is actually composed of two
registers, TCCR1A and TCCR1B.
• TCCR1A controls the compare modes and the pulse width modulation
modes of Timer1.
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• TCCR1B controls the prescalar and input multiplexer for Timer 1, as

well as the input capture modes.
TCCR1A Register:-
Register:-
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The Timer/Counter1 Control Register A, shown in figure below.
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Bit 7 6 5 4 3 2 1 0
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CO CO CO CO FOC FO W W
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M1 M1 M1 M1B 1A C1 G GM
A1 A0 B1 0 B M1 10
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/write
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Initial 0 0 0 0 0 0 0 0
value
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Figure
Figure2
ure2.4.10:
.4.10: TCCR1A Register
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• The behavior changes depending upon the following modes:

a
o Non-PWM mode (normal / CTC mode).

.s
o Fast PWM mode.

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o Phase Correct / Phase & Frequency Correct PWM mode.

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• Bit 7:6 – COM1A1:0 and Bit 5:4 – COM1B1:0

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o Compare Output Mode for Compare Unit A/B.

A/B
o These bits control the behavior of the Output Compare (OC)
pins.
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COM1A1/ COM1A0/ Description

COM1B1
COM1B1 COM1B0
0 0 Normal port operation, OC1A/OC1B disconnected.
0 1 Toggle OC1A/OC1B on compare match.
1 0 Clear OC1A/OC1B on compare match (Set output to
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low level)
1 1 Set OC1A/OC1B on compare match (Set output to
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high level)
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Table
Table4.4.11:
4.4.11: Compare Output Mode, non-
non-PWM
at
• Bit 3:2 – FOC1A: B – Force Output Compare for Compare Unit A/B.
A/B
uc
o These bits are write only bits.
o They are active only in non-PWM mode.
ed
o For ensuring compatibility with future devices, these bits must be

hi
set to zero (which they already are by default).

o Setting them to ‘1’ will result in an immediate forced compare
ks
match and the effect will be reflected in the OC1A/OC1B pins.

a
o The thing to be noted is that FOC1A/FOC1B will not generate

.s
any interrupt, nor will it clear the timer in CTC mode.

w
TCCR1B Register:-
Register:-
w
The Timer/Counter1 Control Register B shown in figure below.

w
Bit 7 6 5 4 3 2 1 0
IC ICE - WG WG CS1 CS CS1
NC S1 M13 M12 2 11 0
1
Read R/W R/W R R/W R/W R/W R/W R/W
24
/write
Initial 0 0 0 0 0 0 0 0
value
Figure
Figure2
ure2.4.12:
.4.12: - TCCR1B Register
The bit 2:0 – CS12:10 are the Clock Select Bits of TIMER1. Their selection
m
is as follows.
co
n.
io
at
0 1 1 uc ClkI/O/64 (From prescaler)
ed

edge.
hi

ks
edge.
a
Figure 4.4.13:
4.4.13: - TCCR1B Prescalar Definitions
.s
Bits 7:6 in TCCR1B:-

TCCR1B:-
w
• ICNC1 (Input Capture Noise Canceller) (1 = enabled)

w
• ICES1 (Input Capture Edge Select) (1 = rising edge, 0 = falling edge)

w
Bits 1:0 in TCCR1A (WGM11 & WGM11) and
Bits 4:3 in TCCR1B (WGM13 & WGM12) are Wave Generation Mode Bits
which are used to select mode shown in figure below.
25
Mo W WG WGM WGM Timer/Counter Mode of Top Update TO

de G M12 11 10 operation of V1
M1 (CTC (PW (PWM OCR1x Flag
3 1) M11) 10) Set
on
0 0 0 0 0 Normal 0xFFF Immedi MA
F ate X
m
1 0 0 0 1 PWM, Phase Correct, 8- 0x00F TOP BO
bit F TT
co
OM
n.
bit F TT
io
OM
at
bit F TT
uc OM
4 0 1 0 0 CTC OCR1 Immedi MA
A ate X
ed
5 0 1 0 1 Fast PWM, 8-bit 0x00F TOP TO

F P
hi

ks
F P
a
F P
.s
8 1 0 0 0 PWM, Phase & ICR1 BOTT BO

Frequency correct OM TT
w
OM
w
9 1 0 0 1 PWM, Phase & OCR1 BOTT BO

Frequency correct A OM TT
w
OM
10 1 0 1 0 PWM, Phase Correct ICR1 TOP BO
TT
OM
11 1 0 1 1 PWM, Phase Correct OCR1 TOP BO
26
A TT
OM
12 1 1 0 0 CTC ICR1 Immedi MA
ate X
13 1 1 0 1 Reserved - - -
14 1 1 1 0 Fast PWM ICR1 TOP TO
P
m
15 1 1 1 1 Fast PWM OCR1 TOP TO
co
A P
n.
Figure2
Figure2.4.14:
.4.14: - Wave Generation Mode Bit Description
io
In pin configuration of ATMEGA16/32, we can see the pins PB3, PD4, PD5
at
and PD7. Their special functions are mentioned in the brackets (OC0, OC1A,
OC1B and OC2). These are the Output Compare pins of TIMER0, TIMER1 and
uc
TIMER2 respectively shown in figure below.
ed
hi
ks
OCR1A and OCR1B Registers:-

Registers:-
a
We must tell the AVR to reset the timer as soon as its value reaches such and such
.s
value. So, the question is, how do we set such and such values? The Output
w
Compare Register 1A – OCR1A and the Output Compare Register 1B – OCR1B

w
are utilized for this purpose.

w
Bit 7 6 5 4 3 2 1 0
OCR 15:8 OCR1A
1A H
OCR 7:0 OCR1A
27
1A L
Rea R/W R/W R/W R/W R/W R/W R/W R/W
d
/wri
te
Initi 0 0 0 0 0 0 0 0
m
al
valu
co
e
n.
Figure
Figure2
ure2.4.15:
.4.15: OCR1A Register
io
Bit 7 6 5 4 3 2 1 0
at
OCR 15:8 OCR1B
1B
uc
H
OCR 7:0 OCR1B
ed
1B L
Rea R/W R/W R/W R/W R/W R/W R/W R/W
hi
d
ks
/wri
te
a
Initi 0 0 0 0 0 0 0 0
.s
al
valu
w
e
w
Figure2
Figure2.4.16:
.4.16: OCR1B Register
w
Since the compare value will be a 16-bit value (in between 0 and 65535), OCR1A
and OCR1B are 16-bit registers. In ATMEGA16/32, there are two CTC channels –
A and B. We can use any one of them or both. Let’s use OCR1A.
28
TIMER 2:
Features:-
Features:-
• Single Compare unit Counter
• Clear Timer on Compare Match (Auto Reload)
• Glitch-free, Phase Correct Pulse Width Modulator (PWM)
m
• Frequency Generator
• 10-bit Clock Prescaler
co
• Overflow and Compare Match Interrupt Sources (TOV2 and OCF2)
n.
• Allows clocking from External 32 kHz Watch Crystal Independent of
the I/O Clock
io
• TIMER2 is an 8-bit timer (like TIMER0).
at
• Most of the registers are similar to that of TIMER0 registers. Apart
uc
from that, TIMER2 offers a special feature which other timers don’t
that is Asynchronous Operation.
ed
Operation
• Timer 2 can be used as timer 1 or timer 0 but it can act as Real Time
hi
Counter, when the 32.768 kHz connected to Tosc1 and Tosc2 pins
ks
(PORT C) of ATMEGA16 and set AS2 bit.

• Asynchronous operation is controlled by ASSR register.
a
.s
- - - - AS2 TCNT2UB OCR2UB TCR2UB

w
w
If AS2 = 1,
1 Timer2/counter2 is clocked from a crystal oscillator connected to
w
the timer oscillator1 (TOSC1) pin.
If AS2 = 0, Timer2/counter2 is clocked from internal clock oscillator.
29
In timer0 when cs02 – cs00 have values 110 and 111, Timer 0 counts the
external events. But , in Timer 2 the values of cs are different compared to
Timer 0.
TCNT2 Register:
In the Timer/Counter register shown in figure below.
m
Bit 4
co
6 5 3
7 4 2 1 0
n.
TCNT2[7:0]
io
Read\
Read\Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial 0 0 0 0 0 0 0 0
at
Value uc
Figure2
Figure2.4.17:
.4.17: - TCNT2 Register
ed
TCCR2 Register:-
Register:-
hi
The Timer/Counter
Timer/Counter Control Register is shown in figure below.
ks
Bit 4
7 6 5 4 3
a
2 1 0
.s
FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20

Read\
Read\Write W R/W R/W R/W R/W R/W R/W R/W
w
Initial 0 0 0 0 0 0 0 0
w
Value
w
Figure 2.4.18:
.4.18: TCCR2 Register
In TIMER0/1 the prescalar available are 8, 64, 256 and 1024, whereas in
TIMER2, we have 8, 32, 64, 128, 256 and 1024.
30
The bit 2:0 – CS22:20 are the Clock Select Bits of TIMER2. Their selection
is as follows.

0 0 1 ClkT2S/1 (No prescalar)
m
0 1 0 ClkT2S/8 (From prescalar)
co
n.
io
at
1 1 1 uc ClkT2S/1024 (From prescalar)
Figure 2.4.19:
.4.19: Clock Select Bit Description
The mode or counting sequence is determined by setting WGM21 and WGM20.
ed
WGM21 WGM20 TIMER2 MODE

0 0 NORMAL
hi
0 1 CTC
1 0 PWM PHASE
ks
CORRECT
1 1 FAST PWM
a
.s
Figure 2.4.20:
2.4.20: Mode Selection Bit Description
w
w
w
31
CHAPTER 3
TIMER MODES
Lesson 1:
1: Introduction
Timers are basically used to,
o Produce the delay.
m
o Counts the events from external world.
o It can generate waveforms.
co
o It can measure the waveform period.
n.
The above applications can be done using
using all the timers present in the ATMEGA16
io
micro controller.
at
The above tasks listed are categorized under the section called modes. So , it can be
uc
said that the timers have four modes.
ed
1. Normal mode
2. CTC mode.
hi
3. Fast PWM mode.

ks
4. Phase Correct PWM mode.

a
Lesson 2: Normal mode

.s
w
w
w
32
Figure3
Figure3.2.1:
.2.1: - The timer or counter 0 in NORMAL MODE
o The contents of the timer/counter increments with each clock.

o It counts up until it reaches its maximum of 0XFF.
o When it rolls over from 0XFF to 0X00, it sets high a flag bit
called TOVO (timer over flow flag).
m
Steps to Program Timer0 in Normal Mode
co
Step 1:-
1:- Load the TCNT0 register with initial value.
n.
Step 2:-
2:- Load the TCCR0 register,
io
at
• Indicating which mode (8 bit or 16 bit) is to be used.
uc
• Prescalar option.
ed
Step 3:-
3:- Keep monitoring the timer overflow flag (TOV0) to see if it is raised get
out of the loop.
hi
Step 4:-
4: Stop the timer by disconnecting the clock source TCCR0.
ks
Step 5:-
5: clear the TOV0 flag for the next round.
a
.s
Step 6:-
6: go back to step1 to load TCNT0 again.
w
The above procedure can also be applied to Timer 1 and Timer2.

w
w
Example 1:-
1:-
The led blinking program for delay of 3 sec using Timer 1 Normal
Mode using the XTAL = 8MHZ.
33
#include<avr/io.h>
#include<util/delay.h>
void delay3(void);
void main(void)//START MAIN FUNCTION
m
{
co
DDRB|=0XFF;//MAKE PROT B AS OUTPUT PORT
while(1)//loop
n.
{
io
PORTB|=0x01;//LED CONNECTED TO PORTB 0 PIN GETS THE
at
SUPPLY uc
delay3();
PORTB|=0x00;//NO SUPPLY TO THE LED'S

ed
delay3();
hi
}//WHILE LOOP CLOSE

ks
}//MAIN FUNCTION END

a
void delay3()//START DELAY FUNCTION

.s
{
w
TCNT1H|=0XA4;//TIMER1 REGISTER LOADED WITH A

w
VALUE
w
TCNT1L|=0X71;
TCCR1A|=0X00; //INTIALISE THE TIMER 1 WITH NORMAL

MODE,1024 PRESCALAR
TCCR1B|=0X05;
34
while ((TIFR&(1<<TOV1))==0);//CHECK WHETHER THE TFV1

FLAG IS OVERFLOWN
TCCR1B=0;//IF YES THEN CLEAR THE TCCR1B REG
TIFR = (0X01<<TOV1);//CLEAR THE TOV11 FLAG BIT
}//CLOSE DELAY FUNCTION
m
To get the 3 sec delay using timer 1 in the above mentioned example, TCNTI =
co
0XA471 is loaded. How the value is calculated?
n.
The F_CPU frequency considered is 8MHZ.
io
Then according to the formula,
at
uc
ed
Required delay given = 3 seconds,

hi
ks
Clock time period = 1/8MHZ

a
the timer count value is = 23999999.

.s
No timer belongs to ATMEGA 16 has the capacity to load the val

value
ue 23999999. So
w
we should switch over to the prescalar option.

w
w
Prescalar Frequency / Time Timer Count

prescalar
8 1MHZ 1Usec 2999999
64 125000 8 USec 374999
35
256 31250 32Usec 93750

1024 7812.5 128Usec 23436
In the above table the last column has the Timer Count values.
The timer 1 has capability to store the value up to 65535.
m
The timer 0 and timer 2 have the capability to store the value up to
co
255.
n.
• When prescalar value is 8 then timer count value is 2999999. This
io
value cannot be stored in any timer register. So neglect it.
at
uc
ed

hi
value can be stored in timer 1 register but not in timer 0 register.

ks
So timer 1 is selected for producing the delay of 3 sec.

a
.s
• The hex value to be stored in TCNT1 register

register is,
w
23436-----
23436-----0X5B8C
-----0X5B8C
FFFF-
FFFF-5B8C = A473.
w
w
The A473 is loaded into the TCNT1 register.
36
Lesson 3:
3: CTC MODE
We consider timer 1 is considered for the explanation of CTC mode.
The timer 1 is a 16 bit timer. It has the timer counter register TCNT1 and
two OCR1 registers called OCR1A and OCR1B. Both are 16 bit registers. To
control these compare registers there must be required two TCCRn registers
m
of 16 bit size. They are TCCR1A and TCCR1B registers.
co
n.
io
at
uc
ed
Figure 3.3.1: - The timer or counter

counter 0 in CTC MODE
hi
ks
The timer counts up until the content of the TCNT1 register becomes equal to the
content of OCR1A register. Then the timer will be cleared when the
a
next clock occurs. The OCF1A flag will be set as a result of compare
.s
match.
w
TCCR1A and TCCR1B

TCCR1B Registers:
w
w
We are already aware of the Clock Select Bits – CS12:10 in TCCR1B.

Hence, right now, we are concerned with the Wave Generation Mode Bits –
WGM13:10.
WGM13:10 These bits are spread across both the TCCR1 registers (A and B).
Thus we need to be a bit careful while using them. Their selection is as follows:
37
M WG WG WGM WGM Timer/Counter Mode of Top Update TOV1

o M13 M12 11 10 operation of Flag Set
d (CTC (PWM (PWM OCR1x on
e 1) 11) 10)
0 0 0 0 0 Normal 0xFFF Immedia MAX
F te
1 0 0 0 1 PWM, Phase Correct, 8- 0x00FF TOP BOTT
m
bit OM
co
2 0 0 1 0 PWM, Phase Correct, 9- 0x01FF TOP BOTT
bit OM
3 0 0 1 1 PWM, Phase Correct, 0x03FF TOP BOTT
n.
10-bit OM
io
4 0 1 0 0 CTC OCR1 Immedia MAX
A te
at
5 0 1 0 1 Fast PWM, 8-bit 0x00FF TOP TOP
uc
ed
8 1 0 0 0 PWM, Phase & ICR1 BOTTO BOTT

Frequency correct M OM
9 1 0 0 1 PWM, Phase & OCR1 BOTTO BOTT
hi
Frequency correct A M OM
ks
1 1 0 1 0 PWM, Phase Correct ICR1 TOP BOTT

0 OM
a
1 1 0 1 1 PWM, Phase Correct OCR1 TOP BOTT

.s
1 A OM
1 1 1 0 0 CTC ICR1 Immedia MAX
w
2 te
w
1 1 1 0 1 Reserved - - -
3
w
1 1 1 1 0 Fast PWM ICR1 TOP TOP

4
1 1 1 1 1 Fast PWM OCR1 TOP TOP
5 A
Figure 3.3.2
.3.2: Wave Generation Mode Bit Description
38
We can see that there are two possible selections for CTC Mode. Practically,
both are the same, except the fact that we store the timer compare value in different
registers. Right now, let’s move on with the first option (0100). Thus, the
initialization of TCCR1A and TCCR1B is as follows.
TCCR1A |= 0; // not required since WGM11:0, both are zero (0)
m
TCCR1B |= (1 << WGM12)|(1 << CS11)|(1 << CS10); // Mode = CTC,
co
Prescaler = 64
n.
OCR1A and OCR1B Registers:
io
We must tell the AVR to reset the timer as soon as its value reaches to the
at
value stored in the OCR1A register. So, the question is, how do we set such values?
uc
The Output Compare Register 1A – OCR1A and the Output Compare Register 1B
– OCR1B are utilized for this purpose.
ed
Since the compare value will be a 16-bit value (in between 0 and 65535),
hi
OCR1A and OCR1B are 16-bit registers. In ATMEGA16/32, there are two CTC
channels – A and B. We can use any one of them or both. Let’s use OCR1A.
ks
Example:
a
.s
OCR1A = 24999; // timer compare value

w
TIFR Register:
w
w
Figure 3.3.3 :-
:- TIFR register
39
We are interested in Bit 4:3 – OCF1A: B – Timer/Counter1, Output

Compare A/B Match Flag Bit.
Bit This bit is set (one) by the AVR whenever a match
occurs i.e. TCNT1 becomes equal to OCR1A (or OCR1B). It is cleared
automatically whenever the corresponding Interrupt Service Routine (ISR) is
executed. Alternatively, it can be cleared by writing ’1′ to it!
m
Using Interrupts with CTC Mode:
co
In the previous methodology, we simply used the CTC Mode of operation.
We used to check every time for the flag bit (OCF1A). Now let’s shift this
n.
responsibility to the AVR itself! Yes, now we do not need to check for the flag bit at
io
all! The AVR will compare TCNT1 with OCR1A. Whenever a match occurs, it sets
at
the flag bit OCF1A, and also fires an interrupt! We just need to attend to that
uc
interrupt, that’s it.
There are three kinds of interrupts in AVR –

ed
• Overflow,
hi
• Compare
• Capture.
ks
We have already discussed the overflow interrupt.

a
TIMSK Register:
.s
w
w
w
Figure 3.3.4 :-
:- TIMSK register
40
The Bit 4:3 – OCIE1A: B – Timer/Counter1, Output Compare A/B Match

Interrupt Enable bits are of our interest here. Enabling it ensures that an interrupt is
fired whenever a match occurs. Since there are two CTC channels, we have two
different bits OCIE1A and OCIE1B for them.
Whenever a match occurs (TCNT1 becomes equal to OCR1A = 24999), an
m
interrupt is fired (as OCIE1A is set) and the OCF1A flag is set. Now since an
co
interrupt is fired, we need an Interrupt Service Routine (ISR) to attend to the
interrupt. Executing the ISR clears the OCF1A flag bit automatically and the timer
n.
value (TCNT1) is reset.
io
Example:-
Example:-Without
Without Interrupts
at
Program that shows how the led that is connected to the PORTB.1 pin blinks with
uc
3 seconds delay ctc mode, timer1, 1024 PRESCALAR.
ed
//F_CPU=8MHZ
hi
#include<avr/io.h> //AVR INPUT AND OUTPUT HEADER FILE

ks
#include<util/delay.h> //DELAY HEADER FILE

a
void delay(void); //PROTOTYPE DECLARATION

.s
int main(void) //START OF THE MAIN PROGRAM

w
{
w
w
DDRB|=0XFF; //MAKE THE PORTB AS OUTPUT PORT
while(1) //WHILE LOOP
PORTB=0b00000010; //LED ON OF PIN1 OF PORTB
41
delay(); //DELAY FUNCTION CALL
PORTB=0b00000000; //LED OFF OF PIN1 OF PORTB
delay(); //DELAY
m
}
co
n.
void delay() //FUNCTION DEFINITION
io
{
at
TCNT1=0X0000; //TIMER 1A IS LOADED WITH 0 VALUE
uc
OCR1A=0X5B8C; // OCR1A IS LOADED WITH 999 IN DECIMAL
TCCR1A=0X00; //CTC MODE,NO PRESCALAR,TIMER1 IS SET

ed
USING THIS TCCR1A AND TCCR1B REGISTERS

hi
TCCR1B=0X0D;
ks
while((TIFR&(1<<OCF1A))==0);
{
a
.s
PORTB=0X01;
w
_delay_ms(500);
w
PORTB=0X00;
w
_delay_ms(500);
TIFR=(1<<OCF1A); //CLEARED THE FLAG OCF1A
TCCR1B=0X00; //CLEARED THE REGISTER TO STOP THE TIMER

42
OCR1A=0X00; //CLEARED THE OUTPUT COMPARE REGISTER
} //END OF DELAY FUNCTION.
Using Hardware CTC Mode:
In the pin configuration of ATMEGA16/32, we can see the pins PB3, PD4,
PD5 and PD7. Their special functions are mentioned in the brackets (OC0, OC1A,
m
OC1B and OC2). These are the Output Compare pins of TIMER0, TIMER1 and
co
TIMER2 respectively.
n.
Here TCCR1A Register plays major role to operate this mode.
io
at
uc
ed
Figure 3.3.5 :-
:- TCCR1A register
hi
ks
Now time for us to concentrate on Bit 7:6 – COM1A1:0 and Bit 5:4
5:4 –
a
COM1B1:0 – Compare Output Mode for Compare Unit A/B.

A/B These bits control
.s
the behavior of the Output Compare (OC) pins. The behavior changes depending
w
upon the following modes:

w
• Non-PWM mode (normal / CTC mode)

w
• Fast PWM mode

• Phase Correct / Phase & Frequency Correct PWM mode
Right now we are concerned only with the CTC mode.
43
COM1A1/ COM1A0/ Description

COM1B1 COM1B0
0 0 Normal port operation, OC1A/OC1B disconnected.
0 1 Toggle OC1A/OC1B on compare match.
1 0 Clear OC1A/OC1B on compare match (Set output to low
m
level)
1 1 Set OC1A/OC1B on compare match (Set output to high
co
level)
n.
Figure 3.3.6 :-
:- compare match table
io
at
• We choose the second option (01). No need to check any flag bit, no need to
uc
attend to any interrupts, nothing. Just set the timer to this mode. Whenever a
ed
compare match occurs, the OC1A pin is automatically toggled.
But we need to compromise on the hardware. Only PD5 or PD4 (OC1A or

hi
OC1B) can be controlled this way, which means that we should connect the LED to
ks
PD5 (since we are using channel A) instead of PC0 or else.

a
Example Code:
.s
#include <avr/io.h>
w
#include <avr/interrupt.h>
w
// initialize timer, interrupt and variable

w
void timer1_init()
{
// set up timer with prescaler = 64 and CTC mode
TCCR1B |= (1 << WGM12)|(1 << CS11)|(1 << CS10); CS10);
// set up timer OC1A pin in toggle mode
TCCR1A |= (1 << COM1A0);
// initialize counter
44
TCNT1 = 0;
// initialize compare value
OCR1A = 24999;
}
int main(void)
{
DDRD |= (1 << 5); 5); // connect led to pin PD5
m
timer1_init();
timer1_init();//
); initialize timer
while(1) // loop forever
co
{
// do nothing
n.
// whenever a match occurs
// OC1A is toggled automatically!
io
// no need to keep track of any flag bits or ISR
}
at
} uc
Forcing Compare Match:
ed
Bit 3:2in TCCR1A – FOC1A: B – Force Output Compare for Compare Unit
hi
A/B.
A/B
ks
• These bits are write only bits.

• They are active only in non-PWM mode.
a
.s
• For ensuring compatibility with future devices, these bits must be set to
w
zero (which they already are by default).

• Setting them to ‘1’ will result in an immediate forced compare match
w
and the effect will be reflected in the OC1A/OC1B pins.

w
• The thing to be noted is that FOC1A/FOC1B will not generate any

interrupt, nor will it clear the timer in CTC mode.
45
CTC mode - Timer 0/

0/ Timer 2:
In this section we will discuss about the registers only. CTC mode of TIMER
0/ 2 is exactly in the same way of TIMER 1. So we will discuss about TIMER 0 now.
TCCR0 Register:
m
The Timer/Counter0 Control Register–
Register TCCR10 Register is as follows:
co
• Bit 6:3 – WGM01:00 – Wave Generation Mode – Just like in
TIMER1, we choose the type of wave mode from here as follows.
n.
Choose 10 for CTC mode.
io
o
at
uc
ed

hi
Figure 3.3.7:
.3.7: Compare Output Mode, non-
non-PWM
ks
• Bit 7 – FOC0 – Force Output Compare – This bit,

a
When set to ‘1’ forces an immediate compare match and

.s
affects the behavior of OC0 pin.

w
w
o For ensuring compatibility with future devices, this bit must

be set to ‘0’.
w
• Bit 2:0 – CS02:0 – Clock Select Bits
46
OCR0 Register:
The Output Compare Register–

Register OCR0 Register is as follows:
m
co
Figure
Figure 5.3.8:
5.3.8: OCR0 Register
n.
The value to be compared (max 255) is stored in this register.
io
TIMSK Register:
at
The Timer/Counter Interrupt Mask–
uc Mask TIMSK Register is as follows:
ed
hi
Figure
Figure 3.3.9:
.3.9: TIMSK Register
ks
The Bit 1 – OCIE0 – Timer/Counter0 Output Compare Match Interrupt

a
Enable enables the firing of interrupt whenever a compare match occurs.

.s
w
TIFR Register: The Timer/Counter Flag Register– TIFR is as follows:

w
w
Figure
Figure 3.3.10:
.3.10: TIFR Register
47
The Bit 1 – OCF0 – Output Compare Flag 0 is set whenever a compare

match occurs. It is cleared automatically whenever the corresponding ISR is
executed. Alternatively it is cleared by writing ‘1’ to it.
CHAPTER 4
WAVE GENERATION MODE USING TIMERS
m
co
Lesson 1: Introduction
This topic helps you to understand the concept like how to generate the square wave
n.
using the in built feature of AVR timers. The square wave can be generated from the
io
AVR port pins. By using some program we toggle 0 and 1from a pin of the micro
at
controller with some delay provided, so that we can obtain the square wave from
uc
that pin.
• There are four pins in ATMEGA16 micro controller used for generate the
ed
waveform.
hi
• Each pin is operated by their corresponding pin only.

ks
•
a
Pins Pin number on Timer

.s
ATMEGA16
w
OCO (PB3) 4 TIMER 0

w
0C1A(PD5) 19 TIMER 1
OC1B(PD4) 18 TIMER 1
w
OC2(PD7) 21 TIMER2
Figure 4.1.1:-
.1.1:- pin description of OC0, OC1A, OC1B, OC2 pins.
There are different modes of timers where wave form a be generated.
48
Mode number Mode name

1 Normal mode
2 CTC mode
3 Phase correct PWM mode
4 Fast PWM mode
m
Figure 4.1.2:-
.1.2:- timer modes
co
Here, the toggling the pin with some delay is enough to produce the square wave
form. So, delay can be produced by using the Normal mode and CTC mode. So we
n.
have seen earlier that the concept how to produce the delay using two modes. The
io
better option is to use the CTC mode than normal mode to have delay, to produce
at
the waveform from a pin.
When the Timer is triggered, register TCNTx counts the value constantly as timer
uc
started. Each timer has an OCRx (Output Compare Register), which is continuously
ed
compared with TCNTx register. In CTC mode whenever match occurs, OCFx
(Output Compare Flag) will set to 1. If continuous wave form generation is required,
hi
OCFx must be reset again. Alternatively, if OCIEx (Output Compare interrupt) and
ks
Global interrupt flags in SREG are set, OCFx will reset automatically after interrupt
execution.
a
.s
For example if we consider the Timer0 to produce the waveform then, OCR0
register is used as comparison register and OC0 pin is used to output the waveform
w
signal.
w
w
The bits WGM0 [1:0] are programmed to select waveform generation mode
Mode number WGM[1:0] Mode name

1 00 Normal mode
2 01 Phase correct PWM mode
49
3 10 CTC mode
4 11 Fast PWM mode
Figure 4.1.3:-
.1.3:- Waveform generation mode
There is a provision of selecting the functionality of OC0 pin.
The below table shows the functionalities.
m
co
COM[1:0] DESCRIPTION
DESCRIPTION
1 Normal, OC0 disconnected
n.
2 Toggle OC0 on compare match
io
at
3 uc Clear OC0 on compare match
4 Set OC0 on compare match

ed
hi
ks
OCRx TCNTx
a
.s
8 bit comparator
w
w
OCFx Interrupt request

w
TCNTx
Wave
TCNTx Bottom generator OCx
OCx
FOCx 50
Figure 4.1.4:
.1.4: - Wave Generator of 8 bit timer
Steps To Generate Waveform Using Timer 0:-

0:-
• For each register there is at least an OCRx register (like OCR0 for timer 0).
m
The value of the register (OCRx) is constantly compared with the TCNTx
co
register, when match occurs, OCFx flag is set.
n.
• Each timer has waveform generator. This waveform generator can generate
io
the waves on OCx pin.
• The WGMx and COMx of the TCCRx register can determine the how the
waveform generator works.
at
uc
• When TCNTx register reaches top or bottom or compare match occurs, the
ed
waveform generator is informed. Then wave generator changes the state of the
OC0 pins according to the mode of timer (WGM00, WGM01) and compare
hi
output mode (COM01, COM00) bits.

ks
• For timer 0 the wave generator generates the waveform on OC0.

a
Example: -
.s
The square wave generated from Pinb.4 (OC0) of 32 kHz, timer 0, ctc mode.
w
//XTAL=12MHZ
w
//concept:
//concept: waveform generation without using interrupts
w
#include<avr/io.h> //for input and output headerfiles
int main() //start point of the program
51
DDRB=0X08; //making oc0 pin as output pin
OCR0=126; //loading count value into the compare register
TCCR0=0X19;
TCCR0=0X19; //setting the mode,prescalar ,compare modes of the timer
while(1); //repeat forever
m
co
} //end of the program
n.
Example:-
Example:-
io
The square wave generated from Pinb.4 (OC0) of 32 kHz, timer 0, ctc mode.
//XTAL=12MHZ
at
uc
//concept: waveform generation using
using interrupts
ed
#include<avr/io.h> //for input and output header files

hi
int main() //start point of the program

ks
DDRB=0X08; //making oc0 pin as output pin

a
.s
TCCR0=0X19; //setting the mode, prescalar, compare modes of the timer

w
while(1); //repeat forever

w
w
} //end of the program
ISR( TIMER0_COMP_vect) //interrupt service routine of timer interrupt 0
OCR0 = 187
187;
87;
52
} //end
How to calculate the value to be stored in OCR0 register?
m
co
n.
io
at
uc
Figure 4.1.5:- Waveform generation of frequency 32kHZ.
ed
hi
T = 1/ 32 kHz = 31.25micro seconds.

ks
Ton or Toff = 15.625 micro seconds.
According to the formula,

a
.s
w
w
w
Timer count = -1 = 187
This 187 value is loaded into the OCR0 register.
Lesson 2
53
Wave Generation Mode – PWM Modes
Introduction:
Introduction:-
oduction:-
Pulse width modulation or pulse duration modulation is a modulation

technique that changes the width of the pulse, formally the pulse duration, based on
modulator signal information. Although this modulation technique can be used to
m
encode information for transmission, its main use is to allow the control of the
co
power supplied to electrical devices, especially to inertial loads such as motors.
n.
Note:-
Note:-
io
at
The average value of voltage (and current) fed to the load is controlled by turning the
switch between supply and load on and off at a fast pace.. The longer the switch is on
uc
compared to the off periods, the higher the power supplied to the load is.
ed
The above point shown

shown in form of diagram as follows,
hi
a ks
.s
w
w
w
Figure 4.2.1: - 25% duty cycle - - - - -1/4 power
54
m
co
n.
io
at
uc
Figure 4.2.2: - 50%
50% duty cycle - - - - -1/2 power
ed
hi
ks
3/2 power
a
.s
w
w
w
Figure 4.2.3
4.2.3:
2.3: - 75% duty cycle - - - - -3/2 power
55
So for example, if we consider a DC motor DC supply is provided to that for its

function.
So when constant supply is fed to the DC motor then it runs with some constant
speed. So, if in case we want to vary the speed of the motor then the supply voltage /
power is need to be changed. This can be achieved by using the PWM technique.
m
Here only the duty cycle is change to vary the speed of the motor.
co
The larger the ON time period in the wave form the more power fed into the motor.
n.
So the PWM signals can be provided by using micro controllers where a PWM
io
circuitry chip is embedded into the microcontroller.
at
We are very well aware that the AVR provides us with an option of 8 and 16 bit
uc
timers. 8bit timers count from 0 to 255, then back to zero and so on. 16bit timers
ed
count from 0 to 65535, then back to zero. Thus for a 8bit timer, MAX = 255 and for
a 16bit timer, MAX = 65535.
hi
a ks
.s
w
w
Figure 4.2.4 : - fixed top and fixed max value

w
56
m
co
Figure 4.2.5:
.2.5: - fixed top and variable max value
n.
io
at
uc
ed
hi
Figure 4.2.6:
.2.6: -Fixed and Variable TOP in Timers
ks
Note: - TOP never exceeds MAX. TOP <= MAX.

a
Before going to PWM concepts in timers we have to aware about TOP, Bottom and
.s
MAX. TOP then overflows back to zero. The 1st

MAX The timer always counts from 0 to TOP,
w
figure shown above, TOP = MAX.

MAX We know in CTC Mode that we can clear the
w
timer whenever a match occurs. Due to this, the value of TOP can be reduced as
w
shown in 2nd figure. The thick line shows how the timer would have gone in normal
mode. Now, the CTC Mode can be extended to introduce variable TOP as shown
in 3rd figure.
57
Lesson 3
PWM Modes of Operation
In general, there are three modes of operation of PWM Timers:
• Fast PWM.
• Phase Correct PWM.
m
Fast PWM Mode:
Mode:-
co
Let us consider the Timer 0 for the explanation
explanation of this mode.
n.
In this method the saw tooth wave is considered and this wave is compared with a
fixed voltage level as shown in figure. Now suppose we increase the compare voltage
io
level (to, say B). In this case, as we can see, the pulse width has reduced, and hence
at
the duty cycle.
uc
ed
hi
a ks
.s
w
w
w
Figure 4.3.1:
.3.1: - Example of Fast PWM Mode
But, as you can see, both the pulses (A and B) end at the same time
irrespective of their starting time.
58
In this mode, since saw tooth waveform is used, the timer counter TCNTx (n
= 0, 1, 2) counts from BOTTOM to TOP and then it is simply allowed to overflow
(or cleared at a compare match) to BOTTOM.
This method is not correct to use for controlling the DC motors of a robot because
the saw tooth wave considered is not symmetrical.
m
Phase of the output waveform cannot be maintained constant in this method.
co
In the Fast PWM method the counter counts like in normal mode. The TCNT
n.
value increments up to 0XFF and then then rolls from 0XFF to 00, it sets high
io
TOV0 flag bit.
at
When we consider the Timer 0 then OC0 pin of ATMEGA16 is used for output
uc
the waveform.
We can choose any timer of AVR microcontroller, here we are using

ed
TIMER0.
hi
TCCR0 – Timer/Counter0 Control Register:

ks
Here, we will learn how to set appropriate bits to run the timer in PWM
mode.
a
.s
Bit 7 6 5 4 3 2 1 0
w
C0 GM M0 M00 M01 2 01 0
w
00 1
w
/write
Initial 0 0 0 0 0 0 0 0
value
Figure
Figure 4.3.2:
59
We will discuss only those bits which are of interest to us now.
• Bit 6, 3 – WGM01, 00 – Waveform Generation Mode - These bits can

be set to either “00″ or “01″ depending upon the type of PWM you
want to generate.

Set-on
m
co
correct
n.
io
at
Figure
Figure 4.3.3:
.3.3: Waveform Generation Mode Bit Description
uc
• Bit 5, 4 – COM01:0 – Compare Match Output
Output Mode - These bits are
set in order to control the behavior of Output Compare pin (OC0) in
ed
accordance with the WGM01:00 bits.

hi
The following look up table to determine the operations of OC0 pin for Fast
ks
PWM mode.

a

.s

w

(non inverting mode)
w

w
(inverting mode)
Figure
Figure 4.3.4:
.3.4: Compare Output Mode, Fast PWM Mode
60
CS02
CS02 CS01 CS00 Timer 0 clock seletor
m
co
n.
edge.
io
edge.
at
Figure 4.3.5: Timer 0 clock selector table
uc
Choosing Compare Output Modes to produce the PWM output :-
:-
ed
Out of the three modes,

hi
• inverted,
• non-inverted
ks
We see what the inverting and non inverting mode makes the difference in
a
.s
producing the PWM output.

w
w
w
61
Non -Inverting Mode:

Mode:-
m
co
n.
io
at
uc
ed
hi
Figure 6.3.6: - PWM with non inverting mode

ks
When the COM01: 00 is 0:1 then when compare match occurs then the OC0 pin is
cleared. OC0 pin is low till the next comparison is matched. This example is shown
a
.s
in above figure mentioned. This process is called as NON-

NON-INVERTING MODE.
w
w
w
62
m
co
n.
io
at
uc
ed
hi
aks
.s
w
w
Figure 4.3.7: - PWM with non inverting mode

w
63
m
co
n.
io
at
uc
ed
hi
a ks
.s
Figure 4.3.8:
.3.8: - PWM with non inverting mode with 100% duty cycle
w
w
w
Note:-
Note:-
We can observe in this mode that as the OCR0 value is increased the
duty cycle of the output wave is increased.
64
Inverting Mode:-
Mode:-
m
co
n.
io
at
uc
ed
hi
a ks
.s
w
w
Figure 4.3.9:
.3.9: - PWM with inverting mode.
w
When the COM01: 00 is 1:1 then when compare matc

matchh occurs then the OC0 pin is
high. OC0 pin is high till the next comparison is matched. This example is shown in
above figure mentioned. This process is called as INVERTING MODE.
65
m
co
n.
io
at
uc
ed
hi
aks
.s
w
w
w
Figure 4.3.10:
.3.10:- PWM with inverting mode
66
m
co
n.
io
at
uc
ed
hi
a ks
.s
w
Figure 4.3.11:
.11:- PWM with inverting mode with 100% duty cycle.
inverting
w
w
Note:-
Note:-
67
duty cycle of the output wave is decreased.
I ll make you understand how the wave form is generated with some considerations
like duty cycle with certain frequency using inverting or non inverting mode.
Example:-
Example:- for non inverting mode
m
co
Assuming XTAL = 8MHZ, using FAST PWM non-
non-inverting mode, write a program
that generates a wave with frequency of 31,250 Hz and duty cycle of 75%.
n.
Solution:-
Solution:-
io
Given,
XTAL = 8MHZ
at
uc
Frequency of the output wave should be 31,250 Hz.
ed
Duty cycle to be maintained is 75%.

hi
Mode: - Fast PWM Mode, non inverting mode.

ks
STEP 1:-
1:- Find the OCR0 value using formula,
a
.s
Duty cycle = *100.

w
75 = 100
w
w
OCR0 = 191.
STEP 2:-
2:- set the timer in
68
• No prescalar.
• Non-
Non- inverted Fast PWM mode.
How to set prescalar value?
m
Frequency of generated wave = .
co
Where, N is prescalar value and fosc = frequency of
oscillator.
n.
io
So when we substitute the values in above formula then we
get N =1.
at
uc
Set CS 02:01:00 = 0 0 1 in TCCR0 register.
STEP 3:-
3:- To set the timer in Fast PWM mode, Non Inverting Mode.
ed
To set in non inverting mode then

hi
Set Com01:00 = 1 0.
ks
To set in Fast PWM mode,

a
.s
Set WGM01:00 = 1 1.
w
Then TCCR0 register value is,

w
TCCR0 – Timer/Counter0 Control Register 0:

w
Bit 7 6 5 4 3 2 1 0
C0 GM M0 M00 M01 2 01 0
00 1
69
/write
Initial 0 0 0 0 0 0 0 0
value
m
0 1 1 0 1 0 0 1
co
TCCR0 = 0x69
n.
io
4:- The above process must repeated for infinite times to produce the wave
Step 4:-
form from OC0 pin continuously.
at
uc
Embedded C program:
program: - for non inverting mode
ed

hi
a ks
Note: - the OC0 pin is at PB3 of ATMEGA16.

.s
#include<avr/io
#include<avr/io.h>
avr/io.h> // header file includes the functions of input and output
w
statements
w
int main()
w
{ //start of main function
DDRB = 0b00001000; //PORT B 4 pin (OC0) as output pin.
70
OCR0 = 191; // top value stored in compare register.TCNT0 has

0 values initially.
TCCR0 = 0X69;// mode non inverting Fast PWM mode with no

prescalar option is set to timer 0.
while (1); //never ending loop
m
co
return 0;
} // end of main funtion
n.
Output:-
Output:-
io
at
uc
ed
hi
a ks
.s
w
w
w
.3.12: - output waveform of 31250 HZ, fast PWM, non inverting mode
Figure 4.3.12:
71
Example:-
Example:- for inverting mode.
Assuming XTAL = 8MHZ, using FAST PWM inverting mode, write a program
Solution:-
Solution:-
m
Given,
co
XTAL = 8MHZ
n.
Frequency of the output wave should be 31,250 Hz.
io
Duty cycle to be maintained is 75%.
at
Mode: - Fast PWM Mode, inverting mode.
uc
STEP 1:-
ed
Duty cycle = *100.

hi
OCR0 = 63.
ks
STEP 2:-
a
• No prescalar.
.s
• Non-
w
w
w

oscillator.
72

get N =1.
3:- To set the timer in Fast PWM mode, Non Inverting Mode.
STEP 3:-
m
To set in inverting mode then
co
Set Com01:00 = 1 1.
n.
io
Set WGM01:00 = 1 1.
at
uc
ed

hi
Bit 7 6 5 4 3 2 1 0
ks
C0 GM M0 M00 M01 2 01 0
00 1
a

.s
/write
w
Initial 0 0 0 0 0 0 0 0
value
w
w
0 1 1 1 1 0 0 1
TCCR0 = 0x79
73
Step 4:-
Embedded C program:-
program:- for inverting mode.

program
m
co
n.
#include<avr/io.h> // header file includes the functions of input and output
io
statements
at
int main()
uc
ed

hi
OCR0 = 63;
63; // top value stored in compare register.TCNT0 has 0
ks
values initially.
a
TCCR0 = 0X79
0X79;
79;// mode non inverting Fast PWM mode with no
.s

w
while (1); //never ending

ending loop
w
return 0;
w
Output:-
Output:-
74
m
co
n.
io
at
uc
ed
hi
Figure 4.3.13:
.3.13:-output waveform of 31250 HZ, fast PWM, inverting mode
ks
The same concept can be applied to the Timer 1 but the formulas will be changed
like,
a
.s
To calculate the prescalar (N):-

w
F generated wave =
w
w
Duty cycle for non inverted mode can be calculated as:-
F generated wave = *100
75
Duty cycle for inverted mode can be calculated as:-
F generated wave = *100
Phase Correct PWM mode
Let us consider Timer 0 to understand how this mode works
m
co
n.
io
at
uc
ed
Figure 4.3.14: -Timer 0 phase correct PWM mode.

mode
hi
The TCNT0 value goes up and down as shown in above figure. First it counts up
ks
and then counts down. Whenever it reaches zero then TOV0 flag is set to 1.
a
These registers of Timer 0 are used to set the mode and to control the registers.
.s
w
TCCR0 – Timer/Counter0 Control Register:

w
Here, we will learn how to set appropriate bits to run the timer in PWM
mode.
w
76
Bit 7 6 5 4 3 2 1 0
C0 GM M0 M00 M01 2 01 0
00 1
/write
Initial 0 0 0 0 0 0 0 0
m
value
co
Figure
Figure 4.3.15:
We will discuss only those bits which are of interest to us now.
n.
• Bit 6, 3 – WGM01, 00 – Waveform Generation Mode - These bits can
io
be set to either “00″ or “01″ depending upon the type of PWM you
at
want to generate.

uc
Set-on
ed

correct
hi

ks

a
Figure
Figure 4.3.16:
.3.16: Waveform Generation Mode Bit Description
.s
• Bit 5, 4 – COM01:0 – Compare Match Output Mode - These bits are

w
set in order to control the behavior of Output Compare pin (OC0) in

w
accordance with the WGM01:00 bits.

w
The following look up table to determine the operations of OC0 pin for
phase correc PWM mode.
77

(non inverting mode)
(inverting mode)
m
Figure
Figure 4.3.17:
.3.17: Compare Output Mode, phase correct mode
co
CS02 CS01 CS00 Timer 0 clock seletor
n.
io
at
0 1 1 uc ClkI/O/64 (From prescaler)
ed

edge.
hi

ks
edge.
a
Figure 4.3.18:
.3.18: - Timer 0 clock selector
.s
This mode also can be operated in two modes,

w
• Non inverting mode.

w
• Inverting mode.
w
Non inverting mode:-

mode:- When the COM01: 00 is 0:1 then when compare match
occurs then the OC0 pin is cleared. OC0 pin is low till the next comparison is
matched. This example is shown in above figure mentioned. This process is called
as NON-INVERTING MODE.
78
m
co
n.
io
at
uc
ed
hi
a ks
Figure 4.3.19:- Phase Correct PWM Mode With Non Inverting Mode.
.s
w
w
w
79
m
co
n.
io
at
uc
ed
hi
ks
Figure 4.3.20:
.3.20: - Phase correct non inverted PWM mode with 100% duty cycle.
a
.s
Note:-
Note:-
w
w
duty cycle of the output wave is increased.

w
Note:-
Note:-
The longer the switch is on compared to the off periods, the higher the
power supplied to the load is.
80
Inverting mode:-
mode:-
When the COM01: 00 is 0:1 then when compare match occurs then the OC0 pin is
set to 1. OC0 pin is set to 1 till the next comparison is matched. This example is
shown in above figure mentioned. This process is called as INVERTING MODE.
m
co
n.
io
at
uc
ed
hi
a ks
.s
w
w
Figure 4.3.21: - Phase Correct Inverted mode

w
As we increase the OCR0 value then the duty cycle of the output wave form
decreases.
81
m
co
n.
io
at
uc
ed
Figure 4.3.22:
.3.22: - Phase Correct Inverted mode wi
with
th 0 % duty cycle
I will make you understand how the wave form is generated with some
hi
considerations like duty cycle with certain frequency using inverting or non inverting
ks
mode.
a
Example:
Example: - Phase Correct PWM non-inverting mode
.s
Assuming XTAL = 8MHZ, using Phase Correct PWM non-

non-inverting mode, write a
w
program that generates a wave with frequency of 61 Hz and duty cycle of 87.5%.
w
w
Using timer 0.
Solution:-
Solution:-
Given,
XTAL = 8MHZ
82
Frequency of the output wave should be 61 Hz.
Duty cycle to be maintained is 87.5%.

5%.
Mode: - Phase Correct PWM non-

non-inverting mode
STEP 1:-
m
Duty cycle = *100.
co
OCR0 = 223.
223.
n.
STEP 2:-
io
• Non-
at
uc
ed

hi

ks
oscillator.
a

.s
get N =256
w

w
w
STEP 3:-
3:- To set the timer in Phase Correct PWM non-inverting mode
83
Set Com01:00 = 1 0.
Set WGM01:00
WGM01:00 = 0 1.
1.
m
co
n.
Bit 7 6 5 4 3 2 1 0
io
C0 GM M0 M00 M01 2 01 0
at
00 1
uc
/write
Initial 0 0 0 0 0 0 0 0
ed
value
hi
1 1 0 0 1 0 0
ks
0
a
.s
TCCR0 = 0x6
0x64
w
w
Step 4:-
w
84
Embedded C program: - for non inverting mode
Assuming XTAL = 8MHZ, using Phase Correct PWM non-

non-inverting mode,
mode, write a
program
m
co
statements
n.
int main()
io
DDRB = 0b00001000;
at //PORT B 4 pin (OC0) as output pin.
uc
OCR0 = 223;
223; // top value stored in compare register.TCNT0 has
ed
0 values initially.
hi
TCCR0 = 0X6
0X64;// mode non inverting Fast PWM mode with no
ks

a

.s
return 0;
w

w
w
85
Output:-
Output:-
m
co
n.
io
at
uc
Figure 4.3.23:-
.3.23:- the output wave of Phase Correct PWM non inverted mode
ed
hi
Example:-
Example:- Phase Correct PWM inverting mode
ks
Assuming XTAL = 8MHZ, using Phase Correct PWM inverting mode, write a
a
.s
Using timer 0.
w
Solution:-
Solution:-
w
Given,
w
XTAL = 8MHZ
Frequency of the output wave should be 61 Hz.
Duty cycle to be maintained is 87.5%.
86
Mode: - Phase Correct PWM inverting mode
STEP 1:-
Duty cycle = *100.
OCR0 = 32
m
STEP 2:-
co
• Phase Corrected PWM inverted mode
n.
io
at
uc
ed
oscillator.
hi

ks
get N =256
a

.s
STEP 3:-
3:- To set the timer in Phase Correct PWM inverting mode.
w

w
w
Set Com01:00 = 1 1.
1.
Set WGM01:00
WGM01:00 = 0 1.
87
Bit 7 6 5 4 3 2 1 0
C0 GM M0 M00 M01 2 01 0
m
00 1
co
/write
Initial 0 0 0 0 0 0 0 0
n.
value
io
at
1 1 1 0 1 0 0
0
uc
ed
TCCR0 = 0x7
0x74
hi
Step 4:-
ks

a
.s
Embedded C program: - Phase Correct PWM inverting mode

w
Assuming XTAL = 8MHZ, using Phase Correct PWM inverting mode, write
write a
w
w

statements
88
int main()
OCR0 = 32;
32; // top value stored in compare register.TCNT0 has 0
m
values initially.
co
TCCR0 = 0X74;// mode non inverting Fast PWM mode with no
n.
io
at
return 0; uc
ed
Output:-
Output:-
hi
a ks
.s
w
w
w
.3.24: - the output wave of Phase Correct PWM inverted mode.

Figure 4.3.24:
89
The same concept can be applied to the Timer 1 but the formulas will be changed
like,
To calculate the prescalar (N):-

(N):-
!!"# $
F generated wave =
m
% & '
co
as:--
Duty cycle for non inverted mode can be calculated as:
n.
(
F generated wave = )& *+
*100
io
Duty cycle for inverted mode can be calculated as:-
as:-
at
& ' (
F generated wave = )& *+
*100
uc
ed
hi
a ks
.s
w
w
w
90

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TIMERS AND COUNTERS OF ATMEGA 16

In this lesson we will know about the introduction to timers/counters.

counter represents how many times an event has occurred..

controller’s source code. This is possible because, Timers/counters are separate

Timer Resolution = (1 / Input Frequency).

Consider a microcontroller with an oscillator with frequency of 1 MHz; in the

counters. So the important issue is irrespective of whether the timer/counter is in

Because of this roll over,

• The interrupt may be provided from the timer.

General view of timers and counters:-

Pins corresponding to the timers/counters:-

• T0 = timer0/counter0 counter source.

T1 = timer1/counter1 counter source.

• OC0 = Timer/Counter0 Output Compare Match Output.

• OC1A = Timer/Counter1 Output Compare A Match Output.

• OC1B = Timer/counter1 output compare B match output.

In ATMEGA16, we have three different kinds of timers:-

Timer/Counter Type Capacity Counting capacity

Register Type Name Description

contents can be accessed

from this register.

TCCR(x) register. Timer /counter control This register is used to

register control the function of

register are compared

with the TCNT(x). When

• This register is a counter. Upon reset the registers contains zero.

2. TOVX flag bit:-

TIFR register (timer

Generally the timer can operate in three modes,

For example, to specify the timer0 to work as a timer/counter by loading

Now suppose, we need to flash an LED eve

Now, as stated above, we need a delay of 10 msec. This mayb

counting up to 65535) to achieve this delay.

a greater delay, say 20 ms? We are stuck?!

using a 16-bit timer. At this frequency, a maximum delay of 131.072 ms can be

No other value in between.

So, we have to select the best prescalar,

Required delay = 184 msec; F_CPU = 4MHZ.

Prescalar Clock frequency Timer count

1 is eligible for this case.

because timer count value in all cases is above 255 values.

Lesson 4 AVR Timers

Timer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter

Since timer is a peripheral, it can be activated by setting some bits in some

The Timer/Counter Register,

Read R/W R/W R/W R/W R/W R/W R/W R/W

The value of the counter is stored here and increases/decreases automatically.

are shown below.

CS02 CS01 CS00 Description

0 0 0 No clock source (Timer/Counter stopped)

0 0 1 ClkI/O/1 (No prescaling)

1 0 1 ClkI/O/1024 (From prescaler)

Mode WGM01 WGM00 Timer/Counter TOP Update of TOV0 Flag

(CTC0) (PWM0) Mode of operation OCR0 Set-

0 0 0 Normal 0xFF Immediate MAX

3 1 1 Fast PWM 0xFF TOP MAX

Bit 5:4 – COM01:00 – Compare Match Output Mode:-

The selection options of non-PWM mode are as follows.