Comparison Between Phase- and Level-shifted PWM

Schemes for Flying Capacitor Multilevel Inverter

S. Ketsakoon, S. Polmai
Department of Electrical Engineering, Faculty of Engineering
King Mongkut’s Institute of Technology Ladkrabang (KMITL)
Chalongkrung Rd., Ladkrabang, Bangkok THAILAND 10520
E-mail: [email protected], [email protected]

Abstract-This paper presents the study and comparison of multilevel inverter is balancing of voltage across each
PWM schemes for five-level flying capacitor inverter. The PWM capacitor. Having capability of balancing the capacitor voltage
schemes. Included in this study are phase-shifted and level-shifted without additional dedicated hardware is preferable. The
multi-carrier sinusoidal modulation. The comparison focuses on flying-capacitor and cascade multi-cell inverter utilize the
output voltage THD, capacitor voltage balancing and effect of the
dead time. The results of the comparison will be used to aid the
redundant switching states to solve this problem. Owning to the
design of five-level flying capacitor inverter in the future. single dc source constraint, the flying-capacitor inverter is
selected for this study.
Keywords - Flying-capacitor multilevel inverter, SPWM, total Multilevel sinusoidal pulse-width modulation (SPWM) is
harmonic distortion, energy balance. investigated in this study. The PWM schemes included in this
study are phase-shifted and level-shifted multi-carrier
INTRODUCTION sinusoidal modulation. The investigation focuses on output
In recent years, industry has begun to demand higher power voltage THD, capacitor voltage balancing and effect of the
equipment, which now reaches the megawatt level. Controlled dead time. The results of the comparison will be used to aid the
ac drives in the megawatt range are usually connected to the design of five-level flying-capacitor inverter in the future.
medium-voltage network. Today, it is hard to connect a single
FLYING CAPACITOR INVERTER CIRCUIT
power semiconductor switch directly to medium-voltage grids
(2.3, 3.3 or 6.9kV). For these reasons, a new family of The flying-capacitor inverter Fig. 2 can produce an inverter
multilevel inverters has emerged as the solution for working phase voltage with five voltage levels. When switches S1, S2,
with higher voltage levels [1]-[2]. S3, and S4 conduct, the inverter phase voltage vAN is 4E, which
Today, multilevel inverters are extensively used in high- is the voltage at the inverter terminal A with respect to the
power applications with medium voltage levels. The field negative dc bus N. Similarly, with S1, S2, and S3 switched on,
applications include use in motor drive, harmonic elimination vAN = 3E. Table II lists all the voltage levels that can be
and improvement power factor in system and static VAR obtained by the six sets of different switching states.
compensations to system.
Three different topologies have been proposed for multilevel
inverters: diode-clamed (neutral-clamped); capacitor-clamed
(flying capacitors); and cascaded multi-cell with separated
sources. In addition, several modulation and control strategies
have been developed or adopted for multilevel inverters
including the following: multilevel sinusoidal pulse width
modulation (SPWM), multilevel selective harmonic
elimination, and space-vector (SVM) [2].
The most attractive features of multilevel inverters are as (a) (b) (c)
Figure 1. Multi-level inverter topology. (a) diode-clamped. (b) cascaded-
follows. multicell. (c) capacitor-clamped (flying-capacitor).
They can generate output voltages with extremely low
distortion and lower dv/dt. TABLE I
They draw input current with very low distortion. COMPARISON OF MULTILEVEL INVERTER CIRCUITS TOPOLOGIES
They can operate with a lower switching frequency. Comparison Diode-clamped Cascaded-multicell Flying capacitor
Common DC link
Table I shows the comparison of the multilevel inverter Redundant of
topologies. In the application that requires energy source, such switching state.
as adjustable speed drive of ac machines, the dc link energy is Number of dc
Few Few Many
capacitors
normally fed from the ac source via rectifier or converter Isolated voltage dc
circuit. Having only single dc link is the benefit in term of Single Many Single
source
reliability and ease of control. Another issue concerning with

ECTI-CON 2007
The 2007 ECTI International Conference
____________________________________________________________
370
 The switching state redundant is a common phenomenon in B.Level-shifted Multi-carrier PWM Scheme
multilevel converters, which provides a great flexibility for the Fig. 4 illustrates three variation of the level-shifted multi-
switching pattern design. carrier PWM named (a) in-phase disposition (IPD) where all
carriers are in phase, (b) alternative phase opposite disposition
(APOD) where all carriers are alternatively in opposite
SINUSOIDAL MULTI-CARRIER PULSE-WIDTH MODULATION
disposition and (c) phase opposite disposition (POD) where all
Several multi-carrier techniques have been developed to carriers above the zero reference are in phase but in opposition
reduce the distortion in multilevel inverters, based on the with those below the zero reference. In what follows, only IPD
classical SPWM with triangular carriers [1]. Some methods use modulation scheme is discussed in detail due to page
carrier disposition and others use phase shifting of multiple limitation.
carrier signals [3].
Vˆcr Vˆm
A. Phase-shifted Multi-carrier PWM Scheme
Fig. 3 illustrates typical gating signal using phase-shifted
multi-carrier PWM for one phase leg of the inverter shown in
Fig. 2. In this paper, we choose a number of m-voltage levels
requires (m-1) triangular carriers in one phase with their
carriers shifted by an angle given by
!cr = 360"/(m – 1 ), (1)

Figure 3. Modified phase-shifted modulation for five-level inverter

of one phase-leg.

Vˆm Vˆcr

(a) In-Phase Disposition (IPD) .

Vˆm Vˆcr

Figure 2. Five-level flying-capacitor inverter.

TABLE II
VOLTAGE LEVEL AND SWITCHING STATE OF A FIVE-LEVEL FLYING-
CAPACITOR INVERTER

Switching states Output voltage Inverter

related of phase C1 C2 C3 C4
S1 S2 S3 S4 capacitor voltage vAN (b) Alternative Phase Opposite Disposition (APOD).
1 1 1 1 4E Vdc(4E) - N N N
Vˆm Vˆcr
1 1 1 0 4E - 1E - N N +
1 1 0 1 4E - 2E + 1E - N + -
3E
1 0 1 1 4E - 3E + 2E - + - N
0 1 1 1 3E N - N N
1 1 0 0 4E - 2E - N + N
1 0 1 0 4E - 3E + 2E - 1E - + - +
0 1 1 0 3E - 1E N - N +
2E
1 0 0 1 4E - 3E + 1E - + N -
0 1 0 1 3E - 2E + 1E N - + -
0 0 1 1 2E N N - N
1 0 0 0 4E - 3E - + N N
(c) Phase Opposite Disposition (POD).
0 1 0 0 3E - 2E N - + N
1E
0 0 1 0 2E - 1E N N - + Figure 4. Level-shifted multi-carrier modulation for five-level inverter.
0 0 0 1 1E N N N -
0 0 0 0 0 0 N N N N
The phase-shifted PWM scheme have characteristic as
Index: 1-sw on, 0-sw off, N-none, + charging mode, - discharging mode follows.

ECTI-CON 2007
The 2007 ECTI International Conference
____________________________________________________________
371
 TABLE III
INVERTER OPERATING FOLLOWING
ma = Vˆm / Vˆcr , for 0 # ma # 1, (2)
fsw,dev = fcr, (3) Parameter operating Phase-shifted PWM Level-shifted modulation
fsw,inv = (m-1)fsw,dev, (4) fm 50 Hz 50 Hz
where fcr 750 Hz 3000 Hz
fm Fundamental frequency mf 15 60
fcr Carrier frequency fsw,dev 750 Hz 750 Hz
fsw,inv 3000 Hz 3000 Hz
fsw,dev Frequency switching device
load PF = 0.8 lagging, 0.414 kVA
fsw,inv Switching frequency of inverter
mf Frequency modulation index ( fcr / fm )
ma Modulation index S1
m Voltage levels S2
S3
As stated earlier, the frequency of the dominant harmonic in S4
the inverter output voltage represents the inverter switching
fsw,inv. Since the dominant harmonics in vAN and vAB distributed

vAB (V)
4E
around (m - 1)mf. 0
The level-shifted PWM scheme have characteristic as
follows.

Amplitude
40 4mf + 1 THD = 20.7686%
ma = Vˆm / Vˆcr (m $ 1) , for 0 # ma # 1, (6) n=1
4mf – 5 4mf + 5
20 4mf – 7 4mf + 7
fsw,dev = fcr /(m-1), (7) 0
0 10 20 30 40 50 60 70 80 90 100
fsw,inv = fcr, (8) Number of spectrum harmonics
As stated earlier, the frequency of the dominant harmonic in Figure 5. Simulated waveforms for a five-level flying-capacitor inverter with
the inverter output voltage represents the inverter switching phase-shifted PWM (mf =15, ma =1.0, fm =50 Hz,
fsw,inv. Since the dominant harmonics in vAN and vAB distributed fcr =750 Hz, and fsw,dev =750 Hz).
around mf.
S1
SIMULATION RESULT S2
The simulations comparisons between both schemes are S3
S4
focused on three topics the output voltage THD, capacitor
energy balancing and effect of the dead time. To compare the
vAB (V)

performance of inverter, it is assumed that the average 4E

0
switching frequency of the solid-state devices is the same in
both schemes. Table III shows the important parameters used
Amplitude

in the simulations. 40 mf + 2
THD = 8.9887 %
mf – 4 mf + 4
Fig. 5 shows the simulated waveforms using phase-shift 20 n=1 mf + 10
mf – 10
multi-carrier PWM schemes for the inverter operating under 0
0 10 20 30 40 50 60 70 80 90 100
the condition of mf = 50, ma = 1.0, fm = 60 Hz, and fcr = 750 Hz. Number of spectrum harmonics
As stated earlier, the frequency of the dominant harmonic in
Figure 6. Simulated waveforms for a five-level flying-capacitor inverter with
the inverter output voltage represents the inverter switching IPD modulation (mf = 60, ma = 1.0, fm = 50 Hz,
frequency fsw,inv. Since the dominant harmonic in vAB in Fig. 5 fcr = 3000 Hz, and fsw,dev = 750 Hz).
are distributed around 4mf, the inverter switching frequency 140

can be found from fsw,inv = 4mf % fm = 4fsw,dev, which is four fsw,dev = 750 Hz
times the device switching frequency. 120
five level inverter
Fig. 6 shows the simulated waveforms using IPD multi- Phase shifted
100
carrier PWM schemes for the inverter operating under the IPD
condition of mf = 50, ma = 1.0, fm = 60 Hz and fcr = 3000 Hz. 80
POD
THD(%)

Although the carrier frequency of 3000 Hz seems high for APOD

high-power converters, the average device switching frequency 60

is only 750 Hz.

40
Fig. 7 shows the THD profile of the line-to-line voltage vAB
produced by the phase- and level-shifted modulation schemes. 20
As can be seen from the Figure, the IPD modulation scheme
gives the best THD result all over the length of modulation 0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
index. The phase-shift and APOD have the same THD Modulation index (Ma)

characteristic all the range of modulation index. The THD Figure 7. THD profile of vAB produced by the five-level inverter with phase-
calculation is performed up to 100th order. and level-shifted modulation schemes.

ECTI-CON 2007
The 2007 ECTI International Conference
____________________________________________________________
372
 The table IV shows the effect of dead time on THD of the Fig. 8 shows the current flowing through each flying
inverter output voltage. The THD increased with the increased capacitor. In case of phase-shifted PWM scheme the currents
dead time but only at a very small fraction. flowing in the flying-capacitors are balanced, i.e. the average
current is zero. In case of IPD PWM scheme, the currents
TABLE IV flowing through the flying-capacitors are not balanced,
PERCENT THD OF VAB AFFECTED BY THE DEAD TIME resulting in a non-zero average current. If no energy source is
Modulation Index : ma
connected to the flying-capacitor; this would result in uneven
dead time 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 level of the output voltage.
1&s 134.97 116.13 88.71 57.60 28.40 8.19 17.98 24.29 23.39 18.92
Phase-
2&s 135.10 116.43 89.10 58.01 28.74 8.19 17.79 24.25 23.45 19.01
shifted CONCLUSION
4&s 135.36 117.02 89.88 58.84 29.43 8.22 17.41 24.16 23.57 19.20
1us 55.95 43.67 26.57 12.96 19.78 8.05 9.73 9.61 5.69 7.64 Simulations of flying-capacitor multilevel inverter have been
IPD 2&s 56.13 43.85 26.80 13.04 19.58 8.10 9.67 9.69 5.75 7.56
carried out using phase-shifted and level-shifted PWM
4&s 56.46 44.24 27.25 13.21 19.19 8.23 9.55 9.82 5.90 7.38
schemes. The results of the simulation are compared. The IPD
1&s 134.95 116.12 88.70 57.60 28.42 30.08 34.89 34.06 27.49 17.44
POD 2&s 135.07 116.42 89.09 58.00 28.73 29.96 34.82 34.07 27.60 17.59
PWM scheme provided the lowest output voltage THD over
4&s 135.07 116.45 89.06 58.04 28.72 8.25 17.77 24.18 23.41 18.98 the range of modulation index. However it could not balance
1&s 134.95 116.16 88.67 57.64 28.42 8.25 17.96 24.22 23.34 18.88 the energy flow of the flying-capacitors and could lead to
APOD 2&s 135.32 117.00 89.87 58.83 29.37 29.71 34.67 34.07 27.80 17.88 uneven level of the output voltage. The phase-shifted PWM
4&s 135.33 117.03 89.83 58.85 29.35 8.28 17.39 24.09 23.53 19.17 scheme, while providing a higher output voltage THD, it is
capable of balancing the energy flow of the flying-capacitors.
2
Both features, low THD and capacitor energy balancing, could
idc1(A)

0 not be attained at the same time by both modulation schemes.

Regarding to the THD performance, IPD PWM scheme will
-2
0.135 0.14 0.145 0.15 0.155 0.16 0.165 0.17 0.175 be suitable for adjustable speed-drive application, where full
2
range of modulation is required. Balancing of the capacitor
idc2(A)

0 energy under IPD PWM scheme using a technique introduced

in [4] as well as other techniques will be reported in the future.
-2
0.135 0.14 0.145 0.15 0.155 0.16 0.165 0.17 0.175
2
idc3(A)

-2
0.135 0.14 0.145 0.15 0.155 0.16 0.165 0.17 0.175
REFERENCES
2
[1] L. Tolbert, F.-Z. Peng, and T. Habetler, “Multilevel converters for large
electric drives,” IEEE Trans. Ind. Applicat., vol. 35, pp. 36-44, Jan./Feb.
idc4(A)

0
1999.
-2
[2] F. Zheng Peng, J. Rodriguez, and J. Sheng Lai ,Multilevel Inverter: A
0.135 0.14 0.145 0.15 0.155 0.16 0.165 0.17 0.175 Survey of Topologies, Control and Application, IEEE Trans. Ind.
Time(sec)
Applicat., Vol. 49, No. 4, August 2002.
(a) Incase of phase-shifted PWM scheme. [3] Bin Wu, High-Power Converters and ac Drives, The Institute of
Electrical and Electronics Engineerings, Inc., 2006, pp.127-136.
2
[4] F. Z. Peng and J. S. Lai, “Dynamic performance and control of a static
VAR generator using cascade multilevel inverter,” IEEE Trans. Ind.
idc1(A)

0
Applicat., vol. 33, pp. 748=755, May/June 1997.
-2
0.135 0.14 0.145 0.15 0.155 0.16 0.165 0.17 0.175
2
idc2(A)

-2
0.135 0.14 0.145 0.15 0.155 0.16 0.165 0.17 0.175
2
idc3(A)

-2
0.135 0.14 0.145 0.15 0.155 0.16 0.165 0.17 0.175
2
idc4(A)

-2
0.135 0.14 0.145 0.15 0.155 0.16 0.165 0.17 0.175
Time(sec)

(b) Incase of IPD PWM scheme.

Figure 8. Waveforms of the current flowing through the flying capacitors.

ECTI-CON 2007
The 2007 ECTI International Conference
____________________________________________________________
373