2015 IEEE International Conference on Computational Intelligence & Communication Technology

Implementing Communication Bridge Between I2C and

APB
Jasmine Chhikara, Reshma Sinha, Shuchita Kaila

Department of Electronics and Communication Engineering – VLSI Design

Indira Gandhi Delhi Technical University for Women
(Formerly Indira Gandhi Institute of Technology)
Kashmere Gate, Delhi-110006, India
[email protected], [email protected], [email protected]

Abstract— All design units consist of smaller functional blocks

called subsystem or module. For effective functioning of the sys-
tem these modules need to be in sync with each other and share
resources. Problem starts when one module follows different
protocol as others and each module has its different bit rate or
baud rate of data transfer which can be either asynchronous or
synchronous. The paper takes an example of I2C protocol and
AMBA APB protocol to describe the architecture which defines
how data are transferred from one protocol to another. It ex-
ploits the flexible protocols of I2C to make it compatible with
APB protocol. The proposed architecture is a bridge between I2C Fig. 1. I2C Data Transfer Protocol.
Master and APB Salve. The data travels from a serial bus (I2C)
to parallel bus (APB) to serial (I2C) in sync with the respective
domain clock. This forms a bidirectional interface between I2C B. APB Write Protocol
supported module and APB supported module.
Fig. 2 explains the write cycle as- IDLE: The default
Keyword: SCL, SDA, PSELx, PENABLE, Xilinx ISE.
state. SETUP: When transfer is required the bus moves into
I. INTRODUCTION the SETUP state, where the select signal, PSELx, is asserted.
The bus remains here for one clock cycle and moves to the
I2C is a 2-wire, SDA and SCL, bus developed with the
ENABLE state on the next rising edge of the clock. ENABLE:
basic idea of connecting different ICs and application specific
The enable signal, PENABLE, is asserted. The address, write
modules with processors on a common communication net-
and select signals have to remain stable during the transition
work. I2C is a multi-master bus and the peripheral devices are
from the SETUP to ENABLE state. If no further transfers are
addressed by unique programmable address. By sampling the
required the bus returns to the IDLE state. Alternatively, if
SDA above Nyquist rate I2C can communicate with any de-
another transfer is to be made then the bus will move to SE-
vice. On the other hand APB is a low bandwidth bus with re-
TUP. Address, write and select signals can glitch during tran-
duced interface complexity. APB has dedicated programmable
sition.
control registers to access peripherals devices. Like I2C, APB
compatible devices are easily incorporated in any design flow.
A. I2C Protocol

I2C bus runs on simple master-slave relationship. All

trans-actions begin with detection of START condition and
are terminated by encountering STOP condition. As soon as
start condition arises bus is considered to be busy and it will
re-main in the same state till all requests for the bus have been
granted. For the read/write operation, first the slave’s address
is sent followed by the corresponding data, as shown in figure
1. ACK signal is sent after successful transfer of each data
byte. For interrupted transmission NACK signal is raised.
Fig. 2. State Diagram for write operation on APB.

978-1-4799-6023-1/15 $31.00 © 2015 IEEE 235

DOI 10.1109/CICT.2015.19
Rest of the paper is divided in five sections. Section II illu- this way a communication between I2C Master and APB
strates the motivation behind the work. Section III is the core Slave is done.
of the paper and gives details about designed and hence im-
A. Write Operation
plemented architecture which is essentially a bridge be-tween
I2C protocols to APB Protocols. The section describes func-
• Whenever I2C Master needs to communicate with
tionality of the system. Section IV addresses the limitations
APB Slave it would be done via I2C Slave.
that are encountered while operating the system and may need
attention. Following the limitations is the section V of future • I2C Slave will assert Data Valid and Address Valid
work which is framed considering who these limitations could signals.
be resolved and also further development in the design. Sec-
• Seeing these signal high, designed APB Master polls
tion VI gives the simulation results from Xilinx ISE 14.2 Si-
the memory for its availability and starts APB write
mulator. The last section, section VII is the concluding part.
state machine.
II. RELATED WORK • I2C sends four chunks of 8-bit data serially to be
I2C bus was developed to reduce congestion, area and written on APB Memory at four consecutive ad-
power consumption by microcontroller when multiple devices dresses.
were needed to be attached to it. Owing to increasing demand
• After transfer of each byte APB Master keeps a
of the high-speed high-performance system microcontroller
check on count whether all four memory locations
ran on parallel buses. This triggered the need to interface seri-
are updated successfully.
al buses with parallel buses. [9] created a common architecture
for I2C and SPI interface with APB AMBA bus thereby re- • As soon as the data at APB Master is updated it
ducing the chip area. PCA9564 bus controller [10] is a generic transfers the same 32-bit data to APB Slave.
interface between I2C and SMBus with standard 8-bit parallel
B. Read Operation
buses. [11] shows AHB communicating with SPI Master. [12]
and [13] connected host compliant with AMBA protocol to
• Here again when I2C need to read data from the APB
I2C bus via APB protocol.
Slave, communication will take place via APB Mas-
ter to I2C Salve to I2C master.
III. DESIGNED ARCHITECTURE
Architectural block diagram of the implemented commu- • APB Salve will send a signal to APB Master telling
nication bridge between I2C and APB is shown in Fig. 3. The that the data are available to be read.
Structure contains two main blocks, i.e. I2C Slave and APB • APB Salve then transmit the data to APB Master
Master. I2C Slave takes the data from I2C Master in respec- where it is stored in the internal memory to be
tive format and provide it to APB Master. This APB Master fetched by I2C Slave at time point of time.
further sends out this data to APB Slave in APB Protocol. In

Fig. 3. Block Diagram of Proposed Communication Bridge

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 IV. LIMITATIONS • Keeping the operating frequencies of designed APB
• By the design I2C operating frequency is much master compatible with I2C.
greater than designed APB master clock frequency. The other ways to perform Reading Operations-
I2C can overwrite the same address multiple times.
In this scenario, designed APB master block sends • Time Based: APB reads in a particular time interval
the updated data only and data transfer rate limits by which is defined by user. APB reads the data at the
the operating frequency of the designed APB master. address of interfaced module and updates all register
in its internal memory.
• Designed APB master does not send the address
specified by the I2C. It sends only data from the in- • Making I2C initiate read operation in APB.
ternal memory to the fixed addresses. This internal
memory updates through the I2C any time. VI. RESULT
Figure 4 shows input data to the I2C bus is being replicated at
• When I2C writes the 4 successive data in the internal
the output slave device, meeting all the protocols and con-
memory of designed APB master then only designed
straints. In this data changes in-between high edges of clock.
APB master writing operation initiates. Data flows
Data transfer takes place between start and stop. Start condi-
from the I2C to APB and from APB to I2C.
tion is depicted by a high to low transition on the SDA line
• I2C bus will hang even if the single device on the bus while SCL is high whereas Stop condition is marked by low to
stops operating. The operation can be restored by cy- high transition on the SDA line while SCL is high. When Start
cling the power to the bus. condition is matched with the following data transfer protocol
- Start bit, Device address, R/W bit(0), Acknowledge, Register
V. FUTURE WORK Address, Acknowledge, Data, Acknowledge, Data (Auto In-
As proposed care has been taken to match data transfer crement), Acknowledge, Data (Auto Increment), Acknowl-
speed of both the buses for better compliance. We intend to edge,……., Stop bit - I2C sends four chunks of 8 bit data seri-
design a model with added buffers at the interface to get even ally to be written on APB memory block at four consecutive
higher speed of data transfer address. APB master keeps a check on count whether all four
memory locations are updated successfully. As soon as the
Latency and chances of losing data can be decreased by- data at APB Master is updated it transfers the same 32-bit data
• Increasing the buffer length at the interface of de- to APB Slave as shown in the figure 5.
signed APB master.

Fig. 4. Data transfer format of I2C Bus

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 Fig. 5. Communication between I2C and designed APB master

[8] D.B.Rane, Ahmed Mustafa M. I. Shaikh, Devanand Mahajan, Mehdi

VII. CONCLUSION Ali, ”Priority Based I2C Bus Controller” (IJCTEE) Volume 3, Special
The implemented communication bridge between I2C and Issue, March-April 2013.
APB was designed and implemented in Xilinx ISE 14.2, Ver- [9] Bacciarelli, L. Lucia, G. ; Saponara, S. ; Fanucci, L. ; Forliti, M., “De-
tex 6, using Verilog HDL. I2C Bus was successfully designed sign, testing and prototyping of a software programmable I2C/SPI IP on
AMBA bus” , IEEE Research in Microelectronics and Electronics 2006,
according to the standards given by NXP Semiconductors. A
Ph. D.
working communication model was set up between I2C proto-
col and APB protocol. Data flow from I2C master to I2C slave [10] “NXP I2C-bus and SMBus controller PCA9564”, www.nxp.com.

to APB master to APB Slave is shown while describing the [11] Chetan Sharma, Abhishek Godara, “AHB interface with SPI master by
architecture. Simulation results are verified and data transfer using verilog”, International Journal of Advances in Engineering Re-
search, 2011, Vol. No. 2, Issue No. VI, December.
from I2C master to APB slave can be clearly seen in provided
simulation results. [12] Product brochure, “National Semiconductor I2C Interface”, www.ip-
extreme.com.
As proposed care has been taken to match data transfer speed
[13] “DB-I2C-M-APB-DS-V1.1”, APB Bus I2C Master Controller, Digital
of both the buses for better compliance. We intend to design a Blocks, Inc., September 2013.
model with added buffers at the interface to get even higher
speed of data transfer.

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