• •

8-Channel Programmable
Interface
Manual

Copyright © June I 1983

Sigma Information Systems Anaheim, CA
• •

June 9, 1983

Contents

SECTION 1 - GENERAL INFORMATION

1 .1 INTRODUCTION 1
1 .2 GENERAL DESCRIPTION 2
1 .3 FEATURES 2
1 .4 SPECIFICATIONS 3

SECTION 2 - INSTALLATION
2.1 UNPACKING AND INSPECTION 5
2.2 ADDRESS SELECTION 7
2.3 VECTOR SWITCH SELECTION 8
2.4 BAUD RATE SELECTION 9
2.5 LINE PARAMETERS SWITCH SELECTION 10
2.6 CONSOLE SELECTION 10
2.7 BREAK RESPONSE 11
2.8 CABLING 11
2.9 MODULE INSTALLATION 12
2.10 RACKMOUNT PANEL (OPTION) 12

SECTION 3 - PROGRAMMING CONSIDERATIONS

3.1 INTRODUCTION 13
3.2 DEVICE ADDRESS FORMAT 15
3.3 VECTOR INTERRUPT FORMAT 16
3.4 WORD FORMATS 17
3.3.1 Receive Control/Status
Register (RCSR) 17
3.4.2 Receive Buffer (RBUF) 18
3.4.3 Transmit Control/Status
Register (XCSR) 19
3.4.4 Transmit Buffer (XBUF) 19

APPENDIX A BUS SIGNALS AND PIN ASSIGNMENTS A-11

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June 9, 1983

Figures

2-1 COMPONENT LOCATIONS SHOWING FACTORY

CONFIGURATIONS 6
2-2 RACKMOUNT CONNECTOR PANEL 12

Tables

2-1 EXAMPLE ADDRESS SELECTION 7

2-2 VECTOR SELECTION EXAMPLES 8
2-3 BAUD RATE SELECTION 9
2-4 LINE PARAMETERS SWITCH SELECTION 10
2-5 CONSOLE ENABLE 10
2-6 BREAK RESPONSE 11
2-7 CABLE PIN ASSIGNMENTS 11
3-1 STANDARD ADDRESS AND VECTOR ASSIGNMENTS 14

------~--
.. .

Section, 1 - General Description

1.1 INTRODUCTION

This manual supplies the information needed to install and operate

the SCD-DLV11J/8 8-channel serial line interface module manufactu-
red by Sigma Information Systems, Anaheim, California. The
material is arranged into the following sections:

SECTION 1 - GENERAL INFORMATION. This section contains a general

description of the interface module, along with features. Spec-
ifications are included.

SECTION 2 - INSTALLATION. This section contains the switch

selection and associated register formats for device and vector
address assignments, baud rates and line parameters. Cabling and
backplane installation is included.

SECTION 3 - PROGRAMMING CONSIDERATIxJNS. This section contains the

address/vector formats and register formats for transmit and re-
ceive control/status and buffer registers.

APPENDIX A The appendix lists the bus signals and their

associated pin assignments.
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June 9, 1983
Page 2

1.2 GENERAL DESCRIPTION

The SCD-DLV11J/8 is a dual-wide asynchronous interface between the

LSI-11 bus and up to eight standard serial I/O devices. It is
software compatible with DEC* operating systems and diagnostics
designed for the DLV11J. It plugs directly into any dual Q bus*
slot.
Sigms's SCD-DLV11J/8 has switch selectable address (160000 to
177776) and vector (000 to 776) assignments. Once the initial ad-
dress and vector are assigned, all eight channels are contiguous
except the console channel which, if selected, resides at 177560
with vector at 60.
All channels share a programmable baud rate with a switch select-
able default value. Baud rates range from 50 to 19.2K buad. The
SCD-DLV11J/8 supports only RS-232C devices with all channels shar-
ing switch selectable line parameters.
The interface module includes two 12-foot, 4-channel cables, each
with four DB25P connectors. An optional rackmount panel provides
convenient mounting for the eight DB25P connectors.

1.3 FEATURES

The following are some of the features of the SCD-DLV11J/8P.

• Eight asynchronous serial lines can be supported on one

dual-wide module.
• The module is plug compatible with LSI-11 backplanes
and plugs directly into any Q bus slot without backplane
modification.
• The interface is software compatible with operating
systems and diagnostics designed for the DLV11J.
• Baud rate is programmable with a switch selectable
default value.
• Device address and vector assignments are switch
selectable.
• Line parameters are switch selectable.

*DEC and Q bus are registered trademarks of Digital Equipment Cor-

poration.
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June 10, 1983
Page 3

1.4 SPECIFICATIONS

Power Requirements: +5VDC AT 2.0A

12VDC at 0.2A
Device Address: Switch selectable 160000-177776
(Console = 171560)
Vector Switch selectable 000-776
(console = 60)
Baud Rate: Programmable per channel
50, 75, 110, 1 34 .5, 1 50, 200, 300,
600, 1200, 1800, 3400, 3600, 4800
7200, 9600 and 19.2K
Line Parameters: Switch selectable. Shared by
all channels
Data Bit: 7 or 8
Parity: Odd, even or none
Stop Bit: 1 or 2

Operation: Full duplex

I nterface Type: RS-232C
Bus Load: One DC load
Cables: Includes two 12-ft, 4-channel cables,
each with four DB25P connectors.
Terminals require null modem cables
with DB25S connectors to SCD-DLV11J/8P
and associated terminal connectors.
Optional Panel: Mounts the eight DB25P connectors for
convenient rear rackmount cabling to
RS-232C devices.
Installation: Plugs directly into any standard Q bus
slot that provides continuous BIAK1 and
BlAKO lines.
Dimensions: Single dual-wide module: 5.2"W x 8.9"H
(13.2cmW x 22.8cmH)
Temperature
Operating: oOC to 50°C
Storage: -40°C to 85°C
Humidity: 10% to 90% noncondensing

_---
- _._----_..
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June 10, 1983
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Page 5

Section 2 - Installation

2.1 UNPACKING AND INSPECTION

The SCD-DLV11J/8P is shipped in a special packing carton designed

to keep the module from vibrating and to give it maximum protec-
tion during shipment. The packing carton should be retained in
case the unit requires reshipment.
Unpack the SCD-DLV11J/8P and visually inspect it for any damage
that may have occurred during shipment. If any damage has oc-
curred notify Sigma Information Systems immediately.
Verify that the factory set switches are set correctly according
to Figure 2-1.
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June 10, 1983
Page 6

OFF ON
1 • Address
2 • 176500
43 ~
•
____________ _
5 ___ ~_~~~S~i!~~~~e
6 •
OFF ON 7 •
1 Stop Bit • 1 8'--_·....
Odd/Even • 2
Disable Parity • 3
8 bit Character
• 4
-----.- -----
Baud •
5 . OFF ON
Rate • 6 ~---------------4--1 •
9600 .•, 7 -----------
2 •
• 8 3. Vector
4 • 300
----- ------
5 •
6 •
7 •
OFF::::: 1 8 •
ON :::::¢

FIGURE 2-1 : COMPONENT LOCATIONS SHOWING FACTORY CONFIGURATIONS

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June 9, 1983
Page 7

2.2 ADDRESS SELECTION

The SCD-DLV11J/8P has switch selectable device addressing in the

range of 160000 to 177776 (octal). Once an initial address is as-
signed, the remaining seven channels are contiguous except the
console which, if selected, resides at 177560 as channel 7. Refer
to Section 3.1 for a description of the device address and vector
interrupt assignments. The initial address format is shown below.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 a

EXAMPLE:
1 6 a 0 a 0
1 7 6 5 a a
1 7 7 500

Significant address bits set by SW3

The initial address is determined with significant address bits

A6-A12 set by switch SW3. Some examples follow in Table 2-1.

ADDRESS BITS
ADDRESS A12 A11 IA10 A8 IA9 I A7 A6.
SET BY SW3- POSITIONS,
SW3 1 213141 8 7 6
1 764 00 1 1 1 a 1 0 0
*1 765 00 1 1 1 a 1 0 1
1 766 00 1 1 1 a 1 1 0

*Factory preset o = ON
1 = OFF

TABLE 2-1: EXAMPLE ADDRESS SELECTION

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June 9, 1983
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2.3 VECTOR SWITCH SELECTION

The SCD-DLV11J/8P has switch selectable vector assignments in the

range of 000-776 (octal). Once the initial vector is assigned the
remaining seven vectors are contiguous except the console which,
if assigned, resides at 60 as channel 7. The initial vector
format is shown below.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 o

EXAMPLE:

Significant vector bits set by SW1

The initial vector is determined by significant vector bits V6-V8

set by switch SW1. Some examples follow in Table 2-2.

---VECTOR BITS--
VECTOR V8 I V7 I V6
SET BY --SW1 POSITIONS-
SW1 4 I 3 I 2
2 00 0 1 0
*3 00 0 1 1
6 00 1 1 0
*Factory present o = ON
1 = OFF

TABLE 2-2: VECTOR SELECTION EXAMPLES

 June 9, 1983
Page 9

2.4 BAUD RATE SELECTION

All channels share the same programmable baud rate. The baud rate
format is shown below.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 o

where BRO-BR3 define programmable baud rates and SW2 defines de-
fault switch selectable baud rates as shown in Table 2-3.

XCSR BITS
BAUD 15 /13 I 12
I 14
RATE t - - SW2 POSITIONS-
5 6 J 7 8
I I
50 0 0 0 0
75 0 0 0 1
110 0 0 1 0
134.5 0 0 1 1
150 0 1 0 0
200 0 1 0 1
300 0 1 1 0
600 0 1 1 1
1200 1 0 0 0
1800 1 0 0 1
2400 1 0 1 0
3600 1 0 1 1
4800 1 1 0 0
7200 1 1 0 1
9600* 1 1 1 0
19.2K 1 1 1 1

*Factory present o = ON
1 = OFF

TABLE 2-3: BAUD RATE SELECTION

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June 9, 1983
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2.5 LINE PARAMETERS SWITCH SELECTION

All eight channels share the same line parameters. The start bit
is 1, but data bit, parity and stop bits can be assigned via
switch SW2 as shown in Table 2-4.

LINE SW2 DEFINITION

PARAMETER ~OSITION

CHARACTER 4 0 =7 BITS, *1 =8 BITS

LENGTH
PARITY 3 *0 = DISABLE PARITY, 1 = ENABLE PARITY
2 o = ODD PARITY, 1 = EVEN PARITY
STOP BITS 1 *0 =1 STOP BIT, 1 =2 STOP BITS
*Factory preset o = ON
1 = OFF

TABLE 2-4: LINE PARAMETERS SWITCH SELECTION

2.6 CONSOLE SELECTION

The console, if selected, is assigned channel 7. The SCD-

DLV11J/8P is shipped with the console enabled. To disable the
console set switch SW3-5 as shown in Table 2-5.

SW3-5 CONSOLE STATUS

0 DISABLE
*1 ENABLE
*Factory preset o = ON
1 = OFF
TABLE 2-5: CONSOLE ENABLE

----~-------~--- ----------------
 June 9, 1983
Page 11

2.7 BREAK RESPONSE

Channel 7 can be configured to either bootstrap, halt (console em-

ulation mode), or have no response to a receive break condition.
A bootstrap operation upon a receive break condition causes the
CPU to execute the bootstrap program strating at the memory loc-
ation defined by the power-up mode jumpers of the CPU. A halt
operation unpon a receive break condition causes the processor to
halt and the console octal debugging technique (ODT) microcode to
be invoked. Configurations are shown in Table 2-6.

BREAK RESPONSE E1-E2 E1-E3

None OUT OUT
Boot IN OUT
Halt OUT IN
TABLE 2-6: BREAK CONFIGURATIONS

2.8 CABLING

The SCD-DLV11J/8P has two 40-pin connectors and is supplied with

two cables, each terminating in four DB25P connectors. The 40-pin
connectors and associated 25-pin terminating connector pin as-
signments are defined in Table 2-6.

25-PIN 40-PIN CONNECTOR

DB25P ~LINE NUMBER--

~I ~ I ~
SIGNAL DESCRIPTION 3
I7
Transmit Data transmitted from 3 33 23 13 3
Data SCD-DLV11J/8 to terminal
Recei ve Data received by SCD-DLV11J/8P 2 38 28 18 8
Data from terminal
Clear Signal sent by device to SCD- 5 34 24 14 4
to Send DLV11J/8 to indicate readi-
ness for transmitted data
Ground Signal Ground 1 ,7 39 25 12 5
Ground Protective Ground 1 ,7 32 22 15 2

TABLE 2-7: CABLE PIN ASSIGNMENTS

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June 9, 1983
Page 12

The SCD-DLV11J/SP provides a Clear to Send input which can be

driven by the attached serial line device to cause the SCD-
DLV11J/SP channel to stop transmitting. The common use for this
feature is with a printer that does not support XON-XOFF, but does
provide a buffer full signal. This buffer status signal can be
used to assert the CTS signal and effectively control transmission
of data to the printer from the SCD-DLV11J/SP.
Cabling to terminals requires null modem cables with DB25S sockets
between the SCD-DLV11J/SP connectors and associated terminal con-
nectors.

2.9 MODULE INSTALLATION

The SCD-DLV11J/SP plugs directly into any Q bus slot, providing

BIAK1 and BIAKO lines from the interface to the CPU are continu-
ous. Bus signals and associated pin assignments are listed in
Appendix A.

2.10 RACKMOUNT PANEL (OPTION)

An optional rackmount panel provides convenient mounting for the

eight DB25P connectors. The panel is illustrated in Figure 2-2.

FIGURE 2-2: RACKMOUNT CONNECTOR PANEL

 June 10, 1 9S3
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Section 3 - Programming Considerations

3.1 INTRODUCTION

The SCD-DLV11J/SP is controlled by four device registers per chan-

nel for a total of 32 device registers. The four device registers
provided for each of the eight channels are:

RCSR Receive Control/Status Registers

RBUF Receive Buffer
XCSR Transmit Control/Status Register
XBUF Transmit Buffer

With the exception of the console channel, the device registers

are assigned in a contiguous block by setting the address of chan-
nel O. If the SCD-DLV11J/SP is used as the console device,
channel 1 is assigned the console address and vector. If the SCD-
DLV11J/SP is not used as the console, channel 1 is assigned as the
last contiguous address set. Table 3-1 illustrates an initial ad-
dress and vector assignment with contiguous locations.
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ADDRESS REGISTER VECTOR CHANNEL

176500 RCSR 300 0
176502 RBUF
176504 XCSR 304 0
176506 XBUF
176510 RCSR 310 1
176512 RBUF
176514 XCSR 314 1
176516 XBUF
176520 RCSR 320 2
176522 RBUF
176524 XCSR 324 2
176526 XBUF
176530 RCSR 330 3
176532 RBUF
176534 XCSR 334 3
176536 XBUF
176540 RCSR 340 4
176542 RBUF
176544 XCSR 344 4
176546 XBUF
176550 RCSR 350 5
176552 RBUF
176554 XCSR 354 5
176556 XBUF
176560 RCSR 360 6
176562 RBUF
176564 XCSR 364 6
176566 XBUF
176570* RCSR 370 7
176572 RBUF
176574 XCSR 374 7
176576 XBUF
*If the console is selected it resides at channel 7
and the last four addresses in this table are:
177560 RCSR 60 7
177562 RBUF
177564 XCSR 64 7
177566 XBUF

TABLE 3-1: STANDARD ADDRESS AND VECTOR ASSIGNMENTS

 June 9, 1983
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3.2 DEVICE ADDRESS FORMAT

The address configurations are listed in Table 3-2.

17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
I... 1 1 1 1 I 1 IA12 All1Al0 IA9
,
A8 I A7 I A6 I J

Bank 71
Selected (1 )

Initial Address
(See Section 2.2)

Channel (Device) Select

000 = cn 0
001 = CH 1
010 = CH 2
011 = CH 3
100 = CH 4
101 = CH 5
110 = CH 6
11 1 = CH 7

Register Select
00 = RCSR
01 = RBUF
10 = XCSR
1 1 = XBUF

Byte Pointer
 June 9, 1983
Page 16

3.3 VECTOR INTERRUPT FORMAT

The interrupt vector format is shown below.

17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
V6

Initial Vector
(See Section 2.3)

Channel Requesting Interrupt

000 = CH 0
001 = ClI 1
010 = CH 2
011 = CH 3
100 = CH 4
101 = CH 5
110 = CH 6
111 = CH 7

Interrupt ________________________________________________ ~

o = Receiver Interrupt
1 = Transmitter Interrupt

All bits not used are read as O.

 June 10, 1983
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3.4 WORD FORMATS

The four word formats, one for each device register within a
channel, are described in the following sections.

Receive Control/Status Register (RCSR)

12 11 10 8 7 6
RX RX
DN INT

RX DN RECEIVER DONE. Set when an entire character has been

received and is ready for input to the CPU. Cleared
when RBUF is read or BINIT L signal goes true. If RX
INT (bit 6) is set, setting RX DN starts an interrupt
sequence. Read only.
RX INT RECEIVER INTERRUPT ENABLE. Set under pro~ram control
to generate a receiver interrupt request (when a char-
acter is ready for input to the processor signified by
bit 7 being set). Cleared under program control or by
BINIT signal. Read/write.
All bits not used are read as 0.
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June 10., 1983

Page 18

Receiver Buffer (RBUF)

15 7 6 5 4 3 2 1 o
CH OVR DATA BITS
ERR RUN

CH ERR CHANNEL ERROR STATUS. Logical OR of bits 14, 13, and

12. Read only.
OVR OVERRUN ERROR. When set, indicates that the reading
RUN of the previously received character was not completed
(receiver done not cleared) prior to receiving a new
character. Cleared by BINIT signal. Read only.
NOTE: When "back-to-back" characters are received, one
full character time is allowed from the time instant
receiver done (bit 7) is set to the occurrence of an
overrun error.
FRM FRAMING ERROR. When set, indicates that the character
ERR read had no valid stop bit. Cleared by BINIT signal.
Read only.
PAR PARITY ERROR. When set, indicates that the parity
ERR received does not agree with the expected parity. This
bit is always 0 if no-parity operation is configured
for the channel. Read only.
NOTE: Error bits remain valid until the next character
is received, at which time the error bits are updated.
DATA DATA BITS. Contains seven or eight data bits in a
BITS right-justified format. Bit 7 = 0 when 7 data bits are
enabled. Read only.
All bits not used are read as O.
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June 9, 1983
Page 19

Transmit Control/Status Register (XCSR)

BR3- PROGRAMMABLE BAUD RATE SELECT. When set, these bits

BRO choose a baud rate from 50-19.2K baud. See section
2.4. Write only.
BR PROGRAMMABLE BAUD RATE ENABLE. Must be set in order to
ENB select a new baud rate indicated by bits 12-15. Write
only.
XMT TRANSMIT READY. Set when XBUF is empty and can accept
RDY another character for transmission. It is also set by
INIT, during power-up or during a reset instruction.
Read only.
XMT TRANSMIT INTERRUPT ENABLE. Set under program control
INT when it is desired to generate a transmitter interrupt
request when transmitter is ready to accept a character
for transmission. Cleared under pro~ram control, during
power-up or reset instruction. Read/write.
XMT TRANSMIT BREAK. Set or reset under program control.
BRK When set, a continuous space level is transmitted.
However, transmit done and transmit interrupt can still
operate, allowing software timing of break. When not
set, normal character transmission can occur. Cleared
by BINIT. Read/write.
All bits not used are read as O.

3.4.4 Transmit Buffer (XBUF)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
DATA BITS

Bits 0-7 contain the seven or eight right-justified data bits.

Loaded under program control for serial transmission. Bits not
used are read as O.

-- ------~--------~-. "." .~.-----

 CONNECTOR A CONNECTOR B

PIN SIGNAL NAME PIN SIGNAL NAME

AAI Not Used BAI BDCOK H

ABI Not Used BBI Not Used
ACI Not Used BCI Not Used
ADI Not Used BDI Not Used
AEI Not Used BEl Not Used
AFI Not Used BFI Not Used
AHI Not Used BHl Not Used
AJI GND BJI GND
AKI Not Used BKI Not Used
ALI Not Used BLI Not Used
AMI GND BMI GND
ANI Not Used BNI Not Used
API BHALH BPI Not Used·
ARl Not Used BRI Not Used
ASI Not Used BSI Not Used
ATI GND BTl GND
AUl Not Used BUl Not Used
AVI Not Used BVl +5VDC
AA2 +5VDC BA2 +5VDC
AB2 Not Used BB2 Not Used
AC2 GND BC2 GND
AD2 +l2VDC BD2 Not Used
AE2 BOOUT L BE2 BDAL2 L
AF2 BRPLY L BF2 BDAL3 L
AH2 BDIN L BH2 BDAL4 L
AJ2 BSYNC L BJ2 BOAL5 L
AK2 Not Used BK2 BDAL6 L
AL2 BIRQL BL2 BDAL7 L
AM2 BIAKI L BM2 BDALS L
AN2 BIAKO L BN2 BDAL9 L
AP2 BBS7 L BP2 BDALlO L
AR2 BDMGI L BR2 BDALll L
AS2 BDMGO L BS2 BDALl2 L
AT2 BINIT L BT2 BDALl3 L
AU2 BDALO L BU2 BDALl4 L
AV2 BDALI L BV2 BDALl5 L

BUS SIGNALS AND PINS ASSIGNMENTS

A-l
... ,.