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What Is Verilog?: Ch#1: Introduction

This document outlines chapters in an introduction to Verilog textbook. Chapter 1 introduces Verilog and the chip design flow. Chapter 2 covers Verilog data types including scalars, vectors, and arrays. Chapter 3 discusses Verilog building blocks such as modules, ports, always blocks, initial blocks and generate statements. Chapter 4 examines behavioral modeling with block statements, assignment types, control flow and functions. Chapter 5 concludes with gate and switch level modeling examples.

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T V Murali Krishna
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35 views1 page

What Is Verilog?: Ch#1: Introduction

This document outlines chapters in an introduction to Verilog textbook. Chapter 1 introduces Verilog and the chip design flow. Chapter 2 covers Verilog data types including scalars, vectors, and arrays. Chapter 3 discusses Verilog building blocks such as modules, ports, always blocks, initial blocks and generate statements. Chapter 4 examines behavioral modeling with block statements, assignment types, control flow and functions. Chapter 5 concludes with gate and switch level modeling examples.

Uploaded by

T V Murali Krishna
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Ch#1: Introduction

What is Verilog?
Introduction to Verilog
Chip Design Flow
Chip Abstraction Layers

Ch#2: Data Types


Verilog Syntax
Verilog Data types
Verilog Scalar/Vector
Verilog Arrays

Ch#3: Building Blocks


Verilog Module
Verilog Port
Verilog Module Instantiations
Verilog assign statements
Verilog assign examples
Verilog Operators
Verilog always block
Combo Logic with always
Sequential Logic with always
Verilog initial block
Verilog in a nutshell
Verilog generate
Verilog Sequence Detector
Verilog Pattern Detector

Ch#4: Behavioral modeling


Verilog Block Statements
Verilog Assignment Types
Verilog Blocking/Non-blocking
Verilog Control Flow
Verilog for Loop
Verilog case Statement
Verilog Functions
Verilog Tasks
Verilog Parameters
Verilog `ifdef `elsif
Verilog Delay Control
Ch#4: Simulation
Verilog Simulation Basics
Verilog Timescale
Verilog Scheduling Regions
Verilog Display tasks
Ch#5: Gate/Switch modeling
Gate Level Modeling
Gate Level Examples
Gate Delays
Switch Level Modeling

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