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Junction Field Effect Transistor

The Junction Field Effect Transistor, or JFET, is a voltage controlled three terminal unipolar semiconductor
device available in N-channel and P-channel con gurations

In the Bipolar Junction Transistor  tutorials, we saw that the output Collector current of the transistor is
proportional to input current owing into the Base terminal of the device, thereby making the bipolar transistor
a “CURRENT” operated device (Beta model) as a smaller current can be used to switch a larger load current.

The Field Effect Transistor, or simply FET however, uses the voltage that is applied to their input terminal, called
the Gate to control the current owing through them resulting in the output current being proportional to the
input voltage. As their operation relies on an electric eld (hence the name eld effect) generated by the input
Gate voltage, this then makes the Field Effect Transistor a “VOLTAGE” operated device.

The Field Effect Transistor is a three terminal unipolar semiconductor device that has very similar
characteristics to those of their Bipolar Transistor counterparts. For example, high ef ciency, instant operation,
robust and cheap and can be used in most electronic circuit applications to replace their equivalent bipolar
junction transistors (BJT) cousins.

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Field effect transistors can be made much smaller than an equivalent BJT
transistor and along with their low power consumption and power dissipation
makes them ideal for use in integrated circuits such as the CMOS range of
digital logic chips.

We remember from the previous tutorials that there are two basic types of
bipolar transistor construction, NPN and PNP, which basically describes the
physical arrangement of the P-type and N-type semiconductor materials from
Typical Field Effect
which they are made. This is also true of FET’s as there are also two basic
Transistor
classi cations of Field Effect Transistor, called the N-channel FET and the P-
channel FET.

The eld effect transistor is a three terminal device that is constructed with no PN-junctions within the main
current carrying path between the Drain and the Source terminals. These terminals correspond in function to
the Collector and the Emitter respectively of the bipolar transistor. The current path between these two
terminals is called the “channel” which may be made of either a P-type or an N-type semiconductor material.

The control of current owing in this channel is achieved by varying the voltage applied to the Gate. As their
name implies, Bipolar Transistors are “Bipolar” devices because they operate with both types of charge carriers,
Holes and Electrons. The Field Effect Transistor on the other hand is a “Unipolar” device that depends only on
the conduction of electrons (N-channel) or holes (P-channel).

The Field Effect Transistor has one major advantage over its standard bipolar transistor cousins, in that their
input impedance, ( Rin ) is very high, (thousands of Ohms), while the BJT is comparatively low. This very high
input impedance makes them very sensitive to input voltage signals, but the price of this high sensitivity also
means that they can be easily damaged by static electricity.

There are two main types of eld effect transistor, the Junction Field Effect Transistor or JFET and the
Insulated-gate Field Effect Transistor or IGFET), which is more commonly known as the standard Metal Oxide
Semiconductor Field Effect Transistor or MOSFET for short.

The Junction Field Effect Transistor

We saw previously that a bipolar junction transistor is constructed using two PN-junctions in the main current
carrying path between the Emitter and the Collector terminals. The Junction Field Effect Transistor (JUGFET or
JFET) has no PN-junctions but instead has a narrow piece of high resistivity semiconductor material forming a
“Channel” of either N-type or P-type silicon for the majority carriers to ow through with two ohmic electrical
connections at either end commonly called the Drain and the Source respectively.

There are two basic con gurations of junction eld effect transistor, the N-channel JFET and the P-channel
JFET. The N-channel JFET’s channel is doped with donor impurities meaning that the ow of current through
the channel is negative (hence the term N-channel) in the form of electrons.
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Likewise, the P-channel JFET’s channel is doped with acceptor impurities meaning that the ow of current
through the channel is positive (hence the term P-channel) in the form of holes. N-channel JFET’s have a greater
channel conductivity (lower resistance) than their equivalent P-channel types, since electrons have a higher
mobility through a conductor compared to holes. This makes the N-channel JFET’s a more ef cient conductor
compared to their P-channel counterparts.

We have said previously that there are two ohmic electrical connections at either end of the channel called the
Drain and the Source. But within this channel there is a third electrical connection which is called the Gate
terminal and this can also be a P-type or N-type material forming a PN-junction with the main channel.

The relationship between the connections of a junction eld effect transistor and a bipolar junction transistor
are compared below.

Comparison of Connections between a JFET and a BJT

Bipolar Transistor (BJT) Field Effect Transistor (FET)

Emitter – (E)     >>     Source – (S)

Base – (B)     >>     Gate – (G)

Collector – (C)     >>     Drain – (D)

The symbols and basic construction for both con gurations of JFETs are shown below.

The semiconductor “channel” of the Junction Field Effect Transistor is a resistive path through which a voltage
VDS causes a current ID to ow and as such the junction eld effect transistor can conduct current equally well
in either direction. As the channel is resistive in nature, a voltage gradient is thus formed down the length of the
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channel with this voltage becoming less positive as we go from the Drain terminal to the Source terminal.

The result is that the PN-junction therefore has a high reverse bias at the Drain terminal and a lower reverse
bias at the Source terminal. This bias causes a “depletion layer” to be formed within the channel and whose
width increases with the bias.

The magnitude of the current owing through the channel between the Drain and the Source terminals is
controlled by a voltage applied to the Gate terminal, which is a reverse-biased. In an N-channel JFET this Gate
voltage is negative while for a P-channel JFET the Gate voltage is positive.

The main difference between the JFET and a BJT device is that when the JFET junction is reverse-biased the
Gate current is practically zero, whereas the Base current of the BJT is always some value greater than zero.

Biasing of an N-channel JFET

The cross sectional diagram above shows an N-type semiconductor channel with a P-type region called the Gate
diffused into the N-type channel forming a reverse biased PN-junction and it is this junction which forms the
depletion region around the Gate area when no external voltages are applied. JFETs are therefore known as
depletion mode devices.

This depletion region produces a potential gradient which is of varying thickness around the PN-junction and
restrict the current ow through the channel by reducing its effective width and thus increasing the overall
resistance of the channel itself.

Then we can see that the most-depleted portion of the depletion region is in between the Gate and the Drain,
while the least-depleted area is between the Gate and the Source. Then the JFET’s channel conducts with zero
bias voltage applied (ie, the depletion region has near zero width).

With no external Gate voltage ( VG = 0 ), and a small voltage ( VDS ) applied between the Drain and the Source,
maximum saturation current ( IDSS ) will ow through the channel from the Drain to the Source restricted only
by the small depletion region around the junctions.

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If a small negative voltage ( -V GS ) is now applied to the Gate the size of the depletion region begins to increase
reducing the overall effective area of the channel and thus reducing the current owing through it, a sort of
“squeezing” effect takes place. So by applying a reverse bias voltage increases the width of the depletion region
which in turn reduces the conduction of the channel.

Since the PN-junction is reverse biased, little current will ow into the gate connection. As the Gate voltage ( -
VGS ) is made more negative, the width of the channel decreases until no more current ows between the Drain
and the Source and the FET is said to be “pinched-off” (similar to the cut-off region for a BJT). The voltage at
which the channel closes is called the “pinch-off voltage”, ( VP ).

JFET Channel Pinched-off

In this pinch-off region the Gate voltage, VGS controls the channel current and VDS has little or no effect.

The result is that the FET acts more like a voltage controlled resistor which has zero resistance
when VGS = 0 and maximum “ON” resistance ( RDS ) when the Gate voltage is very negative.
Under normal operating conditions, the JFET gate is always negatively biased relative to the
source.

It is essential that the Gate voltage is never positive since if it is all the channel current will ow JFET Model
to the Gate and not to the Source, the result is damage to the JFET. Then to close the channel:

No Gate Voltage ( VGS ) and VDS is increased from zero.

No VDS and Gate control is decreased negatively from zero.
VDS and VGS varying.

The P-channel Junction Field Effect Transistor operates exactly the same as the N-channel above, with the
following exceptions: 1). Channel current is positive due to holes, 2). The polarity of the biasing voltage needs to
be reversed.

The output characteristics of an N-channel JFET with the gate short-circuited to the source is given as: /
Output characteristic V-I curves of a typical junction FET

The voltage VGS applied to the Gate controls the current owing between the Drain and the Source terminals.
VGS refers to the voltage applied between the Gate and the Source while VDS refers to the voltage applied
between the Drain and the Source.

Because a Junction Field Effect Transistor is a voltage controlled device, “NO current ows into the gate!” then
the Source current ( IS ) owing out of the device equals the Drain current owing into it and therefore ( ID = IS ).

The characteristics curves example shown above, shows the four different regions of operation for a JFET and
these are given as:

Ohmic Region – When VGS = 0 the depletion layer of the channel is very small and the JFET
acts like a voltage controlled resistor.

Cut-off Region – This is also known as the pinch-off region were the Gate voltage, VGS is
suf cient to cause the JFET to act as an open circuit as the channel resistance is at maximum.

Saturation or Active Region – The JFET becomes a good conductor and is controlled by

the Gate-Source voltage, ( VGS ) while the Drain-Source voltage, ( VDS ) has little or no effect.

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 Breakdown Region – The voltage between the Drain and the Source, ( VDS ) is high enough
to causes the JFET’s resistive channel to break down and pass uncontrolled maximum
current.

The characteristics curves for a P-channel junction eld effect transistor are the same as those above, except
that the Drain current ID decreases with an increasing positive Gate-Source voltage, VGS.

The Drain current is zero when VGS = VP. For normal operation, VGS is biased to be somewhere between VP
and 0. Then we can calculate the Drain current, ID for any given bias point in the saturation or active region as
follows:

Drain current in the active region.

Note that the value of the Drain current will be between zero (pinch-off) and IDSS (maximum current). By
knowing the Drain current ID and the Drain-Source voltage VDS the resistance of the channel ( RDS ) is given as:

Drain-Source Channel Resistance.

Where: gm is the “transconductance gain” since the JFET is a voltage controlled device and which represents the
rate of change of the Drain current with respect to the change in Gate-Source voltage.

Modes of FET’s
Like the bipolar junction transistor, the eld effect transistor being a three terminal device is capable of three
distinct modes of operation and can therefore be connected within a circuit in one of the following
con gurations.

Common Source (CS) Con guration

In the Common Source con guration (similar to common emitter), the input is applied to the Gate and its output
is taken from the Drain as shown. This is the most common mode of operation of the FET due to its high input
impedance and good voltage ampli cation and as such Common Source ampli ers are widely used.

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 The common source mode of FET connection is generally used audio
frequency ampli ers and in high input impedance pre-amps and stages.
Being an amplifying circuit, the output signal is 180o “out-of-phase” with the
input.

Common Gate (CG) Con guration

In the Common Gate con guration
(similar to common base), the input is
applied to the Source and its output is
taken from the Drain with the Gate
connected directly to ground (0v) as
shown. The high input impedance feature
of the previous connection is lost in this
con guration as the common gate has a low input impedance, but a high output impedance.

This type of FET con guration can be used in high frequency circuits or in impedance matching circuits were a
low input impedance needs to be matched to a high output impedance. The output is “in-phase” with the input.

Common Drain (CD) Con guration

In the Common Drain con guration (similar to common collector), the input
is applied to the Gate and its output is taken from the Source. The common
drain or “source follower” con guration has a high input impedance and a
low output impedance and near-unity voltage gain so is therefore used in
buffer ampli ers. The voltage gain of the source follower con guration is less
than unity, and the output signal is “in-phase”, 0o with the input signal.

This type of con guration is referred to as “Common Drain” because there is

no signal available at the drain connection, the voltage present, +VDD just provides a bias. The output is in-
phase with the input.

The JFET Ampli er

Just like the bipolar junction transistor, JFET’s can be used to make single stage class A ampli er circuits with the
JFET common source ampli er and characteristics being very similar to the BJT common emitter circuit. The
main advantage JFET ampli ers have over BJT ampli ers is their high input impedance which is controlled by
the Gate biasing resistive network formed by R1 and R2 as shown.

Biasing of JFET Ampli er

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This common source (CS) ampli er circuit is biased in class “A” mode by the voltage divider network formed by
resistors R1 and R2. The voltage across the Source resistor RS is generally set to be about one quarter of VDD, (
VDD /4 ) but can be any reasonable value.

The required Gate voltage can then be calculated from this RS value. Since the Gate current is zero, (IG = 0) we
can set the required DC quiescent voltage by the proper selection of resistors R1 and R2.

The control of the Drain current by a negative Gate potential makes the Junction Field Effect Transistor useful
as a switch and it is essential that the Gate voltage is never positive for an N-channel JFET as the channel
current will ow to the Gate and not the Drain resulting in damage to the JFET. The principals of operation for a
P-channel JFET are the same as for the N-channel JFET, except that the polarity of the voltages need to be
reversed.

In the next tutorial about Transistors, we will look at another type of Field Effect Transistor called a MOSFET
whose Gate connection is completely isolated from the main current carrying channel.

117 Comments

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AYONELISA LANDE
I do not see the three connections of a junction eld effect transistor

Posted on August 21st 2019 | 3:56 pm

 Reply

Jean
Is the formula for gm not wrong, you are using Vds, I think it should be Vgs?

Posted on July 19th 2019 | 7:48 am

 Reply

Theophilus
This really helped my understanding on JFET… I can now write my exams with con dence. Thanks /
Posted on July 14th 2019 | 1:38 pm
 Reply

Anurag kumar
I read your in Hindi

Posted on May 16th 2019 | 3:25 pm

 Reply

Wayne Storr
ALL the tutorials are in English, we do not do Hindi.

Posted on May 16th 2019 | 4:47 pm

 Reply

Usman
Its best one.. So nicely explained

Posted on May 15th 2019 | 7:25 pm

 Reply

Sarfraz Ahmed

Posted on May 07th 2019 | 9:04 pm

 Reply

Abdoul
Bsr. Je cour /
Posted on April 21st 2019 | 8:47 pm
 Reply

Japheth
Good content, I have enjoyed reading!!!

Posted on April 19th 2019 | 2:28 am

 Reply

Buvanesh
Its too amazing

Posted on April 18th 2019 | 1:44 pm

 Reply

Ranjay
Thanks so much for the detailed explanation. However, would like to clarify the situation after “pinch-off”.
Does the two depletion regions merge together or a thin gap is left no matter how large a voltage is
applied at the drain (less than breakdown)?

Posted on April 17th 2019 | 12:51 am

 Reply

Wayne Storr
The region closes but there will always be a very small leakage current, nA or pA, depending on
the device.

Posted on April 17th 2019 | 11:40 am

 Reply

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