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Harsh Sharma Mini Project On Washing Machine: Block Diagram

The document contains code for a washing machine state machine written in Verilog. It defines states for checking the door, filling with water, adding detergent, running the cycle, draining water, and spinning. The state machine uses signals for inputs like start, door close, and timeouts and outputs like motor on and valve controls. It also includes a testbench module to simulate the state machine.

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Harsh Sharma
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231 views9 pages

Harsh Sharma Mini Project On Washing Machine: Block Diagram

The document contains code for a washing machine state machine written in Verilog. It defines states for checking the door, filling with water, adding detergent, running the cycle, draining water, and spinning. The state machine uses signals for inputs like start, door close, and timeouts and outputs like motor on and valve controls. It also includes a testbench module to simulate the state machine.

Uploaded by

Harsh Sharma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as RTF, PDF, TXT or read online on Scribd
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HARSH SHARMA

MINI PROJECT ON
WASHING MACHINE
BLOCK DIAGRAM

SIGNAL SPECIFICATION
FSM DIAGRAM
CODE
module wm
(done,motor_on,fill_valve_on,drain_valve_on,door_lock,rst,start,door_close,filled,drain,added,c
ycle_time_out,spin_time_out);

input rst,start,door_close,added,cycle_time_out,spin_time_out;
output reg done,motor_on,fill_valve_on,drain_valve_on,door_lock;

input [1:0] drain,filled;

parameter check_door=3'b000,

fill_water=3'b001,

add_det=3'b011,

cycle=3'b010,

drain_water=3'b101,

spin=3'b111;

reg clk;

reg [2:0]d,q;

initial begin

clk=0;

end

always

#10 clk=~clk;

always @(start,door_close,added,cycle_time_out,spin_time_out,filled,drain,q)

begin

done=0;

motor_on=0;

fill_valve_on=0;

drain_valve_on=0;

door_lock=1;

case(q)

check_door: if (start==1 && door_close==1) begin

d<=fill_water;
end

else begin

d<=check_door;

end

fill_water: if(filled==2'b00) begin

d<=fill_water;

fill_valve_on=1;

end

else if(filled==2'b01)begin

d<=add_det;

end

else begin

d<=cycle;

end

add_det: if(added==0) begin

d<=add_det;

end

else begin

d<=cycle;

end

cycle: if(cycle_time_out==0) begin

d<=cycle;

motor_on<=1;

end
else begin

d<=drain_water;

end

drain_water: if(drain==2'b00) begin

d<=drain_water;

drain_valve_on=1;

end

else if(drain==2'b01) begin

d<=spin;

drain_valve_on=1;

end

else begin

d<=fill_water;

end

spin: if(spin_time_out==0) begin

d<=spin;

drain_valve_on=1;

end

else begin

d<=check_door;

done<=1;

door_lock<=0;

end

default : begin

done=0;
motor_on=0;

fill_valve_on=0;

drain_valve_on=0;

door_lock=1;

q=0;

d<=check_door;

end

endcase

end

always @(posedge clk or negedge rst) begin

if(~rst)

q<=0;

else

q<=d;

end

endmodule

module tb_wm;

reg rst,start,door_close,added,cycle_time_out,spin_time_out;

wire done,motor_on,fill_valve_on,drain_valve_on,door_lock;

reg[1:0] filled,drain;

wm
m1(done,motor_on,fill_valve_on,drain_valve_on,door_lock,rst,start,door_close,filled,drain,adde
d,cycle_time_out,spin_time_out);

initial begin

$monitor("$time=%d,done=%b,motor_on=%b,fill_valve_on=%b,drain_valve_on=%b,door_lock=
%b,rst=%b,start=%b,door_close=%b,filled=%b,drain=%b,added=%b,cycle_time_out=
%b,spin_time_out=%b",$time
,done,motor_on,fill_valve_on,drain_valve_on,door_lock,rst,start,door_close,filled,drain,added,c
ycle_time_out,spin_time_out);

end

initial begin

rst=0;

#11 rst=1;

end

initial begin

#30 start=1;door_close=1;

#20 filled=2'b00;

#20 filled=2'b01;

#20 added=1;

#20 cycle_time_out=0;

#20 cycle_time_out=1;

#20 drain=2'b00;

#20 drain=2'b01;

#20 spin_time_out=0;

#20 spin_time_out=1;

end

endmodule

OUTPUT
WAVE

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