Chapter 10

Analog-to-Digital Converter (S08ADC12V1)

10.1 Overview
The 12-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation
within an integrated microcontroller system-on-chip.
NOTE
MC9S08JM60 series devices operate at a higher voltage range (2.7 V to
5.5 V) and do not include stop1 mode. Therefore, please disregard
references to stop1.

10.1.1 Module Configurations

This section provides information for configuring the ADC on this device.

10.1.1.1 Channel Assignments

The ADC channel assignments for the MC9S08JM60 Series devices are shown in the table below.
Reserved channels convert to an unknown value.

MC9S08JM60 Series Data Sheet, Rev. 3

Freescale Semiconductor 135
Chapter 10 Analog-to-Digital Converter (S08ADC12V1)

Table 10-1. ADC Channel Assignment

ADCH Channel Input Pin Control ADCH Channel Input Pin Control
00000 AD0 PTB0/MISO2/ADP0 ADPC0 10000 AD16 VREFL N/A
00001 AD1 PTB1/MOSI2/ADP1 ADPC1 10001 AD17 VREFL N/A
00010 AD2 PTB2/SPSCK2/ADP2 ADPC2 10010 AD18 VREFL N/A
00011 AD3 PTB3/SS2/ADP3 ADPC3 10011 AD19 VREFL N/A
00100 AD4 PTB4/KBIP4/ADP4 ADPC4 10100 AD20 VREFL N/A
00101 AD5 PTB5/KBIP5/ADP5 ADPC5 10101 AD21 Reserved N/A
00110 AD6 PTB6/ADP6 ADPC6 10110 AD22 Reserved N/A
00111 AD7 PTB7/ADP7 ADPC7 10111 AD23 Reserved N/A
01000 AD8 PTD0/ADP8/ACMP+ ADPC8 11000 AD24 Reserved N/A
01001 AD9 PTD1/ADP9/ACMP- ADPC9 11001 AD25 Reserved N/A
01010 AD10 PTD3/KBIP3/ADP10 ADPC10 11010 AD26 Temperature N/A
Sensor1
01011 AD11 PTD4/ADP11 ADPC11 11011 AD27 Internal Bandgap N/A
01100 AD12 VREFL ADPC12 11100 Reserved N/A
01101 AD13 VREFL ADPC13 11101 VREFH VREFH N/A
01110 AD14 VREFL ADPC14 11110 VREFL VREFL N/A
01111 AD15 VREFL ADPC15 11111 module None N/A
disabled
1
For more information, see Section 10.1.1.5, “Temperature Sensor.”

NOTE
Selecting the internal bandgap channel requires BGBE =1 in SPMSC1 see
Section 5.7.7, “System Power Management Status and Control 1 Register
(SPMSC1).” For value of bandgap voltage reference see Appendix A.8,
“Analog Comparator (ACMP) Electricals.”

10.1.1.2 Alternate Clock

The ADC is capable of performing conversions using the MCU bus clock, the bus clock divided by two,
the local asynchronous clock (ADACK) within the module, or the alternate clock (ALTCLK). The
ALTCLK on this device is the MCGERCLK.
The selected clock source must run at a frequency such that the ADC conversion clock (ADCK) runs at a
frequency within its specified range (fADCK) after being divided down from the ALTCLK input as
determined by the ADIV bits.
ALTCLK is active while the MCU is in wait mode provided the conditions described above are met. This
allows ALTCLK to be used as the conversion clock source for the ADC while the MCU is in wait mode.
ALTCLK cannot be used as the ADC conversion clock source while the MCU is in stop3.

10.1.1.3 Hardware Trigger

The RTC on this device can be enabled as a hardware trigger for the ADC module by setting the

MC9S08JM60 Series Data Sheet, Rev. 3

136 Freescale Semiconductor
 Chapter 10 Analog-to-Digital Converter (S08ADC12V1)

ADCSC2[ADTRG] bit. When enabled, the ADC will be triggered every time RTCINT matches
RTCMOD. The RTC interrupt does not have to be enabled to trigger the ADC.
The RTC can be configured to cause a hardware trigger in MCU run, wait, and stop3.

10.1.1.4 Analog Pin Enables

The ADC on MC9S08JM60 series contains only two analog pin enable registers, APCTL1 and APCTL2.

10.1.1.5 Temperature Sensor

The ADC module includes a temperature sensor whose output is connected to one of the ADC analog
channel inputs. Equation 10-1 provides an approximate transfer function of the temperature sensor.

Temp = 25 – ((VTEMP – VTEMP25) ÷ m) Eqn. 10-1

where:
— VTEMP is the voltage of the temperature sensor channel at the ambient temperature.
— VTEMP25 is the voltage of the temperature sensor channel at 25°C.
— m is the hot or cold voltage versus temperature slope in V/°C.
For temperature calculations, use the VTEMP25 and m values from the ADC Electricals table.
In application code, the user reads the temperature sensor channel, calculates VTEMP, and compares to
VTEMP25. If VTEMP is greater than VTEMP25, the cold slope value is applied in Equation 10-1. If VTEMP
is less than VTEMP25 the hot slope value is applied in Equation 10-1.
To improve accuracy, calibrate the bandgap voltage reference and temperature sensor. Calibrating at
25 °C will improve accuracy to ±4.5°C. Calibration at 3 points, –40°C, 25°C, and 125°C will improve
accuracy to ±2.5°C. Once calibration has been completed, the user will need to calculate the slope for both
hot and cold. In application code, the user would then calculate the temperature using Equation 10-1 as
detailed above and then determine if the temperature is above or below 25°C. Once determined, if the
temperature is above or below 25°C, the user can recalculate the temperature using the hot or cold slope
value obtained during calibration.

10.1.2 Low-Power Mode Operation

The ADC is capable of running in stop3 mode but requires LVDSE and LVDE in SPMSC1 to be set.

MC9S08JM60 Series Data Sheet, Rev. 3

Freescale Semiconductor 137
Chapter 10 Analog-to-Digital Converter (S08ADC12V1)

USBDP
ON-CHIP ICE AND USBDN
HCS08 CORE
DEBUG MODULE (DBG)

PORT A
6
PTA5– PTA0
USB SIE
BKGD/MS FULL SPEED PTB7/ADP7
BDC CPU USB PTB6/ADP6
USB ENDPOINT TRANSCEIVER
RAM PTB5/KBIP5/ADP5

PORT B
PTB4/KBIP4/ADP4
SS2
PTB3/SS2/ADP3
SPSCK2
RESET HCS08 SYSTEM CONTROL 8-/16-BIT SERIAL PERIPHERAL PTB2/SPSCK2/ADP2
MOSI2
INTERFACE MODULE (SPI2) PTB1/MOSI2/ADP1
MISO2 PTB0/MISO2/ADP0
RESETS AND INTERRUPTS
MODES OF OPERATION PTC6
IRQ/TPMCLK RxD2
POWER MANAGEMENT PTC5/RxD2
SERIAL COMMUNICATIONS
INTERFACE MODULE (SCI2) PTC4

PORT C
TxD2 PTC3/TxD2
COP IRQ LVD
PTC2
SDA
PTC1/SDA
IIC MODULE (IIC) SCL
PTC0/SCL

VDDAD
12-CHANNEL, 12-BIT 8 PTD7
VSSAD
ANALOG-TO-DIGITAL 4 PTD6
VREFL
CONVERTER (ADC) PTD5
VREFH PTD4/ADP11

PORT D
PTD3/KBIP3/ADP10
USER Flash (IN BYTES) PTD2/KBIP2/ACMPO
MC9S08JM60 = 60,912 ACMP–
PTD1/ADP9/ACMP–
ANALOG COMPARATOR ACMP+
MC9S08JM32 = 32,768 PTD0/ADP8/ACMP+
(ACMP)
ACMPO
SS1 PTE7/SS1
USER RAM (IN BYTES) SPSCK1
8-/16-BIT SERIAL PERIPHERAL PTE6/SPSCK1
MC9S08JM60 = 4096 MOSI1
INTERFACE MODULE (SPI1) PTE5/MOSI1
MC9S08JM32 = 2048
MISO1
PTE4/MISO1
TPMCLK

PORT E
6-CHANNEL TIMER/PWM TPM1CH1
MULTI-PURPOSE CLOCK PTE3/TPM1CH1
MODULE (TPM1) TPM1CH0
GENERATOR (MCG) PTE2/TPM1CH0
TPM1CHx 4
RxD1 PTE1/RxD1
SERIAL COMMUNICATIONS
VSSOSC LOW-POWER OSCILLATOR TxD1 PTE0/TxD1
INTERFACE MODULE (SCI1)
PTF7
VDD SYSTEM TPMCLK PTF6
VOLTAGE 2-CHANNEL TIMER/PWM TPM2CH1 PTF5/TPM2CH1
VSS TPM2CH0
PORT F

REGULATOR MODULE (TPM2) PTF4/TPM2CH0

PTF3/TPM1CH5
USB 3.3-V VOLTAGE REGULATOR KBIPx 4 PTF2/TPM1CH4
VUSB33
8-BIT KEYBOARD PTF1/TPM1CH3
INTERRUPT MODULE (KBI) KBIPx 4 PTF0/TPM1CH2
REAL-TIME COUNTER
(RTC) EXTAL PTG5/EXTAL
XTAL
PTG4/XTAL
PORT G

NOTES:
PTG3/KBIP7
1. Port pins are software configurable with pullup device if input port. PTG2/KBIP6
2. Pin contains software configurable pullup/pull-down device if IRQ is enabled PTG1/KBIP1
(IRQPE = 1). Pull-down is enabled if rising edge detect is selected (IRQEDG = 1) PTG0/KBIP0
3. IRQ does not have a clamp diode to VDD. IRQ must not be driven above VDD.
4. Pin contains integrated pullup device.
5. When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the
pullup device, KBEDGn can be used to reconfigure the pullup as a pull-down device.

Figure 10-1. MC9S08JM60 Series Block Diagram Highlighting ADC Block and Pins

MC9S08JM60 Series Data Sheet, Rev. 3

138 Freescale Semiconductor
 Analog-to-Digital Converter (S08ADC12V1)

10.1.3 Features
Features of the ADC module include:
• Linear successive approximation algorithm with 12-bit resolution
• Up to 28 analog inputs
• Output formatted in 12-, 10-, or 8-bit right-justified unsigned format
• Single or continuous conversion (automatic return to idle after single conversion)
• Configurable sample time and conversion speed/power
• Conversion complete flag and interrupt
• Input clock selectable from up to four sources
• Operation in wait or stop3 modes for lower noise operation
• Asynchronous clock source for lower noise operation
• Selectable asynchronous hardware conversion trigger
• Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value
• Temperature sensor

10.1.4 ADC Module Block Diagram

Figure 10-2 provides a block diagram of the ADC module.

MC9S08JM60 Series Data Sheet, Rev. 3

Freescale Semiconductor 139
Analog-to-Digital Converter (S08ADC12V1)

Compare true
3 ADCSC1 ADCCFG

COCO
AIEN

ADLSMP
complete

ADICLK
ADTRG

ADLPC
MODE
ADCO
ADCH

ADIV
Async
1 2 Clock Gen

ADACK

MCU STOP ADCK

Bus Clock
Clock
ADHWT Control Sequencer Divide
÷2
ALTCLK

initialize

transfer
sample

convert

abort
AD0
AIEN 1
•••

Interrupt
ADVIN COCO 2
SAR Converter
AD27

VREFH Data Registers

VREFL
Sum

Compare true
3
Compare
Logic
Value

ACFGT

Compare Value Registers ADCSC2

Figure 10-2. ADC Block Diagram

10.2 External Signal Description

The ADC module supports up to 28 separate analog inputs. It also requires four supply/reference/ground
connections.

Table 10-2. Signal Properties

Name Function

AD27–AD0 Analog Channel inputs

VREFH High reference voltage
VREFL Low reference voltage
VDDAD Analog power supply
VSSAD Analog ground

MC9S08JM60 Series Data Sheet, Rev. 3

140 Freescale Semiconductor
 Analog-to-Digital Converter (S08ADC12V1)

10.2.1 Analog Power (VDDAD)

The ADC analog portion uses VDDAD as its power connection. In some packages, VDDAD is connected
internally to VDD. If externally available, connect the VDDAD pin to the same voltage potential as VDD.
External filtering may be necessary to ensure clean VDDAD for good results.

10.2.2 Analog Ground (VSSAD)

The ADC analog portion uses VSSAD as its ground connection. In some packages, VSSAD is connected
internally to VSS. If externally available, connect the VSSAD pin to the same voltage potential as VSS.

10.2.3 Voltage Reference High (VREFH)

VREFH is the high reference voltage for the converter. In some packages, VREFH is connected internally to
VDDAD. If externally available, VREFH may be connected to the same potential as VDDAD or may be driven
by an external source between the minimum VDDAD spec and the VDDAD potential (VREFH must never
exceed VDDAD).

10.2.4 Voltage Reference Low (VREFL)

VREFL is the low-reference voltage for the converter. In some packages, VREFL is connected internally to
VSSAD. If externally available, connect the VREFL pin to the same voltage potential as VSSAD.

10.2.5 Analog Channel Inputs (ADx)

The ADC module supports up to 28 separate analog inputs. An input is selected for conversion through
the ADCH channel select bits.

10.3 Register Definition

These memory-mapped registers control and monitor operation of the ADC:
• Status and control register, ADCSC1
• Status and control register, ADCSC2
• Data result registers, ADCRH and ADCRL
• Compare value registers, ADCCVH and ADCCVL
• Configuration register, ADCCFG
• Pin control registers, APCTL1, APCTL2, APCTL3

10.3.1 Status and Control Register 1 (ADCSC1)

This section describes the function of the ADC status and control register (ADCSC1). Writing ADCSC1
aborts the current conversion and initiates a new conversion (if the ADCH bits are equal to a value other
than all 1s).

MC9S08JM60 Series Data Sheet, Rev. 3

Freescale Semiconductor 141
Analog-to-Digital Converter (S08ADC12V1)

7 6 5 4 3 2 1 0

R COCO
AIEN ADCO ADCH
W

Reset: 0 0 0 1 1 1 1 1

Figure 10-3. Status and Control Register (ADCSC1)

Table 10-3. ADCSC1 Field Descriptions

Field Description

7 Conversion Complete Flag. The COCO flag is a read-only bit set each time a conversion is completed when the
COCO compare function is disabled (ACFE = 0). When the compare function is enabled (ACFE = 1), the COCO flag is
set upon completion of a conversion only if the compare result is true. This bit is cleared when ADCSC1 is written
or when ADCRL is read.
0 Conversion not completed
1 Conversion completed

6 Interrupt Enable AIEN enables conversion complete interrupts. When COCO becomes set while AIEN is high,
AIEN an interrupt is asserted.
0 Conversion complete interrupt disabled
1 Conversion complete interrupt enabled

5 Continuous Conversion Enable. ADCO enables continuous conversions.

ADCO 0 One conversion following a write to the ADCSC1 when software triggered operation is selected, or one
conversion following assertion of ADHWT when hardware triggered operation is selected.
1 Continuous conversions initiated following a write to ADCSC1 when software triggered operation is selected.
Continuous conversions are initiated by an ADHWT event when hardware triggered operation is selected.

4:0 Input Channel Select. The ADCH bits form a 5-bit field that selects one of the input channels. The input channels
ADCH are detailed in Table 10-4.
The successive approximation converter subsystem is turned off when the channel select bits are all set. This
feature allows for explicit disabling of the ADC and isolation of the input channel from all sources. Terminating
continuous conversions this way prevents an additional, single conversion from being performed. It is not
necessary to set the channel select bits to all ones to place the ADC in a low-power state when continuous
conversions are not enabled because the module automatically enters a low-power state when a conversion
completes.

Table 10-4. Input Channel Select

ADCH Input Select

00000–01111 AD0–15
10000–11011 AD16–27
11100 Reserved
11101 VREFH
11110 VREFL
11111 Module disabled

MC9S08JM60 Series Data Sheet, Rev. 3

142 Freescale Semiconductor
 Analog-to-Digital Converter (S08ADC12V1)

10.3.2 Status and Control Register 2 (ADCSC2)

The ADCSC2 register controls the compare function, conversion trigger, and conversion active of the
ADC module.

7 6 5 4 3 2 1 0

R ADACT 0 0
ADTRG ACFE ACFGT R1 R1
W

Reset: 0 0 0 0 0 0 0 0
1
Bits 1 and 0 are reserved bits that must always be written to 0.

Figure 10-4. Status and Control Register 2 (ADCSC2)

Table 10-5. ADCSC2 Register Field Descriptions

Field Description

7 Conversion Active. Indicates that a conversion is in progress. ADACT is set when a conversion is initiated and
ADACT cleared when a conversion is completed or aborted.
0 Conversion not in progress
1 Conversion in progress

6 Conversion Trigger Select. Selects the type of trigger used for initiating a conversion. Two types of triggers are
ADTRG selectable: software trigger and hardware trigger. When software trigger is selected, a conversion is initiated
following a write to ADCSC1. When hardware trigger is selected, a conversion is initiated following the assertion
of the ADHWT input.
0 Software trigger selected
1 Hardware trigger selected

5 Compare Function Enable. Enables the compare function.

ACFE 0 Compare function disabled
1 Compare function enabled

4 Compare Function Greater Than Enable. Configures the compare function to trigger when the result of the
ACFGT conversion of the input being monitored is greater than or equal to the compare value. The compare function
defaults to triggering when the result of the compare of the input being monitored is less than the compare value.
0 Compare triggers when input is less than compare value
1 Compare triggers when input is greater than or equal to compare value

10.3.3 Data Result High Register (ADCRH)

In 12-bit operation, ADCRH contains the upper four bits of the result of a 12-bit conversion. In 10-bit
mode, ADCRH contains the upper two bits of the result of a 10-bit conversion. When configured for 10-bit
mode, ADR[11:10] are cleared. When configured for 8-bit mode, ADR[11:8] are cleared.
In 12-bit and 10-bit mode, ADCRH is updated each time a conversion completes except when automatic
compare is enabled and the compare condition is not met. When a compare event does occur, the value is
the addition of the conversion result and the two’s complement of the compare value. In 12-bit and 10-bit
mode, reading ADCRH prevents the ADC from transferring subsequent conversion results into the result
registers until ADCRL is read. If ADCRL is not read until after the next conversion is completed, the
intermediate conversion result is lost. In 8-bit mode, there is no interlocking with ADCRL.

MC9S08JM60 Series Data Sheet, Rev. 3

Freescale Semiconductor 143
Analog-to-Digital Converter (S08ADC12V1)

If the MODE bits are changed, any data in ADCRH becomes invalid.

7 6 5 4 3 2 1 0

R 0 0 0 0 ADR11 ADR10 ADR9 ADR8

Reset: 0 0 0 0 0 0 0 0

Figure 10-5. Data Result High Register (ADCRH)

10.3.4 Data Result Low Register (ADCRL)

ADCRL contains the lower eight bits of the result of a 12-bit or 10-bit conversion, and all eight bits of an
8-bit conversion. This register is updated each time a conversion completes except when automatic
compare is enabled and the compare condition is not met. In 12-bit and 10-bit mode, reading ADCRH
prevents the ADC from transferring subsequent conversion results into the result registers until ADCRL
is read. If ADCRL is not read until the after next conversion is completed, the intermediate conversion
results are lost. In 8-bit mode, there is no interlocking with ADCRH. If the MODE bits are changed, any
data in ADCRL becomes invalid.

7 6 5 4 3 2 1 0

R ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0

Reset: 0 0 0 0 0 0 0 0

Figure 10-6. Data Result Low Register (ADCRL)

10.3.5 Compare Value High Register (ADCCVH)

In 12-bit mode, the ADCCVH register holds the upper four bits of the 12-bit compare value. When the
compare function is enabled, these bits are compared to the upper four bits of the result following a
conversion in 12-bit mode.

7 6 5 4 3 2 1 0

R 0 0 0 0
ADCV11 ADCV10 ADCV9 ADCV8
W
Reset: 0 0 0 0 0 0 0 0

Figure 10-7. Compare Value High Register (ADCCVH)

MC9S08JM60 Series Data Sheet, Rev. 3

144 Freescale Semiconductor
 Analog-to-Digital Converter (S08ADC12V1)

In 10-bit mode, the ADCCVH register holds the upper two bits of the 10-bit compare value (ADCV[9:8]).
These bits are compared to the upper two bits of the result following a conversion in 10-bit mode when the
compare function is enabled.
In 8-bit mode, ADCCVH is not used during compare.

10.3.6 Compare Value Low Register (ADCCVL)

This register holds the lower 8 bits of the 12-bit or 10-bit compare value or all 8 bits of the 8-bit compare
value. When the compare function is enabled, bits ADCV[7:0] are compared to the lower 8 bits of the
result following a conversion in 12-bit, 10-bit or 8-bit mode.

7 6 5 4 3 2 1 0

R
ADCV7 ADCV6 ADCV5 ADCV4 ADCV3 ADCV2 ADCV1 ADCV0
W

Reset: 0 0 0 0 0 0 0 0

Figure 10-8. Compare Value Low Register (ADCCVL)

10.3.7 Configuration Register (ADCCFG)

ADCCFG selects the mode of operation, clock source, clock divide, and configures for low power and long
sample time.
7 6 5 4 3 2 1 0

R
ADLPC ADIV ADLSMP MODE ADICLK
W

Reset: 0 0 0 0 0 0 0 0

Figure 10-9. Configuration Register (ADCCFG)

Table 10-6. ADCCFG Register Field Descriptions

Field Description

7 Low-Power Configuration. ADLPC controls the speed and power configuration of the successive approximation
ADLPC converter. This optimizes power consumption when higher sample rates are not required.
0 High speed configuration
1 Low power configuration:The power is reduced at the expense of maximum clock speed.

6:5 Clock Divide Select. ADIV selects the divide ratio used by the ADC to generate the internal clock ADCK.
ADIV Table 10-7 shows the available clock configurations.

4 Long Sample Time Configuration. ADLSMP selects between long and short sample time. This adjusts the
ADLSMP sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for
lower impedance inputs. Longer sample times can also be used to lower overall power consumption when
continuous conversions are enabled if high conversion rates are not required.
0 Short sample time
1 Long sample time

MC9S08JM60 Series Data Sheet, Rev. 3

Freescale Semiconductor 145
Analog-to-Digital Converter (S08ADC12V1)

Table 10-6. ADCCFG Register Field Descriptions (continued)

Field Description

3:2 Conversion Mode Selection. MODE bits are used to select between 12-, 10-, or 8-bit operation. See Table 10-8.
MODE

1:0 Input Clock Select. ADICLK bits select the input clock source to generate the internal clock ADCK. See
ADICLK Table 10-9.

Table 10-7. Clock Divide Select

ADIV Divide Ratio Clock Rate

00 1 Input clock
01 2 Input clock ÷ 2
10 4 Input clock ÷ 4
11 8 Input clock ÷ 8

Table 10-8. Conversion Modes

MODE Mode Description

00 8-bit conversion (N=8)
01 12-bit conversion (N=12)
10 10-bit conversion (N=10)
11 Reserved

Table 10-9. Input Clock Select

ADICLK Selected Clock Source

00 Bus clock
01 Bus clock divided by 2
10 Alternate clock (ALTCLK)
11 Asynchronous clock (ADACK)

10.3.8 Pin Control 1 Register (APCTL1)

The pin control registers disable the I/O port control of MCU pins used as analog inputs. APCTL1 is used
to control the pins associated with channels 0–7 of the ADC module.
7 6 5 4 3 2 1 0

R
ADPC7 ADPC6 ADPC5 ADPC4 ADPC3 ADPC2 ADPC1 ADPC0
W

Reset: 0 0 0 0 0 0 0 0

Figure 10-10. Pin Control 1 Register (APCTL1)

MC9S08JM60 Series Data Sheet, Rev. 3

146 Freescale Semiconductor