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Interleaved power converter with current ripple cancelation at a selectable duty

cycle

Conference Paper · September 2011

DOI: 10.1109/ECCE.2011.6063758

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 Interleaved Power Converter with Current
Ripple Cancelation at a Selectable Duty Cycle
Julio C. Rosas-Caro, Jesus E. Valdez-Resendiz, Jonathan C. Mayo-Maldonado,
Ruben Salas-Cabrera, Juan M. Ramirez-Arredondo, Joel Salome-Baylon.

disadvantage of topology in Fig. 1(a) is that the duty cycle for

Abstract— This work proposes a topology for a boost converter zero input current-ripple can not be selected; it depends on the
with the capability of canceling the input current ripple at an number of switching stages.
arbitrarily selected duty cycle.
In the traditional interleaved boost converter the zero input
current-ripple feature depends on the number of interleaved
switching circuits. For example, two traditional interleaved
converters have a zero input current ripple if and only if the duty
cycle is 0.5.
Other advantages of this proposed topology are: (i) the perfect
ripple-cancelation duty-cycle can be selected without increasing
the component count, (ii) higher voltage gain compared to the
traditional interleaved boost converter; this feature is highly
desirable in renewable energy applications, (iii) the voltage gain
can be easily increased with a diode-capacitor voltage multiplier.
Experimental results and a theoretical analysis are presented
in this work.

Index Terms— DC-DC power converters, Power conversion,

Pulse width modulation converters, current ripple cancelation. Fig. 1. Converters with input current cancelation.

(ii) Several canceling circuits have been proposed in the

I. INTRODUCTION literature, for example the circuit in Fig. 1(b) was presented in
[1]; it is similar to the traditional interleaved converter,
I N a boost converter design, the input current-ripple is
required to be a small percentage of the input dc current. It
is well known that the current ripple is smaller as the input
however the output of the switching structures are connected in
series instead of being connected in parallel; there are two
inductor becomes larger. This is a constraint since increasing switching structures, one of them requires synchronous
the input inductor increases the size and cost of the converter. rectification as this switching structure drains a current with
Several solutions have been proposed for addressing this zero dc component; the main advantage is that the zero
drawback of the boost converter [1-6]. In addition, a large current-ripple duty cycle can be selected; the main
inductor also slows down the open loop transient response of disadvantage is that the component count increases but not the
the converter. A brief review of the literature follows. power rating of the converter.
(i) Interleaving or multi-phase converters, see Fig. 1(a), (iii) Other solution is the use of passive cancelation [2-3],
utilize several switching stages. They have several advantages see Fig. 1(c); this passive cancelation can be hybridized by
compared to the traditional boost converter such as smaller employing an active circuit to improve the current cancelation
input current-ripple with the same storage energy in inductors, [4]. Fig. 1(d) shows another circuit with passive cancelation
the input current-ripple is zero for a fixed duty cycle i.e. when [5-6]; inductors in Fig. 1(d) may be magnetically coupled and
there are two switching stages connected in parallel as shown then the circuit becomes similar to one depicted in Fig. 1(c).
in Fig. 1(a) the input current ripple is zero for a D=0.5. A This paper proposes a boost converter with input current-
ripple cancelation with advantages such as (i) the zero input
current-ripple can be achieved with a arbitrarily selected duty
This work was developed under the project “Investigación de topologias de cycle without increasing the component count, (ii) since the
electronica de potencia” registered in DGEST 2011.
Julio Cesar Rosas-Caro, Jesus Elias Valdez-Resendiz, Jonathan Carlos current canceling circuit drains dc current the power rating of
Mayo-Maldonado and Ruben Salas-Cabrera, are with the Madero City the converter increases, (iii) the boost factor is higher than
Technological Institute, Tamaulipas State, México (e-mail: those factors of the available configurations shown in Fig. 1
[email protected]).
Juan Manuel Ramirez-Arredondo and Joel Salome-Baylon are with the and this factor may be extended by utilizing voltage
Guadalajara Campus of CINVESTAV, México. multipliers.

978-1-4577-0541-0/11/$26.00 ©2011 IEEE 122

 An experimental prototype was build, experimental results the converter operates as the equivalent circuit shown in Fig.
are provided along with theoretical analysis. 2(b). During the time s1 is on, the diode d1 is reverse biased
with VC1. Similarly, diode d3 is reverse biased with VC3. And
II. PROPOSED TOPOLOGY then both diodes are open during this period of time. The
The proposed topology is shown in Fig. 2(a), it contains two current through inductor L2 allows the diode d2 to be closed
transistors, three diodes, two inductors and three capacitors. since transistor s2 is open.
Both transistors switch complementary, i.e. when s1 is closed, Fig. 2(d) shows both inductor currents, the total input
s2 is open and vice-versa. current and the switching sequence for s1 (the switching
The operation of the converter will be explained assuming sequence for s2 is complementary). During the time s1 is on,
the small ripple approximation [7] and the continuous the current through L1 is rising with a slope of Vin/L1 and L2 is
conduction mode. In this case a positive current and voltage discharging while C2 is charging.
(positive according with the sign defined in Fig. 2) are On the other hand, when s1 is off (and s2 is on) the resulting
assumed with a ripple that is considered to be small compared equivalent circuit is depicted in Fig. 2(c). During this time, the
to the magnitude of DC component. The circuit will be current in L1 discharges with a slope of (Vin-VC1)/L1; L2 is
introduced by employing several waveforms obtained from charging as a result of applying the input voltage and its
simulation and experimental tests. corresponding current rises with a slope of Vin/L2.
A key fact of the proposed converter can be derived from
observing Fig. 2(d) and considering the explanation mentioned
above. During each one of the switching states, one inductor is
charging while the other one is discharging. Since both
inductors can be calculated to have the same current ripple at
an arbitrarily selected duty cycle, then the cancelation of the
current ripple in the input voltage can be accomplished. As it
was established earlier this fact stands as an advantage
considering that in the traditional interleaved boost converter
the duty cycle for accomplishing zero input current-ripple
strongly depends on the number of switching stages.
Currents depicted in Fig. 2(d) are shown for a converter that
presents a zero input current-ripple at a duty cycle of D=0.7.

III. ANALYSIS AND SELECTION OF COMPONENTS

As it can be seen from Fig. 2, the proposed converter is an
interleaving converter between the boost converter [7] and a
three-switch high-voltage converter [8], the advantage of
interleaving circuits with this characteristics are that the
voltage gain is higher than interleaving circuits of the same
type, furthermore, the duty cycle of each converter may be
different, in this case the duty cycle of one is defined as the
complement of the other one and this is the trick of the current
ripple cancelation.
A. Voltage gain
In order to analyze the converter during steady state
conditions the small ripple approximation [7] will be assumed.
Considering the duty cycle d as the time when the switch s1 is
closed over the total switching period Ts, see Fig. 1(d), the
average voltages across the input inductors are given as
di L1
L = d (vin ) + (1 − d )(vin − vC1 ) (1)
dt
di
Fig. 2. (a) Proposed topology, (b)-(c) equivalent circuits for each switching L L 2 = d (vin − vC 2 ) + (1 − d )(vin ) (2)
state, (d) magnitude of the total input current, current waveforms through the dt
input inductors, and switching sequence.
In steady state, the average value of variables in (1) and (2)
The converter has two equivalent circuits corresponding to are constant, average voltages across the inductors should be
each one of the switching states. When s1 is on (and s2 is off) equal to zero. Under these conditions and using expressions

123
(1) and (2) the voltages across C1 and C2 may be expressed as B. Inductors and Input current ripple
1 From Fig. 2(d), it is evident that the current ripple of each
VC1 = Vin (3) one of the inductors is given by
1− D
1 Vin V D
VC 2 = Vin (4) ∆iL1 = DTS = in ⋅ (6)
D L1 L1 f S
It is important to note that capital letters indicate steady V V (1 − D)
∆i L 2 = in (1 − D)TS = in ⋅ (7)
state values. L2 L2 fS
C2 clamps the voltage in C3 during the time when the switch
s2 is on, see Fig. 2(c) ant then they get practically the same where f s denotes the switching frequency.
average voltage [8]. The load is connected to the voltage that The input current ripple, denoted by ∆in, is the difference
results of adding VC1+VC3. The voltage gain of the converter between the current ripple of the inductors defined by
can be written as: equations (6) and (7), thus

Vo (
= VC1 + VC 3
) = 1 (5) Vin  D (1 − D) 
Vin Vin D(1 − D) ∆iin =  −  (8)
f S  L1 L2 
The plot of the above voltage gain as a function of the duty
The converter can be designed for obtaining a zero input
cycle is shown in Fig. 3 (a).
current-ripple at a certain duty cycle. This duty cycle can be
calculated from the expected input and output voltages and
using expression given by (5). For the purpose of obtaining a
zero input current-ripple, expression (8) should be equal to
zero and assuming that the duty cycle is known, then the
following relationship between the inductors may be derived
D
L1 = L2 (9)
(1 − D)
For example, if the expected input and output voltages are
such that the duty cycle is equal to 0.75, then the value of L1
should be three times the value of L2 (according with (9)) for
accomplishing zero input current-ripple.
Once we have selected the duty cycle and calculated the
values of each inductor, we can use (8) for analyzing the input
current ripple through the full operation range. For example, if
L1=3L2 and employing expression (8), then the input current
ripple can be expressed as:

Vin  D (1 − D )  Vin  4 
∆iin =  − =  D − 1 (10)
f S  3L2 L2  f S L2  3 
It is clear that there is a linear dependence of current ripple
on the value of the duty cycle. This fact is shown in Fig. 3(b).
If the converter duty cycle is set to 0.6 (inductors are
calculated for having a zero ripple at D=0.75) then the current
ripple would be 0.2 times Vin/(fSL2). It is important to note that
this current ripple is given in amperes (not in percentage).
Finally and consistent with (3) and (4), the average current
Fig. 3. (a) voltage gain vs. duty cycle, (b) input current-ripple vs. duty cycle.
through the inductors can be defined as
According to Fig. 3 (a) and expression (5), the minimum 1
voltage gain is 4 and it is obtained when the duty cycle is equal I L1 = I o (11)
to 0.5. If the duty cycle is smaller than 0.5 the gain increases
1− D
1
again, therefore it is recommendable to employ duty cycles I L2 = Io (12)
higher than 0.5. D

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 C. Capacitors voltage. A diode-clamped multilevel converter can be
For calculating the adequate values of the capacitors we can connected as a load, as it is shown in Fig. 4(b). In Fig. 4(b) a
use a procedure similar to the one used for calculating branch of a five level inverter is connected as a load. Two
inductors. For example, during the time s1 is on, the load branches may be connected in the same way providing higher
current is passing through capacitor C1, then voltage with nine levels.

Io
∆ vC 1 = DTS (13)
C1
For calculating the value of the capacitor C2, the period of
time when s2 is open can be used, i.e.
I L2
∆ vC 2 = DTS (14)
C2
Capacitor C3 is charged by C2 when the switch S2 closes
connecting them in parallel, after this pretty fast dynamics, this
capacitor is always discharging with the load current, the load
current pass throw C3 in Fig. 2(b) and by C2 and C3 in Fig. 2(c)
A good approach which doesn’t depend on the capacitance
in C2 is to consider than the load current pass throw C3 all the
time, in this case the voltage-ripple would be given by (15),
the real voltage ripple in C3 is smaller than the one expressed
in (15).
Io
∆vC 3 = TS (15)
C3

IV. POSSIBLE APPLICATIONS AND VARIATIONS

The application of the proposed topology is mainly focused
on renewable energy sources, where the power source should
have a current-ripple as small as possible.
This converter is able to provide a wide voltage gain (as it
is shown in Fig. 3(a)) and a small current ripple for solar cell
or fuel cells (as it is shown in Fig. 3(b)). Fig. 4. (a) voltage multiplier extension (b) balancing mode.
A possible variation of the topology is to extend it by
utilizing voltage multipliers. Hybridizing dc-dc converters with V. EXPERIMENTAL RESULTS
voltage multipliers has been previously proposed in the A prototype was developed to obtain some experimental
literature [9]. It provides higher voltage gain to the traditional results. The schematic of the implemented converter is the
boost converter and to the three-switch high-voltage converter. same as the one presented in Fig. 2(a). A picture of the
Since the boost converter processes most of the power, the prototype is shown in Fig. 5.
three-switch high-voltage converter can be seen as a current
cancelation circuit,
A. High voltage gain zero ripple converter
The proposed converter can be extended to a multiplier
boost converter [9] as it is shown in Fig. 4(a). An advantage of
this topology is that helps to reduce the size of the input
inductor and its corresponding series resistance.
B. Balancing mode
The converter is designed to have both switches operating in
a complementary way. However, they can also operate with
the same duty cycle in a truly interleaving manner. In this
Fig. 5. Implemented Prototype.
particular case, both output capacitors would obtain the same
The variables and parameters of the prototype during the
voltage. Furthermore, if the design is extended with voltage
experimental tests are: Vin=20V, L1=360µH, L2=120µH,
multipliers, all the output capacitors would have a balanced
125
 C1=33µF, C2=47µF, C3=10µF, Rout=100Ω, D=0.75 and VI. CONCLUSIONS
fs=50kHz. The real voltage gain was tested in several points, This paper proposes a boost converter with input current-
they are shown in Fig. 6(a) ripple cancelation with advantages such as: (i) the zero input
current-ripple can be achieved with an arbitrarily selected duty
cycle. (ii) the current canceling circuit drains dc current,
therefore it contributes to increase the power rating of the
converter. (iii) the boost factor is higher than the available
configurations shown in Fig. 1; this boost factor may be
extended by utilizing diode-capacitor multipliers. Those
features are highly desirable in fuel cell applications.
Experimental results are provided along with a theoretical
analysis. Future work will be done in the research of this
topology.

REFERENCES
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(c)
Fig. 6. (a) Experimental voltage gain (b) traces of both inductor currents 2
A/div (c) trace of the total input current 4 A/div.

Current were measured with sensing resistors, Fig. 6(b)

shows the experimental traces of the input current and each
one of the currents flowing through the inductors with 2 A/div.
Fig. 6(c) shows the total input current with 4 A/div .
126

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