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Lecture 6.1

This document discusses modeling circuits with regular structure in VHDL. It provides examples of modeling a parity checker circuit, multiplexers, and decoders using for generate statements and hierarchical design. The parity checker is modeled by breaking it into stages of XOR gates. Multiplexers are modeled by combining smaller multiplexers. Decoders are modeled similarly by combining smaller decoder components. Using for generate statements and hierarchical design allows modeling larger regular structures concisely.

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Charly Alvarez Heredia
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Download as XLSX, PDF, TXT or read online on Scribd
33 views128 pages

Lecture 6.1

This document discusses modeling circuits with regular structure in VHDL. It provides examples of modeling a parity checker circuit, multiplexers, and decoders using for generate statements and hierarchical design. The parity checker is modeled by breaking it into stages of XOR gates. Multiplexers are modeled by combining smaller multiplexers. Decoders are modeled similarly by combining smaller decoder components. Using for generate statements and hierarchical design allows modeling larger regular structures concisely.

Uploaded by

Charly Alvarez Heredia
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as XLSX, PDF, TXT or read online on Scribd
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Lecture 6

Modeling of Circuits with


Regular Structure
of Circuits with
tructure
Example 1
2
Example 1: Block Diagram
3
Example 1: Block Diagram
PARITY: Entity Declaration
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY parity IS
PORT(
parity_in : IN STD_LOGIC_VECTOR(7 DOWNT
parity_out : OUT STD_LOGIC
);
END parity;
4
Declaration

STD_LOGIC_VECTOR(7 DOWNTO 0);


T STD_LOGIC
PARITY: Block Diagram
xor_out(1)
xor_out(2)
xor_out(3) xor_out(4)

xor_out(5) xor_out(6)

5
Y: Block Diagram
PARITY: Architecture (1)
ARCHITECTURE parity_dataflow OF parity IS
SIGNAL xor_out: std_logic_vector (6 downto 1);
BEGIN
xor_out(1) <= parity_in(0) XOR parity_in(1);
xor_out(2) <= xor_out(1) XOR parity_in(2); xor_out(3
END parity_dataflow;
6
ARITY: Architecture (1)
CHITECTURE parity_dataflow OF parity IS
NAL xor_out: std_logic_vector (6 downto 1);

xor_out(1) <= parity_in(0) XOR parity_in(1);


xor_out(2) <= xor_out(1) XOR parity_in(2); xor_out(3) <= xor_o
D parity_dataflow;
_out(3) <= xor_out(2) XOR parity_in(3); xor_out(4) <= xor_out(3) X
or_out(3) XOR parity_in(4); xor_out(5) <= xor_out(4) XOR parity_i
4) XOR parity_in(5); xor_out(6) <= xor_out(5) XOR parity_in(6); pa
parity_in(6); parity_out <= xor_out(6) XOR parity_in(7);
PARITY: Architecture (2)
ARCHITECTURE parity_dataflow OF parity IS
SIGNAL xor_out: STD_LOGIC_VECTOR (6 DOWNTO 1);
BEGIN
xor_out(1) <= parity_in(0) XOR parity_in(1);
G1: FOR i IN 2 TO 6 GENERATE
xor_out(i) <= xor_out(i-1) XOR parity_in(i); END GENE
parity_out <= xor_out(6) XOR parity_in(7);
END parity_dataflow;
7
WNTO 1);

i); END GENERATE;


PARITY: Block Diagram (2)
xor_out(0)
xor_out(1)
xor_out(2)
xor_out(3) xor_out(4)

xor_out(5) xor_out(6)

xor_out(7)
8
Y: Block Diagram (2)
PARITY: Architecture
ARCHITECTURE parity_dataflow OF parity IS
SIGNAL xor_out: STD_LOGIC_VECTOR (7 downto 0);
BEGIN
xor_out(0) <= parity_in(0);
xor_out(1) <= xor_out(0) XOR parity_in(1); xor_out(2) <= xor_out(1
END parity_dataflow;
9
nto 0);

(2) <= xor_out(1) XOR parity_in(2); xor_out(3) <= xor_out(2) XOR parity_i
ut(2) XOR parity_in(3); xor_out(4) <= xor_out(3) XOR parity_in(4); xor_ou
arity_in(4); xor_out(5) <= xor_out(4) XOR parity_in(5); xor_out(6) <= xor_o
r_out(6) <= xor_out(5) XOR parity_in(6); xor_out(7) <= xor_out(6) XOR pa
or_out(6) XOR parity_in(7); parity_out <= xor_out(7);
PARITY: Architecture (2)
ARCHITECTURE parity_dataflow OF parity IS
SIGNAL xor_out: STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
xor_out(0) <= parity_in(0);
G2: FOR i IN 1 TO 7 GENERATE
xor_out(i) <= xor_out(i-1) XOR parity_in(i); END GEN
parity_out <= xor_out(7);
END parity_dataflow;
10
hitecture (2)
ataflow OF parity IS
GIC_VECTOR (7 DOWNTO 0);

ERATE
out(i-1) XOR parity_in(i); END GENERATE;
For Generate Statement
For - Generate
ate Statement
label:
FOR identifier IN range GENERATE
{VHDL code}
END GENERATE;
11
Example 2
12
Example 2
s0
s1
w0
w3
w4 s
2

s3
w7
f
w8
w
11
w
12
w
15

13
A 4-to-1 Multiplexer
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY mux4to1 IS
PORT ( w0, w1, w2, w3
sf : IN
: OUT
END mux4to1 ;
: IN STD_LOGIC ;
STD_LOGIC_VECTOR(1 DOWNTO 0) ;
STD_LOGIC ) ;
ARCHITECTURE Dataflow OF mux4to1 IS
BEGIN
WITH s SELECT
f <= w0 WHEN "00", w1 WHEN "01",
w2 WHEN "10",
w3 WHEN OTHERS ;
END Dataflow ;
14
Straightforward code for Examp
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY mux16to1 IS
PORT ( w : IN STD_LOGIC_VECTOR(0 TO 15) ;
s : IN STD_LOGIC_VECTOR(3 DOWNT
END mux16to1 ;
15
rd code for Example 2

TD_LOGIC_VECTOR(0 TO 15) ;
N STD_LOGIC_VECTOR(3 DOWNTO 0) ; f : OUT STD_LOGIC ) ;
TD_LOGIC ) ;
Straightforward code for Examp
ARCHITECTURE Structure OF mux16to1 IS
COMPONENT mux4to1
PORT ( w0, w1, w2, w3 : IN STD_LOGIC ;
s : IN STD_LOGIC_VECTO
f : OUT STD_LOGIC ) ; END COMPONENT ;
SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ;
BEGIN
Mux1: mux4to1 PORT MAP ( w(0), w(1), w(2), w(3), s(1 DOWNTO 0),
Mux2: mux4to1 PORT MAP ( w(4), w(5), w(6), w(7), s(1 DOWNTO 0),
Mux3: mux4to1 PORT MAP ( w(8), w(9), w(10), w(11), s(1 DOWNTO 0),
Mux4: mux4to1 PORT MAP ( w(12), w(13), w(14), w(15), s(1 DOWNTO 0),
Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2)
END Structure ;
16
de for Example 2
STD_LOGIC ;
: IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
END COMPONENT ;

w(2), w(3), s(1 DOWNTO 0), m(0) ) ;


w(6), w(7), s(1 DOWNTO 0), m(1) ) ;
w(10), w(11), s(1 DOWNTO 0), m(2) ) ;
w(14), w(15), s(1 DOWNTO 0), m(3) ) ;
m(2), m(3), s(3 DOWNTO 2), f ) ;
Modified code for Example 2
ARCHITECTURE Structure OF mux16to1 IS
COMPONENT mux4to1
PORT ( w0, w1, w2, w3 : IN STD_LOGIC ;
s : IN STD_LOGIC_VECTOR(1 D
f : OUT STD_LOGIC ) ; END COMPONENT ;
SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ;
BEGIN
G1: FOR i IN 0 TO 3 GENERATE
Muxes: mux4to1 PORT MAP (
w(…….), w(……..), w(……..), w(……...), s(………..), m(……….) ) ; END GENERATE
Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ;
END Structure ;
17
Example 2
STD_LOGIC ;
STD_LOGIC_VECTOR(1 DOWNTO 0) ;
END COMPONENT ;

…..), m(……….) ) ; END GENERATE ;


(3), s(3 DOWNTO 2), f ) ;
Modified code for Example 2
ARCHITECTURE Structure OF mux16to1 IS
COMPONENT mux4to1
PORT ( w0, w1, w2, w3 : IN STD_LOGIC ;
s : IN STD_LOGIC_VECTOR(1 D
f : OUT STD_LOGIC ) ; END COMPONENT ;
SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ;
BEGIN
G1: FOR i IN 0 TO 3 GENERATE
Muxes: mux4to1 PORT MAP (
w(4*i), w(4*i+1), w(4*i+2), w(4*i+3), s(1 DOWNTO 0), m(i) ) ; END GENERATE ;
Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ;
END Structure ;
18
Example 2
STD_LOGIC ;
STD_LOGIC_VECTOR(1 DOWNTO 0) ;
END COMPONENT ;

O 0), m(i) ) ; END GENERATE ;


(3), s(3 DOWNTO 2), f ) ;
Example 3
19
Example 3
w1 y3
w0 y2 y1
En y0

w1 y3
w0 y2 y1
En y
0
w1 y3
w0 y2 y1 w y
1 3
En y0
w0 y2 y1
En y0

w1 y3
w0 y2 y1
En y0
w y
1 15
w y
0 14

w3 y8

w2
En y7

y3
y2 y1 y0
20
y
13 y12
y
11 y10 y9

y6 y5 y4
A 2-to-4 binary decoder
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY dec2to4 IS
PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En
y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
END dec2to4 ;
ARCHITECTURE Dataflow OF dec2to4 IS
SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ; BEGIN
Enw <= En & w ;
WITH Enw SELECT
y <= "0001" WHEN "100",
"0010" WHEN "101",
"0100" WHEN "110",
“1000" WHEN "111", "0000" WHEN OTHERS ;
END Dataflow ;
21
ary decoder

STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ;


: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;

F dec2to4 IS
VECTOR(2 DOWNTO 0) ; BEGIN

01" WHEN "100",


"0010" WHEN "101",
"0100" WHEN "110",
“1000" WHEN "111", "0000" WHEN OTHERS ;
_LOGIC ;
VHDL code for Example 3 (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY dec4to16 IS
PORT (w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; E
y : OUT STD_LOGIC_VECTOR(15 DOWNT
END dec4to16 ;
22
r Example 3 (1)

TD_LOGIC_VECTOR(3 DOWNTO 0) ; En : IN STD_LOGIC ;


T STD_LOGIC_VECTOR(15 DOWNTO 0) ) ;
VHDL code for Example 3 (2)
ARCHITECTURE Structure OF dec4to16 IS
COMPONENT dec2to4
PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0
y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END COMPONE
SIGNAL m : STD_LOGIC_VECTOR(3 DOWNTO 0) ;
BEGIN
Dec_r0: dec2to4 PORT MAP ( w(1 DOWNTO 0), m(0), y(3 DOWNTO 0)
Dec_left: dec2to4 PORT MAP ( w(3 DOWNTO 2), En, m ) ; END Structure ;
23
e 3 (2)

CTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ;


) ; END COMPONENT ;

y(3 DOWNTO 0) ); Dec_r1: dec2to4 PORT MAP ( w(1 DOWNTO 0), m(1), y(7 DOWN
END Structure ;
m(1), y(7 DOWNTO 4) ); Dec_r2: dec2to4 PORT MAP ( w(1 DOWNTO 0), m(2), y(11
WNTO 0), m(2), y(11 DOWNTO 8) ); Dec_r3: dec2to4 PORT MAP ( w(1 DOWNTO 0), m
( w(1 DOWNTO 0), m(3), y(15 DOWNTO 12) );
VHDL code for Example 2 (2)
ARCHITECTURE Structure OF dec4to16 IS
COMPONENT dec2to4
PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0
y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END COMPONE
SIGNAL m : STD_LOGIC_VECTOR(3 DOWNTO 0) ;
BEGIN
G1: FOR i IN 0 TO 3 GENERATE
Dec_ri: dec2to4 PORT MAP ( w(…………), m(……), y(……………………
Dec_left: dec2to4 PORT MAP ( w(3 DOWNTO 2), En, m ) ; END Structure ;
24
e 2 (2)

CTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ;


) ; END COMPONENT ;

y(……………………..) ); END GENERATE ;


END Structure ;
VHDL code for Example 2 (2)
ARCHITECTURE Structure OF dec4to16 IS
COMPONENT dec2to4
PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0
y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END COMPONE
SIGNAL m : STD_LOGIC_VECTOR(3 DOWNTO 0) ;
BEGIN
G1: FOR i IN 0 TO 3 GENERATE
Dec_ri: dec2to4 PORT MAP ( w(1 DOWNTO 0), m(i), y(4*i+3 DOWNTO
Dec_left: dec2to4 PORT MAP ( w(3 DOWNTO 2), En, m ) ; END Structure ;
25
e 2 (2)

CTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ;


) ; END COMPONENT ;

, y(4*i+3 DOWNTO 4*i) ); END GENERATE ;


END Structure ;
Example 4
Up-or-down Free Running Co
26
Example 4
Up-or-down Free Running Cou
Up-or-down Free Running Counter
27
Up-or-down Free Running Counter
Up-or-down Free Running Counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity up_or_down_counter is
generic(
WIDTH: natural:=4;
UP: natural:=0
);
port(
clk, reset: in std_logic;
q: out std_logic_vector(WIDTH-1 downto 0)
);
end up_or_down_counter;
28
unning Counter (1)

H-1 downto 0)
Up-or-down Free Running Counter
architecture mixed of up_or_down_counter is
signal r_reg: unsigned(WIDTH-1 downto 0);
signal r_next: unsigned(WIDTH-1 downto 0);
begin
-- register process(clk,reset) begin
if (reset='1') then
r_reg <= (others=>'0');
elsif (clk'event and clk='1') then r_reg <= r_next;
end if;
end process;
29
ng Counter (2)
nter is
to 0);
nto 0);

_reg <= r_next;


Up-or-down Free Running Counter
-- next-state logic
inc_gen: -- incrementor
if UP=1 generate
r_next <= r_reg + 1;
end generate;
dec_gen: --decrementor
if UP/=1 generate
r_next <= r_reg – 1;
end generate;
-- output logic
q <= std_logic_vector(r_reg);
end mixed;
30
unning Counter (3)
Conditional Generate Statement
If - Generate
nal Generate Statement
label:
IF boolean_expression GENERATE
{VHDL code}
END GENERATE;
31
Example 5
Up-and-down Free Running C
32
Example 5
Up-and-down Free Running Co
Up-and-down Free Running Counte
33
Up-and-down Free Running Counter
Up-and-down Free Running Counte
library ieee;
use ieee.std_logic_1164.all; use ieee.numeric_std.all;
entity up_and_down_counter is
generic(WIDTH: natural:=4); port(
clk, reset: in std_logic;
mode: in std_logic;
q: out std_logic_vector(WIDTH-1 downto 0)
);
end up_and_down_counter;
34
e Running Counter (1)
se ieee.numeric_std.all;

; port(

WIDTH-1 downto 0)
Up-and-down Free Running Counte
architecture arch of up_and_down_counter is
signal r_reg: unsigned(WIDTH-1 downto 0);
signal r_next: unsigned(WIDTH-1 downto 0);
begin
-- register process(clk,reset) begin
if (reset='1') then
r_reg <= (others=>'0');
elsif (clk'event and clk='1') then r_reg <= r_next;
end if;
end process;
35
ning Counter (2)
nter is

_reg <= r_next;


Up-and-down Free Running Counte
-- next-state logic
r_next <= r_reg + 1 when mode='1' else
r_reg - 1;
-- output logic
q <= std_logic_vector(r_reg);
end arch;
36
Running Counter (3)
de='1' else
Example 6
Variable Rotator
37
Example 3: Variable rotator - Interface
A
16
Example 3: Variable rotator - Interface
A <<< B
4
B
16

C
38
Block diagram
39
VHDL code for a 16-bit
2-to-1 Multiplexer
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY mux2to1_16 IS
PORT ( w0 : IN STD_LOGIC_VECTOR(15 DO
f : OUT STD_LOGIC_VECTOR
END mux2to1_16 ;
ARCHITECTURE dataflow OF mux2to1_16 IS
BEGIN
f <= w0 WHEN s = '0' ELSE w1 ;
END dataflow ;
40
IC_VECTOR(15 DOWNTO 0); w1 : IN STD_LOGIC_VECTOR(1
D_LOGIC_VECTOR(15 DOWNTO 0) ) ;
OGIC_VECTOR(15 DOWNTO 0); s : IN STD_LOGIC ;
D_LOGIC ;
Fixed rotation
a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a
<<< 3
a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(15) a(
y <= a(……………..) & a(………………);
a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2)
<<< 5
a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(15) a(14) a(13) a
y <= a(……………..) & a(………………);
41
a(5) a(4) a(3) a(2) a(1) a(0)

a(2) a(1) a(0) a(15) a(14) a(13)

a(5) a(4) a(3) a(2) a(1) a(0)

a(0) a(15) a(14) a(13) a(12) a(11)


Fixed rotation
a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a
<<< 3
a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(15) a(
y <= a(12 downto 0) & a(15 downto 13);
a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2)
<<< 5
a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(15) a(14) a(13) a
y <= a(10 downto 0) & a(15 downto 11);
42
5) a(4) a(3) a(2) a(1) a(0)

2) a(1) a(0) a(15) a(14) a(13)

5) a(4) a(3) a(2) a(1) a(0)

0) a(15) a(14) a(13) a(12) a(11)


Fixed rotation by L positions
a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3
<<< L
a(……) a(……...) . . . . . . . . . . . . . . a(1) a(0) a(15) a(14) . . . . . . . a(……
y <= a(………………..) & a(…………………..);
43
Fixed rotation by L positions
a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a
<<< L
a(……) a(……...) . . . . . . . . . . . . . . a(1) a(0) a(15) a(14) . . . . . . . a(………
y <= a(………………..) & a(…………………..);
4) a(3) a(2) a(1) a(0)

a(……….) a(……….)
Fixed rotation by L positions
a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3
<<< L
a(15-L) a(15-L-1) . . . . . . . . . . . . . . a(1) a(0) a(15) a(14) . . . . . . . a(15
y <= a(15-L downto 0) & a(15 downto 15-L+1);
44
Fixed rotation by L positions
a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a
<<< L
a(15-L) a(15-L-1) . . . . . . . . . . . . . . a(1) a(0) a(15) a(14) . . . . . . . a(15-L
y <= a(15-L downto 0) & a(15 downto 15-L+1);
4) a(3) a(2) a(1) a(0)

. a(15-L+2) a(15-L+1)
VHDL code for
for a fixed 16-bit rotator
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY fixed_rotator_left_16 IS
GENERIC ( L : INTEGER := 1);
PORT ( a : IN STD_LOGIC_VECTOR(15 DO
y : OUT STD_LOGIC_VECTOR
END fixed_rotator_left_16 ;
ARCHITECTURE dataflow OF fixed_rotator_left_16 IS
BEGIN
y <= a(15-L downto 0) & a(15 downto 15-L+1);
END dataflow ;
45
C_VECTOR(15 DOWNTO 0);
_LOGIC_VECTOR(15 DOWNTO 0) ) ;
Structural VHDL code for
for a variable 16-bit rotator (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY variable_rotator_16 is
PORT(
A : IN STD_LOGIC_VECTOR(15 downto 0);
B : IN STD_LOGIC_VECTOR(3 downto 0);
C : OUT STD_LOGIC_VECTOR(15 downto 0)
);
END variable_rotator_16;
ARCHITECTURE structural OF variable_rotator_16 IS
TYPE array16 IS ARRAY (0 to 4) OF STD_LOGIC_VECTOR(15 DOWNTO
SIGNAL Al : array16; SIGNAL Ar : array16;
46
(15 DOWNTO 0);
Block diagram
47
BEGIN

Structural VHDL code for


for a variable 16-bit rotator (2)
Al(0) <= A;
G:
FOR i IN 0 TO 3 GENERATE
ROT_I: ENTITY work.fixed_rotator_left_16(dataflow) GENERIC MA
PORT MAP ( a => ……….. ,
y => ………..);
MUX_I: ENTITY work.mux2to1_16(dataflow) PORT MAP (w0 => …
w1 => ………….., s => …………
f => ……………);
END GENERATE;
C <= Al(4);
END structural;
48
ral VHDL code for
riable 16-bit rotator (2)

GENERATE
ENTITY work.fixed_rotator_left_16(dataflow) GENERIC MAP (L => ………)
PORT MAP ( a => ……….. ,
y => ………..);
ENTITY work.mux2to1_16(dataflow) PORT MAP (w0 => …………..,
w1 => ………….., s => …………..,
f => ……………);
=> ………)
BEGIN

Structural VHDL code for


for a variable 16-bit rotator (2)
Al(0) <= A;
G:
FOR i IN 0 TO 3 GENERATE
ROT_I: ENTITY work.fixed_rotator_left_16(dataflow) GENERIC MA
PORT MAP ( a => Al(i) ,
y => Ar(i));
MUX_I: ENTITY work.mux2to1_16(dataflow) PORT MAP (w0 => A
w1 => Ar(i), s => B(i),
f => Al(i+1));
END GENERATE;
C <= Al(4);
END structural;
49
ral VHDL code for
riable 16-bit rotator (2)

GENERATE
ENTITY work.fixed_rotator_left_16(dataflow) GENERIC MAP (L => 2** i)
PORT MAP ( a => Al(i) ,
y => Ar(i));
ENTITY work.mux2to1_16(dataflow) PORT MAP (w0 => Al(i),
w1 => Ar(i), s => B(i),
f => Al(i+1));
=> 2** i)
Block diagram
50
Dataflow VHDL code for
for a variable 16-bit rotator (3)
BEGIN
Al(0) <= A;
G:
FOR i IN 0 TO 3 GENERATE
Ar(i) <= ……………………………………………………….; Al(i+1)
END GENERATE;
C <= Al(4);
END dataflow;
51
ow VHDL code for
variable 16-bit rotator (3)
) <= A;

O 3 GENERATE
<= ……………………………………………………….; Al(i+1) <= …………………
…………………………………………………….;
Dataflow VHDL code for
for a variable 16-bit rotator (3)
BEGIN
Al(0) <= A;
G:
FOR i IN 0 TO 3 GENERATE
Ar(i) <= Al(i)(15-2**i downto 0) & Al(i)(15 downto 15-2**i+1); Al(i
END GENERATE;
C <= Al(4);
END dataflow;
52
ow VHDL code for
variable 16-bit rotator (3)
) <= A;

O 3 GENERATE
<= Al(i)(15-2**i downto 0) & Al(i)(15 downto 15-2**i+1); Al(i+1) <= Al(i) when B
<= Al(i) when B(i)=‘0’ else Ar(i);

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