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0-9 Decoder Display

The document describes a 0-9 decoder display circuit with 7 outputs (a-g). It includes: 1) A truth table that defines the inputs (W,X,Y,Z) and corresponding outputs. 2) Unsimplified and simplified equations for each output using K-maps. 3) A logic circuit diagram that represents the overall circuit.

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Razel Kaye Mahinay
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52 views9 pages

0-9 Decoder Display

The document describes a 0-9 decoder display circuit with 7 outputs (a-g). It includes: 1) A truth table that defines the inputs (W,X,Y,Z) and corresponding outputs. 2) Unsimplified and simplified equations for each output using K-maps. 3) A logic circuit diagram that represents the overall circuit.

Uploaded by

Razel Kaye Mahinay
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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0-9 Decoder Display

I. Truth Table

INPUTS OUTPUTS

W X Y Z a b c d e f g

0 0 0 0 1 1 1 1 1 1 0

0 0 0 1 0 1 1 0 0 0 0

0 0 1 0 1 1 0 1 1 0 1

0 0 1 1 1 1 1 1 0 0 1

0 1 0 0 0 1 1 0 0 1 1

0 1 0 1 1 0 1 1 0 1 1

0 1 1 0 1 0 1 1 1 1 1

0 1 1 1 1 1 1 0 0 1 0

1 0 0 0 1 1 1 1 1 1 1

1 0 0 1 1 1 1 0 0 1 1

II. Unsimplified Equation

A = w’x’y’z’ + wx’yz’ + w’x’yz + w’xy’z + w’xyz’ + w’xyz + wx’y’z’ + wx’y’z

B = w’x’y’z’ + w’x’y’z + w’x’yz’ + w’x’yz + w’xy’z’ + w’xyz + wx’y’z’ + wx’y’z

C = w’x’y’z’ + w’x’y’z + w’x’yz + w’xy’z’ + w’xy’z + w’xyz + w’xyz + wx’y’z’ + wx’y’z

D = w’x’y’z’ + w’x’yz’ + w’x’yz + w’xy’z + w’xyz’ + wx’y’z’ + wx’y’z

E = w’x’y’z’ + w’x’yz’ + w’xyz’ + wz’y’z’


F = w’x’y’z’ + w’xy’z’ + w’xy’z + w’xyz’ + w’xyz + wx’y’z’ + wx’y’z

G = w’x’yz’ + w’x’yz + w’xy’z’ + w’xy’z + w’xyz’ + wx’y’z’ + wx’y’z

III. Simplified Equations Using K-map

For equation A: For equation B:

YZ YZ

WX 00 01 11 10 WX 00 01 11 10

00 1 1 1 00 1 1 1 1

01 1 1 1 01 1 1

11 11

10 1 1 10 1 1

A = w + y + x’z’ + xz B = x’ + y’z’ + yz

For equation C: For equation D:

YZ YZ

WX 00 01 11 10 WX 00 01 11 10

00 1 1 1 00 1 1 1

01 1 1 1 1 01 1 1

11 11

10 1 1 10 1 1

C = y’ + x + z = y’ + (x’z’)’ D = w + x’z’ + xy’z + (xz)’y


For equation E: For equation F:

YZ YZ

WX 00 01 11 10 WX 00 01 11 10

00 1 1 00 1

01 1 01 1 1 1 1

11 11

10 1 10 1 1

E = z’ (x’y’) = x’z’ + yz’ F = y’z’ + x + w

For equation G:

YZ

WX 00 01 11 10

00 1 1

01 1 1 1

11

10 1 1

G = (xz)’y + xy’ + w
IV. Logic Circuit Diagram

Whole Logic Circuit Diagram

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