MICROPROCESSOR &

INTERFACING
EE-243 | Spring 2017

Intel Architecture

Lecture # 03 Dr. Rehan Hafiz | Associate Professor,

ITU Lahore, Pakistan
Difference b/w Micro-Processor & Micro-Controller
(INTEL 8086 vs INTEL 8051)

Intel’s Architectural Timeline

8086 Registers (General Purpose & Special)

Real Mode Addressing

Declaring Variables (Integers, Chars, Strings, Arrays)

MOV Instruction & Addressing Modes
Suggested Reading

 {KI}
 Chapter-2
Difference b/w Micro-Processor & Micro-Controller
https://image.slidesharecdn.com/ppt-140710020843-phpapp02/95/microcontroller-
vs-microprocessor-7-638.jpg?cb=1404958204
Intel Architecture
Timeline 
 1947: The transistor is invented at Bell Labs (& also Pakistan )
 1965: Moore’s Law : Number of transistors on a semiconductor chip
doubles every year
 1969-70: Intel launched SRAM <used for Caches> & DRAM <memory>
 1971: 4 bit Intel 4004  World’s first digital processor
 1972: 8 bit Intel 8008
 1975: First PC (Altair 8080)
 1978: 16 bit 8086 (Used in IBM PCs 1982) – The origin of INTEL’s x86 ISA
 1982: 16 bit 80286
 1985: 32 bit 80386 (Ability to run multiple programs) – (IA-32)
 1986: 32 bit 80486 (Built in Math co-processor)
 1993: P5 : 32 bit Pentium (Code/Data Caches, MMX)
 1995: P6 : Pentium II’s & Pentium Pro (Out of Order Execution)
 2000: NetBurst (Pentium 4)
 2006: Intel Core (Launch of x86-64), Example: Intel Core 2 Duo etc
 2008: Nehalm Archiature (Core, i3, i5, i7)
 https://en.wikipedia.org/wiki/List_of_Intel_CPU_microarchitectures

Year Microarchitecture Pipeline stages max. Clock

1989 486 (80486) 3 100 MHz
1993 P5 (Pentium) 5 300 MHz
14 (17 with load &
1995 P6 (Pentium II) 450 MHz
store/retire)
12 (15 with load &
1999 P6 (Pentium III) 450~1400 MHz
store/retire)
2000 NetBurst (Pentium 4) 20 800~3000 MHz

2003 Pentium M 10 (12 with fetch/retire) 400~1000 MHz

2004 Prescott 31 3800 MHz
2006 Intel Core 12 (14 with fetch/retire) 3000 MHz
2008 Nehalem 20 3000 MHz
16 (20 with prediction
2008 Bonnell 2100 MHz
miss)
2011 Sandy Bridge 14 (16 with fetch/retire) 3600 MHz

2013 Haswell 14 (16 with fetch/retire) ≈4000 MHz

2015 Skylake 14 (16 with fetch/retire) ≈4000 MHz

Intel Microprocessor History

 Intel 8086, 80286

 IA-32 processor family
 P6 processor family
 Core Architecture

Irvine, Kip R. Assembly

9 Language for Intel-Based
Computers 5/e, 2007.
Early Intel Microprocessors
 Intel 8088
 64K addressable RAM

 8-bit registers / data bus

 IBM-PC Used 8088

 Intel 8086
 1 MB addressable RAM

 16-bit registers / data bus

 separate floating-point unit (8087)

 Segmented Memory Model

Irvine, Kip R. Assembly

10 Language for Intel-Based
Computers 5/e, 2007.
 The IBM-AT

 Intel 80286
 16 MB addressable RAM
 Protected memory
 several times faster than 8086
 introduced IDE bus architecture
 80287 floating point unit

 Memory protection
 a way to control memory usage on a computer, and
is core to virtually every modern operating system.
 prevents a process running on an operating system
from accessing memory beyond that allocated to it.
Irvine, Kip R. Assembly
Language for Intel-Based
Computers 5/e, 2007.
Intel IA-32 Family

 Intel386
4GB addressable RAM, 32-bit registers,
paging (virtual memory)
 Intel486
 instruction pipelining
 Pentium
 superscalar, (multiple execution
pipelines) 32-bit address bus, 64-bit
internal data path

Irvine, Kip R. Assembly

12 Language for Intel-Based
Computers 5/e, 2007.
A superscalar processor can
execute more than one instruction
during a clock cycle by
simultaneously dispatching multiple
instructions to different execution
units on the processor. Each
execution unit is not a separate
processor (or a core if the processor
is a multi-core processor), but an
execution resource within a single
CPU such as an arithmetic logic
unit.<Wikipedia>

Simple superscalar pipeline. By fetching

and dispatching two instructions at a time,
a maximum of two instructions per cycle
can be completed. (IF = Instruction Fetch,
ID = Instruction Decode, EX = Execute,
MEM = Memory access, WB = Register
write back, i = Instruction number, t = Clock
Requires multiple arithmetic units. cycle [i.e., time])
Intel P6 Family

 Pentium Pro
 advanced optimization techniques in microcode
 Pentium II
 MMX (multimedia) instruction set
 Pentium III
 SIMD (Internet streaming extensions) instructions
 Pentium 4 and Xeon
 Intel NetBurst micro-architecture, tuned for
multimedia

Irvine, Kip R. Assembly

14 Language for Intel-Based
Computers 5/e, 2007.
IA-32 Addressable Memory

 Protected mode
4 GB
 32-bit address

Irvine, Kip R. Assembly

15 Language for Intel-Based
Computers 5/e, 2007.
 data bus

registers

I/O I/O
Central Processor Unit Memory Storage
Device Device
(CPU) Unit
#1 #2

ALU CU clock

control bus

address bus
 IA-32
IA-32 (short for "Intel Architecture, 32-bit", sometimes also called i386[1][2])[3] is the 32-
bit version of the x86 instruction set architecture (ISA), first implemented in the Intel
80386 microprocessors in 1985. IA-32 is the first incarnation of x86 that supports 32-bit
computing;[4] as a result, the "IA-32" term may be used as a metonym to refer to all x86 versions
that support 32-bit computing.[5][6]
The IA-32 instruction set was introduced in the Intel 80386 microprocessor in 1985 and, as of
2015, remains supported by contemporary PC microprocessors. Even though the instruction set
has remained intact, the successive generations of microprocessors that run it have become
much faster. Within various programming language directives, IA-32 is still sometimes referred to
as the "i386" architecture.
Intel is the inventor and the biggest supplier of IA-32 processors, and the second biggest supplier
is AMD. For a while, VIA, Transmeta and others also produced IA-32 processors, but since the
2000s all manufacturers moved to the 64-bit variant of x86, x86-64. <Wikipedia>

https://software.intel.com/en-us/articles/ia-32-intelr-64-ia-64-architecture-mean
General-Purpose Registers

32-bit General-Purpose Registers

EAX EBP
EBX ESP
ECX ESI
EDX EDI

16-bit Segment Registers

EFLAGS CS ES
SS FS
EIP
DS GS

Irvine, Kip R. Assembly

18 Language for Intel-Based
Computers 5/e, 2007.
 Some Specialized Register Uses (1 of 2)

 General-Purpose
 EAX – accumulator, also used by mul & div
 ECX – loop counter
 ESP – stack pointer (never to be used for ordinary arithmetic or data transfer)
 ESI, EDI – index registers (Source/Destination indexes; memory operations)
 EBP – extended frame pointer (stack)
 Segment
 CS – code segment
 DS – data segment
 SS – stack segment
 ES, FS, GS - additional segments
Irvine, Kip R. Assembly
19 Language for Intel-Based
Computers 5/e, 2007.
Book: The Intel Microprocessors [Barry B. Brey]
Some Specialized Register Uses (2 of 2)

 EIP – instruction pointer (Program Counter)

 EFLAGS
 status and control flags
 each flag is a single binary bit

Irvine, Kip R. Assembly

21 Language for Intel-Based
Computers 5/e, 2007.
 Status Flags – (EFLAGS - Register)

 Carry
 unsigned arithmetic out of range
 Overflow
 signed arithmetic out of range
 Sign
 result is negative
 Zero
 result is zero
 Auxiliary Carry
 carry from bit 3 to bit 4
 Parity
 sum of 1 bits is an even number 22
Irvine, Kip R. Assembly
Language for Intel-Based
Computers 5/e, 2007.
 Accessing Parts of Registers
 Use 8-bit name, 16-bit name, or 32-bit name
 Applies to EAX, EBX, ECX, and EDX
8 8

AH AL 8 bits + 8 bits

AX 16 bits

EAX 32 bits

Irvine, Kip R. Assembly

23 Language for Intel-Based
Computers 5/e, 2007.
Index and Base Registers
 Some registers have only a 16-bit name for
their lower half:

Irvine, Kip R. Assembly

24 Language for Intel-Based
Computers 5/e, 2007.
 Floating-Point, MMX, XMM Registers
80-bit Data Registers

 Eight 80-bit floating-point data registers ST(0)

 ST(0), ST(1), . . . , ST(7) ST(1)

ST(2)
 arranged in a stack
ST(3)
 used for all floating-point
ST(4)
arithmetic
ST(5)
 Eight 64-bit MMX registers ST(6)
 Eight 128-bit MMX registers for single- ST(7)
instruction multiple-data (SIMD) operations

Opcode Register

Irvine, Kip R. Assembly

25 Language for Intel-Based
Computers 5/e, 2007.
IA-32: Modes of Operation
& Memory Management
 IA-32 Modes of Operation
 Real-address mode  4 GB addressable RAM for each program
(00000000 to FFFFFFFFh)
 1 MB RAM maximum addressable space
 Each program assigned a memory partition
 Backward compatibility : programming
which is protected from other programs
environment of 8086
 Designed for multitasking
 Allows just one task to be active at a time
(only interrupts allowed)  Supported by Linux & MS-Windows

 Allows to switch into other modes  Virtual-8086 mode

 All IA-32 processors boot in  Ability to execute older Real-address mode-
real-address mode softwares “in a multitasking
environment”
 Protected mode
 Native state of IA-32 processors  System management mode
 Assigns each process a total of 4GB of  power management, system security,
memory diagnostics

 Memory reference outside allocated

27
segment is checked
1-Real Address Mode

 Single tasking allowing 1MB storage

 Supported by MS-DOS operating system
 Challenge
 8086 has 16 bit registers
 Managing 20 bit address using 16 bit registers ?

 Solution
 Segmented Memory Model
 Memory organized in form of 64KB segments

 Addressing
 Segment : Offset Model
Segmented Memory
Segmented memory addressing: absolute (linear)
address is a combination of a 16-bit segment value
added to a 16-bit offset

F0000
E0000 8000:FFFF
D0000 one segment
C0000
B0000
A0000
90000
80000
70000
60000
8000:0250
50000
0250
40000
30000 8000:0000
20000
10000 Segment: 64K units
seg ofs
00000
 Calculating Linear Addresses
 Given a segment address, multiply it by 16 (add
a hexadecimal zero), and add it to the offset
 Example: convert 08F1:0100 to a linear address
Adjusted Segment value: 0 8 F 1 0
Add the offset: 0 1 0 0
Linear address: 0 9 0 1 0

 A typical program has three segments: code, data

and stack. Segment registers CS, DS and SS are
used to store them separately.
Paging
 Sum of all programs can be larger than physical memory
 Supported directly by the CPU
 Divides each segment into 4096-byte blocks called
pages
 Part of running program is in memory, part is on disk
 Virtual memory manager (VMM) – OS utility that
manages the loading and unloading of pages
 As the program runs, the processor selectively unloads
inactive pages from memory and loads other pages that
are immediately required.
 Page fault – issued by CPU when a page must be
loaded from disk
Questions ??