True Multi-Touch Capacitive Touch Panel Controller

FT5x06
True Multi-Touch
Capacitive Touch Panel Controller
INTRODUCTION
The FT5x06 Series ICs are single-chip capacitive touch panel controller ICs with a built-in 8 bit Micro-controller unit (MCU).They
adopt the mutual capacitance approach, which supports true multi-touch capability. In conjunction with a mutual capacitive touch
panel, the FT5x06 have user-friendly input functions, which can be applied on many portable devices, such as cellular phones, MIDs,
netbook and notebook personal computers.
The FT5x06 series ICs include FT5206/FT5306/FT5406, the difference of their specifications will be listed individually in this
datasheet.
FEATURES
 Capable of Driving Single Channel (transmit/receive) Re-
 Mutual Capacitive Sensing Techniques sistance: Up to15K Ω
 True Multi-touch with up to 10 Points of Absolution X and  Capable of Supporting Single Channel (transmit/receive)
Y Coordinates Capacitance: 60 pF
 Immune to RF Interferences  Optimal Sensing Mutual Capacitor: 1pF~4pF
 Auto-calibration: Insensitive to Capacitance and Environ-  12-Bit ADC Accuracy
mental Variations
 Built-in MCU with 28KB Program Memory, 6KB Data
 Supports up to 28 Transmit Lines and 16 Receive Lines Memory and 256B Internal Data Space
 Supports up to 8” Touch Screen  11 Internal Interrupt Sources and 2 External Interrupt
 Full Programmable Scan Sequences with Individual Ad- Sources
justable Receive Lines and Transmit Lines to Support  3 Operating Modes
Various Applications
 Active
 High Report Rate: More than 100Hz
 Monitor
 Touch Resolution of 100 Dots per Inch (dpi) or above --  Hibernate
depending on the Panel Size
 Operating Temperature Range: -20°C to +85°C
 Optional Interfaces :I2C/SPI
 2.8V to 3.6V Operating Voltage
 Supports 1.8V/AVDD IOVCC
FocalTech Systems Co., Ltd · www.focaltech-systems.com · [email protected]
Document Number: D-FT5x06-1212-V4.0 (Version: 4.0) Revised Dec. 18, 2012
From No.: F-OI-RD01-03-03-B

FT5x06
DATASHEET
TABLE OF CONTENTS
\\
INTRODUCTION..................................................................................................................................................... I
FEATURES............................................................................................................................................................... I
1 OVERVIEW ......................................................................................................................................................... 1
1.1 TYPICAL APPLICATIONS ................................................................................................................................... 1
2 FUNCTIONAL DESCRIPTION .............................................................................................................................. 1
2.1 MCU ........................................................................................................................................................... 2
2.2 OPERATION MODES ........................................................................................................................................ 2
2.3 HOST INTERFACE ............................................................................................................................................ 3
2.4 SERIAL INTERFACE ......................................................................................................................................... 3
2.4.1 I2C ..................................................................................................................................................... 3
2.4.2 SPI ..................................................................................................................................................... 4
3 ELECTRICAL SPECIFICATIONS ........................................................................................................................................... 8
3.1 ABSOLUTE MAXIMUM RATINGS ...................................................................................................................................... 8
3.2 DC CHARACTERISTICS ............................................................................................................................................... 9
3.3 AC CHARACTERISTICS............................................................................................................................................... 9
3.4 I/OPORTSCIRCUITS ................................................................................................................................................10
3.5 POWER ON/RESET/WAKE SEQUENCE ..............................................................................................................................11
4 PIN CONFIGURATIONS ..................................................................................................................................................12
5 PACKAGE INFORMATION ...............................................................................................................................................15
5.1 PACKAGE INFORMATION OF QFN-5X5-40L PACKAGE .................................................................................................................15
5.2 PACKAGE INFORMATION OF QFN-6X6-48L PACKAGE .................................................................................................................16
5.3 PACKAGE INFORMATION OF QFN-6X6-56L PACKAGE ..................................................................................................................17
5.4 PACKAGE INFORMATION OF QFN-8X8-68L PACKAGE ..................................................................................................................18
5.5 ORDER INFORMATION ...............................................................................................................................................19
FocalTech Systems Co., Ltd · www.focaltech-systems.com · [email protected]
Document Number: D-FT5x06-1212-V4.0 (Version: 4.0) Revised Dec. 18, 2012
From No.: F-OI-RD01-03-03-B

1 OVERVIEW
1.1 Typical Applications
FT5x06 accommodate a wide range of applications with a set of buttons up to a 2D touch sensing device, their typical applications are
listed below.
 Mobile phones, smart phones
 MIDs
 Netbook
 Navigation systems, GPS
 Game consoles
 Car applications
 POS (Point of Sales) devices
 Portable MP3 and MP4 media players
 Digital cameras
FT5x06 Series ICs support < 8.0” Touch Panel, users may find out their target IC from the specs listed in the following table,
Panel Package Recommended

Model Name Touch Panel Size
TX RX Type Pin Size Pitch
FT5206GE1 15 10 QFN5*5 40 0.75-P0.4 ≤3.7" ~5mm
FT5306DE4 20 12 QFN6*6 48 0.75-P0.4 ≤5.0" ~5mm
FT5406DQ9 26 16 QFN6*6 56 0.55-P0.35 ≤7.0" ~5mm
FT5406EE8 28 16 QFN8*8 68 0.75-P0.4 ≤8.0" ~6mm
Remarks: FocalTech suggests to use pitch between 4.0mm to 6.0mm; The customer can decide the pitch based on applications.
2 FUNCTIONAL DESCRIPTION
Architectural OverviewFigure2-1 shows the overall architecture for the FT5x06.
Figure 2-1 FT5x06 System Architecture Diagram
The FT5x06 is comprised of five main functional parts listed below,

 Touch Panel Interface Circuits
The main function for the AFE and AFE controller is to interface with the touch panel. It scans the panel by sending AC signals to the
THIS DOCUMENT CONTAINS INFORMATION PROPRIETARY TO FOCALTECH SYSTEMS CO., LTD., AND MAY NOT BE
REPRODUCED, DISCLOSED OR USED IN WHOLE OR PART WITHOUT THE EXPRESS WRITTEN PERMISSION OF
FOCALTECH SYSTEMS CO., LTD.
Copyright © 2012, FocalTech Systems Co., Ltd . All rights reserved Version 4.0︱Page 1 of 21
panel and processes the received signals from the panel. So, it supports both Transmit (TX) and Receive (RX) functions. Key pa-
rameters to configure this circuit can be sent via serial interfaces, which will be explained in detail in a later section.
 8051-based MCU
This MCU is 8051 compatible with some enhancements. For instant, larger program and data memories are supported. In addition, a
Multiplication-Division unit (MDU) is implemented to speed up the touch detection algorithms. Furthermore, a Flash ROM is im-
plemented to store programs and some key parameters.
Complex signal processing algorithms are implemented with firmware running on this MCU to process further the received signals in
order to detect the touches reliably. Communication protocol software is also implemented on this MCU to exchange data and control
information with the host processor.
 External Interface
 I2C/SPI: an interface for data exchange with host
 INT: an interrupt signal to inform the host processor that touch data is ready for read
 WAKE: an interrupt signal for the host to change FT5x06 from Hibernate to Active mode
 /RST: an external low signal reset the chip.
 A watch dog timer is implemented to ensure the robustness of the chip.
 A voltage regulator to generate 1.8V for digital circuits from the input VDD3 supply
 Power On Reset (POR) is active until VDDD is higher than some level and hold decades of μs.
2.1 MCU
This section describes some critical features and operations supported by the 8051 compatible MCU.
Figure 2-2 shows the overall structure of the MCU block. In addition to the 8051 compatible MCU core, we have added the following
circuits,
 MDU: A 16x8 Multiplier and A 32/32 Divider
 Program Memory: 28KB Flash
 Data Memory: 6KB SRAM
 Real Time Clock (RTC): A 32KHz RC Oscillator
 Timer: A number of timers are available to generate different clocks
 Master Clock: 24/ 48MHz from a 48MHz RC Oscillator
 Clock Manager: To control various clocks under different operation conditions of the system
Figure 2-2 MCU Block Diagram

2.2 Operation Modes
FT5x06 operates in the following three modes:
 Active Mode
When in this mode, FT5x06 actively scans the panel. The default scan rate is 60 frames per second. The host processor can configure
FT5x06 to speed up or to slow down.
 Monitor Mode
When in this mode, FT5x06 scans the panel at a reduced speed. The default scan rate is 25 frames per second and the host processor
can increase or decrease this rate. When in this mode, most algorithms are stopped. A simpler algorithm is being executed to determine
if there is a touch or not. When a touch is detected, FT5x06 shall enter the Active mode immediately to acquire the touch information
quickly. During this mode, the serial port is closed and no data shall be transferred with the host processor.
 Hibernate Mode
In this mode, the chip is set in a power down mode. It shall only respond to the “WAKE” or “RESET” signal from the host processor.
The chip therefore consumes very little current, which help prolong the standby time for the portable devices.
2.3 Host Interface

Figure 2-3 shows the interface between a host processor and FT5x06. This interface consists of the following three sets of signals:
 Serial Interface
 Interrupt from FT5x06 to the Host
 Wake-up Signal from the Host to FT5x06
TP Module
Serial
Interface
TX
TP FT5x06 Host
RX
/INT
/WAKE
Figure 2-3 Host Interface Diagram
The serial interfaces of FT5x06 is I2C or SPI. The details of this interface are described in detail in Section 2.5. The interrupt signal
(/INT) is used for FT5x06 to inform the host that data are ready for the host to receive. The /WAKE signal is used for the host to wake
up FT5x06 from the Hibernate mode. After exiting the Hibernate mode, FT5x06 shall enter the Active mode.
2.4 Serial Interface

FT5x06 supports the I2C or SPI interfaces, which can be used by a host processor or other devices.
2.4.1 I2C
The I2C is always configured in the Slave mode. The data transfer format is shown in Figure 2-4.
Figure 2-4 I2C Serial Data Transfer Format
Figure 2-5 I2C master write, slave read
Figure 2-6 I2C master read, slave write

Table 2-1 lists the meanings of the mnemonics used in the above figures.
Table 2-1 Mnemonics Description
Mnemonics Description
S I2C Start or I2C Restart
Slave address
A[6:0] A[6:4]: 3’b011
A[3:0]: data bits are identical to those of I2CCON[7:4] register.
W 1’b0: Write
R 1’b1: Read
A(N) ACK(NACK)
STOP: the indication of the end of a packet (if this bit is missing, S will indicate the end
P
of the current packet and the beginning of the next packet)
I2C Interface Timing Characteristics is shown in Table 2-2.

Table 2-2 I2C Timing Characteristics
Parameter Unit Min Max

SCL frequency KHz 0 400
Bus free time between a STOP and START condition us 4.7 \
Hold time (repeated) START condition us 4.0 \
Data setup time ns 250 \
Setup time for a repeated START condition us 4.7 \
Setup Time for STOP condition us 4.0 \
2.4.2 SPI
SPI is a 4 wire serial interface. The following is a list of the 4 wires:
 SCK: serial data clock
 MOSI: data line from master to slave
 MISO: data line from slave to master
 SLVESEL: active low select signal
SPI transfers data at 8bit packets. The phase relationship between the data and the clock can be defined by the two registers: phase and
polck. Some data transfer examples can be found in Figure 2-7 to Figure 2-10.
Figure 2-7 SPI Data Transfer Format (Phase=0, POLCK=0)
Figure 2-8 SPI Data Transfer Format (PHASE=0, POLCK=1)

SPI can be configured into either Master or Slave mode via the MAS bit of the SPI0CON register. When in the Master mode, the SPI
needs to supply the data clock, whose frequency relationship with the Master clock can be set by CLKDVD bits of the SPI0CON
register. When it is configured in the Slave mode, the clock, SCK, is supplied by the external Master. The maximum data clock fre-
Fmclk
quency must not be higher than .
8
SPI Interface Timing Characteristics is shown in the following Figure2-11,Figure2-12, Figure2-13, Figure2-14 and Table 2-3.
Figure 2-11 SPI master Timing PHASE =0
PHASE=1
Tmck
Tmckl
h
SCK(POLCK=0)
SCK(POLCK=1)
Tmh Tmo
MOSI
MISO
Tmsr
SLVSEL c
Tmsfc
Figure 2-12 SPI master Timing PHASE =1
Figure 2-13 SPI slave Timing PHASE = 0
PHASE=1
Tsck
Tsckl
h
SCK(POLCK=0)
SCK(POLCK=1)
T
Th
s
MOSI
MISO
To
Tsr
SLVSEL c
Tsfc
Figure 2-14 SPI slave Timing PHASE = 1

Table 2-3 SPI Timing Parameters
Parameter Description Min Max Units
Master Mode timing (see figure 2-11,2-12)
Tmckh sck high time 4×Tsysclk -- ns
Tmckl sck low time 4×Tsysclk -- ns
Tmo sck shift edge to mosi data change 0 -- ns
Tmh mosi data valid to sck shift edge 3×Tsysclk -- ns
Tsd slvsel falling edge to mosi data valid 4×Tsysclk -- ns
Tmsfc slvsel falling edge to first sck edge (Tmckh+Tmckl)/2 -- ns
Tmsrc last sck edge to slvsel rising edge (Tmckh+Tmckl)/2 -- ns
Slave mode timing(See figure 2-13,2-14)
Tsckh sck high Time 4×Tsysclk -- ns
Tsckl sck low Time 4×Tsysclk -- ns
Tsd slvsel falling edge to Miso valid data time 0 4xTsysclk ns
Ts Mosi Data valid to sck sample edge 0 -- ns
Th sck sample edge to Mosi data change 4×Tsysclk -- ns
To sck shift edge to Miso data change 0 4xTsysclk ns
Tsfc slvsel falling edge to first sck edge 4×Tsysclk -- ns
Tsrc last sck edge to slvsel rising edge 4×Tsysclk -- ns
*Tsysclk is equal to one period of the device system clock
3 ELECTRICAL SPECIFICATIONS
3.1 Absolute Maximum Ratings
Table 3-1 Absolute Maximum Ratings
Item Symbol Unit Value Note
Power Supply Voltage 1 VDDA - VSSA V -0.3 ~ +3.6 1, 2
Power Supply Voltage 2 VDD3 – VSS V -0.3 ~ +3.6 1, 3
I/O Power Supply Voltage Vt V -0.3 ~ IOVCC + 0.3 1,4
Operating Temperature Topr ℃ -20 ~ +85 1
Storage Temperature Tstg ℃ -55 ~ +150 1
Notes
1. If used beyond the absolute maximum ratings, FT5x06 may be permanently damaged. It is strongly recommended that the device be
used within the electrical characteristics in normal operations. If exposed to the condition not within the electrical characteristics, it
may affect the reliability of the device.
2. Make sure VDDA (high) ≥VSSA (low)
3. Make sure VDD (high) ≥VSS (low)
4. IOVCC is set to VDD3 or VDDD by software configuration.
3.2 DC Characteristics
Table 3-2 DC Characteristics (VDDA=VDD3=2.8~3.6V, Ta=-20~85℃)
Item Symbol Unit Test Condition Min. Typ. Max. Note

Input high-level voltage VIH V 0.7 x IOVCC -- IOVCC
Input low -level voltage VIL V -0.3 -- 0.3 x IOVCC
Output high -level voltage VOH V IOH=-0.1mA 0.7 x IOVCC -- --
Output low -level voltage VOL V IOH=0.1mA -- -- 0.3 x IOVCC
I/O leakage current ILI μA Vin=0~VDDA -1 -- 1
Current consumption VDDA=VDD3 = 2.8V

Iopr mA -- 6 --
（Normal operation mode） Ta=25℃ MCLK=24MHz
Imon mA -- 4 --
（Monitor mode） Ta=25℃ MCLK=24MHz
Islp mA -- 0.03 --
（Sleep mode） Ta=25℃ MCLK=24MHz
Step-up output voltage VDD5 V VDDA=VDD3= 2.8V 5 5.25 5.5
VDDA
Power Supply voltage V 2.8 -- 3.6
VDD3
3.3 AC Characteristics
Table 3-3 AC Characteristics of Oscillators
Item Symbol Unit Test Condition Min. Typ. Max. Note

VDD3 = 2.8V
OSC clock 1 fosc1 MHz Ta=25℃ 43 48 52
VDD3 = 2.8V
OSC clock 2 fosc2 KHz 29 32 36
Ta=25℃
Table 3-4 AC Characteristics of TX & RX

Item Symbol Unit Test Condition Min Typ Max Note
TX acceptable clock ftx KHz 100 150 270
TX output rise time Ttxr nS -- 20 --
TX output fall time Ttxf nS -- 20 --
RX input voltage Trxi V 1.2 -- 1.6
HIS DOCUMENT CONTAINS INFORMATION PROPRIETARY TO FOCALTECH SYSTEMS CO.,LTD., AND MAY NOT BE
FOCALTECH SYSTEMS CO.,LTD.
Copyright © 2012, FocalTech Systems CO.,Ltd . All rights reserved Version 3.0︱Page 9 of 21
3.4 I/OPortsCircuits
Figure 3-1 Digital Input & Output Port Circuits

Figure 3-2 Digital In/Out Port Circuit
Figure 3-3 Reset Input Port Circuits Figure 3-4 Wake Input Port Circuits
Figure 3-5 INT output Port Circuits Figure 3-6 SCL/SDA Port Circuits
3.5 POWER ON/Reset/Wake Sequence
Reset and GPIO such as Wake, INT and I2C are advised to be low before powering on. The signal of waking up should be set to be
high after powering on. INT signal will be sent to the host after initializing all parameters and then start to report points to the host. If
Power is down, the voltage of supply must be below 0.3V and Trst is more than 5ms.
Tris
Power
Figure 3-7 Power on time
Trst
Power
0.3V
Figure 3-8 Power Cycle requirement
T rtp
T vdr
T vd r
Tpo n
VD D
R es et
W ake
INT
I 2C/ SP I
Figure 3-9 Power on / down Sequence

Reset time must be enough to guarantee reliable reset, the time of starting to report point after resetting approach to the time of
starting to report point after powering on.
Trs i
Trs t
Power
RESET
INT
I2C/SPI
Figure 3-10 Reset Sequence
Wake time must be enough to wake up the system, the time of starting to report point after waking approach to the time of starting to
report point after powering on
Tw ai
T wak
Power
Wakeup
INT
I2C/SPI
Figure 3-11 Wake Sequence
Table 3-5 Power on/Reset/Wake Sequence Parameters
Parameter Description Min Max Units

Tris Rise time from 0.1VDD to 0.9VDD -- 5 ms
Trtp Time of resetting to be low before powering on 100 -- μs
Tpon Time of starting to report point after powering on 400 -- ms

Tvdr Reset time after VDD powering on 1 -- ms
Trsi Time of starting to report point after resetting 400 -- ms
Trst Reset time 5 -- ms
Twai Time of starting to report point after waking 300 -- ms
Twak Wake up time 5 -- ms
4 PIN CONFIGURATIONS
Pin List of FT5x06
Table 4-1 Pin Definition of FT5x06
Pin No.
Name Type Description
FT5206GE1 FT5306DE4 FT5406DQ9 FT5406EE8
VSSA 40 1 56 1 PWR Analog ground
NC 1 2 2 Not connected
NC 48 3 Not connected
TX28 4 O Transmit output pin
TX27 5 O Transmit output pin
TX26 1 6 O Transmit output pin
TX20 3 7 12 O Transmit output pin
TX15 2 8 12 17 O Transmit output pin
internal generated 5V power supply,A 1μF
VDD5 17 23 27 32 PWR
ceramic capacitor to ground is required.
VDD3 18 24 28 33 PWR Analog power supply
VSS 19 25 29 34 PWR Analog ground
Digital power supply (1.8V), generated in-
VDDD 20 26 30 35 PWR ternal. A 1μF ceramic capacitor to ground is
required.
Test mode enabled at high and float in normal
TEST_EN 21 27 31 36 I
mode
GPIO0 37 I/O General Purpose Input/Output port
SPI Slave mode, chip select, active low / I2C
SSEL/SCL 22 28 32 41 I/O
clock input
SPI Slave mode, clock input / General Pur-
SCK/GPIO 23 29 33 42 I
pose Input/Output port
SPI Slave mode, data input / I2C data input
MOSI/SDA 24 30 34 43 I/O
and output
MISO 25 31 35 44 O SPI Slave mode, data output
/RST 26 32 36 45 I External Reset, Low is active
WAKE 27 33 37 46 I External interrupt from the host
INT 28 34 38 47 O External interrupt to the host
NC 48 Not connected
NC 49 Not connected
NC 50 Not connected
NC 51 Not connected
VDDA 30 35 39 52 PWR Analog power supply
RX1 29 36 40 53 I Receiver input pins
RX11 46 50 63 I Receiver input pins
RX12 47 51 64 I Receiver input pins
RX13 52 65 I Receiver input pins
FT5206GE1 Package Diagram FT5306DE4 Package Diagram
VDDA
RX15
RX14
RX12
RX11
RX10
RX16
RX13
RX2
RX1
RX9
RX8
RX7
RX6
RX5
RX4
RX3
VSSA
RX15
RX14
RX12
RX11
RX10
RX16
RX13
RX9
RX8
RX7
RX6
RX5
RX4
63
62
61
60
57
56
55
54
68
67
66
65
64
59
58
53
VSSA 1 52 51 NC
56
55
54
52
51
50
45
44
53
49
48
47
46
43
NC 2 50 NC
TX26 1 42 RX3 NC 3 49 NC
TX25 2 41 RX2 TX28 4 48 NC
TX24 3 40 RX1 TX27 5 47 INT
TX23 4 39 VDDA TX26 6 46 WAKE
TX22 5 38 INT TX25 7 45 /RST
TX21 6 37 WAKE TX24 8 44 MISO
TX20 7 36 /RST TX23 9 43 MOSI/SDA
TX19 8 35 MISO TX22 10 42 SCK
TX18 9 34 MOSI/SDA TX21 11 41 SSEL/SCL
TX17 10 33 SCK TX20 12 40 GPIO3
TX16 11 32 SSEL/SCL TX19 13 39 GPIO2
TX15 12 31 TEST_EN TX18 14 38 GPIO1
TX14 13 30 VDDD TX17 15 37 GPIO0
TX13 14 29 VSS TX16 16 36 TEST_EN
TX15 17 35 VDDD
20
21
22
23
26
27
28
18
19
24
25
15
16
17
20
21
22
23
26
27
28
29
33
34
18
19
24
25
30
31
32
TX12
TX11
TX10
VDD5
TX9
TX8
TX7
TX6
TX5
TX4
TX3
TX2
TX1
VDD3
TX13
TX14
TX12
TX11
TX10
VDD5
VDD3
TX9
TX8
TX7
TX6
TX5
TX4
TX3
TX2
VSS
TX1
FT5406DQ9 Package Diagram FT5406EE8 Package Diagram
5 PACKAGE INFORMATION
5.1 Package Information of QFN-5x5-40L Package
Millimeter
Item Symbol
Min Type Max
Total Thickness A 0.7 0.75 0.8
Stand Off A1 0 0.035 0.05
Mold Thickness A2 ---- 0.55 0.57
L/F Thickness A3 0.203 REF
Lead Width b 0.15 0.20 0.25
D 5 BSC
Body Size
E 5 BSC
Lead Pitch e 0.4 BSC
J 3.5 3.6 3.7
EP Size
K 3.5 3.6 3.7
Lead Length L 0.35 0.4 0.45
Package Edge Tolerance aaa 0.1
Mold Flatness bbb 0.1
Co Planarity ccc 0.08
Lead Offset ddd 0.1
eee 0.1
Exposed Pad Offset
Millimeter
Item Symbol
Min Type Max
Stand Off A1 0 0.035 0.05
Lead Width b 0.15 0.20 0.25
D 6 BSC
Body Size
E 6 BSC
J 4.1 4.2 4.3
EP Size
K 4.1 4.2 4.3
Co Planarity ccc 0.08
Lead Offset ddd 0.1
Exposed Pad Offset eee 0.1
Millimeter
Item Name Symbol
Min Type Max
Stand Off A1 0 0.035 0.05
Mold Thickness A2 ---- 0.4 ----
Lead Width b 0.13 0.18 0.23
D 6 BSC
Body Size
E 6 BSC
J 4.6 4.7 4.8
EP Size
K 4.6 4.7 4.8
Coplanarity ccc 0.08
Lead Offset ddd 0.1
Millimeter
Item Name Symbol
Min Type Max
Stand Off A1 0 0.035 0.05
Lead Width b 0.15 0.20 0.25
D 8 BSC
Body Size
E 8 BSC
J 6.1 6.2 6.3
EP Size
K 6.1 6.2 6.3
Coplanarity ccc 0.08
Lead Offset ddd 0.1
5.5 Order Information
QFN
Package Type 40Pin(5 * 5 )/48Pin( 6 * 6 )/56Pin( 6 * 6 )/68Pin ( 8 * 8 )
0.75 - P0.4/0.55 - P0.35
Product Name FT5206GE1/ FT5306DE4/ FT5406DQ9/FT5406EE8
Note:
1). The last two letters in the product name indicate the package type and lead pitch and thickness.
2). The second last letter indicates the package type.
D : QFN-6*6 , E : QFN-8*8, G : QFN-5*5
3). The last letter indicates the lead pitch and thickness.
E : 0.75 - P0.4 , Q:0.55-P0.35
T: Track Code
F/R:”F” for Lead Free process, F T 5x06xxx
”R” for Halogen Free process TFYWWSV
Y: Year Code
WW: Week Code
S: Lot Code
V：IC Version
Product Name Package Type # TX Pins # RX Pins
FT5206GE1 QFN-40L 15 10
FT5306DE4 QFN-48L 20 12
FT5406DQ9 QFN-56L 26 16
FT5406EE8 QFN-68L 28 16
END OF DATASHEET

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FT5x06

FocalTech Systems Co., Ltd · www.focaltech-systems.com · [email protected]

Document Number: D-FT5x06-1212-V4.0 (Version: 4.0) Revised Dec. 18, 2012

From No.: F-OI-RD01-03-03-B

FocalTech Systems Co., Ltd · www.focaltech-systems.com · [email protected]

Document Number: D-FT5x06-1212-V4.0 (Version: 4.0) Revised Dec. 18, 2012

From No.: F-OI-RD01-03-03-B

Panel Package Recommended

FT5306DE4 20 12 QFN6*6 48 0.75-P0.4 ≤5.0" ~5mm

FT5406DQ9 26 16 QFN6*6 56 0.55-P0.35 ≤7.0" ~5mm

FT5406EE8 28 16 QFN8*8 68 0.75-P0.4 ≤8.0" ~6mm

Figure 2-1 FT5x06 System Architecture Diagram

The FT5x06 is comprised of five main functional parts listed below,

Figure 2-2 MCU Block Diagram

2.3 Host Interface

Figure 2-3 Host Interface Diagram

2.4 Serial Interface

Figure 2-4 I2C Serial Data Transfer Format

Figure 2-6 I2C master read, slave write

I2C Interface Timing Characteristics is shown in Table 2-2.

Parameter Unit Min Max

Figure 2-8 SPI Data Transfer Format (PHASE=0, POLCK=1)

Figure 2-9 SPI Data Transfer Format (Phase=1, POLCK=0)

Figure 2-10 SPI Data Transfer Format (Phase=1, POLCK=1)

Figure 2-12 SPI master Timing PHASE =1

Figure 2-14 SPI slave Timing PHASE = 1

Item Symbol Unit Test Condition Min. Typ. Max. Note

Input low -level voltage VIL V -0.3 -- 0.3 x IOVCC

Output high -level voltage VOH V IOH=-0.1mA 0.7 x IOVCC -- --

Output low -level voltage VOL V IOH=0.1mA -- -- 0.3 x IOVCC

I/O leakage current ILI μA Vin=0~VDDA -1 -- 1

Current consumption VDDA=VDD3 = 2.8V

Step-up output voltage VDD5 V VDDA=VDD3= 2.8V 5 5.25 5.5

Item Symbol Unit Test Condition Min. Typ. Max. Note

Table 3-4 AC Characteristics of TX & RX

TX output rise time Ttxr nS -- 20 --

TX output fall time Ttxf nS -- 20 --

RX input voltage Trxi V 1.2 -- 1.6

Figure 3-1 Digital Input & Output Port Circuits

Figure 3-7 Power on time

Figure 3-8 Power Cycle requirement

Figure 3-9 Power on / down Sequence

Parameter Description Min Max Units

Tpon Time of starting to report point after powering on 400 -- ms

FT5206GE1 Package Diagram FT5306DE4 Package Diagram

FT5406DQ9 Package Diagram FT5406EE8 Package Diagram

Product Name Package Type # TX Pins # RX Pins

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