Logic BIST for Large Industrial Designs: Real Issues and Case Studies

Nagesh Tamarapalli, Mark Kassab,

Abu Hassan, and Janusz Rajski
Mentor GraRhics Corporation
8005 S.W. Boeckman Road
Wilsonville, OR 97070, USA

Abstract [I]. Note that manufacturing test is applied to every device

multiple times, at different voltage levels, at the wafer,
packaged device, etc. The manufacturing test cost is
incurred for every manufactured device and might be as
high as 25-30% of the total manufacturing cost.
Logic built-in self-test (BIST) is based on scan as the
fundamental DFT methodology [2,3,4,5]. Initially, the pre-
dominant compelling reason for the adoption of BIST was
the requirement to perform in-field testing. Recently, there
has been growing interest in BIST as it can reduce the cost
of manufacturing test as well as improve the quality of the
test by providing at-speed testing capability. In BIST, pseu-
dorandom patterns are generated on chip, the responses are
compacted on chip, and the control signals are driven by an
on-chip controller. The amount of test data exchanged with
the tester is therefore drastically reduced. In addition, the
scan cells are configured into a large number of relatively
short scan chains, thus reducing the time required to apply
a single test pattern. The low memory and performance
requirements on the tester allows the usage of very low cost
testers for manufacturing test of designs with logic BIST.
Logic BIST is based on pseudorandom patterns and
involves compaction of test responses. Those two charac-
teristics impose more stringent design rules on the BISTed
logic than scan with stored patterns. Logic BIST requires
that bus conflicts are eliminated, sources of X states are
properly bounded to prevent corruption of the signatures,
the circuit is random-pattern testable, etc. In many cases,
the original design does not satisfy many of these require-
ments, thus posing barriers to BIST. In those cases, and in
general, the only practical way to implement BIST is
through automation of the design tasks and their integration
in the overall methodology and design flow.
The introduction of logic BIST at the Texas Instruments
MOS design center is driven by limitations of the cur-
rently-used test equipment and a number of specific goals.
In particular, the testers currently used already limit the
ability to run available tests in the following ways:
1. Scan operates at a maximum frequency of 50 MHz.
2. Tester scan memory is usually filled.
3. Tester has a maximum of 8.scan chains, resulting in a
long test application time for large designs.
4. Tester functional test memory is also filled, leading to
utilization of as little as 10% of the available func-
tional tests.

Paper 142 ITC INTERNATIONAL TEST CONFERENCE

358 $10.00 01999 IEEE
0-7803-5753-1/99
 5. Transition fault or path delay scan ATPG patterns are eral shallow BIST-mode scan chains into a few deep
not used due to lack of tester memory. ATPG-mode scan chains accessed directly from the chip
All these problems are constantly getting worse. They pins in case top-up ATPG is used to improve the fault cov-
could be solved by investing in tester technology. However, erage obtained by BIST.
logic BIST is an attractive alternative solution as it removes
most of the tester limitations. Given the current design
environment and ATPG practice, the following basic logic
BIST goals were derived:
G 1. Eliminate tester memory and frequency limitations.
G2. Solution provides at-speed scan testing.
G3. Solution works for 1-2 million logic gate designs.
G4. BIST stuck-at grade 5 95%.
G5. Logic BIST area overhead 5 2% of logic.
G6. Silicon BIST run time < 1 second.
G7. Engineering effort < 2 person months per design.
It is also important that logic BIST fits seamlessly into
the current design process and that the overnight design
synthesis time is not compromised, hence the following I
additional flow-related goals: I
BIST mode
G8. Ability to use ATPG or logic BIST tests.
G9. Minimal impact on current design methodology. Figure 1: Generic scan-basedlogic BIST architecture.
G10. Automation of the logic BIST flow.
G 11. Additional RTL-to-gates run time < 2 hours. The BIST can be initiated.either through a boundary
G12. Logic BIST fault grade run time < 12 hours. scan TAP controller or by appropriately,asserting a set of
G13. Logic BIST IkosTMsimulation time < 12 hours, new primary inputs in case a stand-alone mode logic BIST
G14. BIST can be run on a very low cost tester. controller is implemented. Prior to running the actual test,
In Section 11, the logic BIST architecture is presented the controller components such as PRPG, MISR and the
with particular emphasis on the controller and its ability to pattern counter need to be initialized. In addition, the inter-
support multi-clock multi-frequency designs. Section I11 nal scan chains can also be optionally initialized. The
covers generation of the BIST-ready core including inser- actual test of the circuit consisting of several patterns then
tion of test points, bounding of X generators, and handling begins. For each pattern the shift counter counts
of primary inputs and outputs. Section IV is devoted to (Nsc + NclC) cycles where Nsc , the number of cycles in
detailed presentation of four case studies. Finally, conclu- the shift window is equal to the length of the longest scan
sions are presented in Section V. chain and N, ,the number of cycles in capture window is
typically equal to one for a simple capture window. Hence
in order to reduce the test application time it is necessary to
11. LOGIC BIST ARCHITECTURE
configure the scan cells into a large number of shallow scan
chains. A systematically designed phase shifter circuit
A. Generic scan based logic BIST architecture [6,7] is placed between the.LFSR and the scan chain inputs
A generic single clock logic BIST architecture based on to eliminate structural dependencies and allow a large num-
the well known STUMPS technique [6] is illustrated in ber of scan chains to be driven by a relatively short LFSR.
Figure 1. The figure depicts the circuit-under-test or core, Similarly an XOR structure called space compactor is
and the logic BIST controller in the highlighted area. The required to compact the large number of scan outputs
circuit is composed of combinational logic, and possibly before feeding them to a small MISR. As with the phase
embedded memories, separated by multiple scan chains. shifter care must be taken in designing the space compactor
to avoid loss of test coverage due to fault masking.
Various components of the logic BIST controller are
shown in the highlighted area. These components include During the shift window of a pattern, new pseudo-ran-
test pattern generation block - composed of the pseudo-ran- dom values from the PRPG are loaded into the scan chains
dom pattern generator (PRPG) and phase shifter circuit, the while simultaneously unloading and compacting the cir-
output response analysis block - composed of multiple- cuit’s response for the previous pattern into the MISR. In
input signature register (MISR), space compactor, and case the internal scan chains are not initialized, for the first
optional AND gates. In addition, there are two counters: pattern, their unknown contents can be blocked as shown in
the pattern counter, and the shift counter which for each Figure 1 by means of AND gates in front of the MISR.
pattern keeps track of the number of cycles required to fill After the scan chains are completely loaded, the multiplex-
the scan chains. The decoder block shown in the figure ers in the scan cells are placed in system mode for one
drives the test points. Finally, the multiplexers between the cycle to capture the circuit’s response. This sequence of
phase shifter and scan inputs are used to concatenate sev- events continues for each pattern. In addition, if multi-

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 the capture window of a test pattern. It is shown that in
order to achieve at-speed test of the circuit, unlike previous
methods [lo],it is not necessary to perform at-speed shift
of the scan chains. In fact only events in the capture win-
dow are crucial to at-speed testing of the circuit.

Figure 2: Multi-frequencylogic BIST controller.

The timing diagram shown in Figure 3 illustrates the

partitioning of a test pattern into shift window and pro-
grammable capture window. The shift window is com-
prised of multiple shift operations required to loadunload
the scan chains. These shift operations can be performed at
a frequency of any of the three clocks or their sub-rnulti-
ples. This freedom of selection of the shift frequency pro-
vides a trade-off between design of scan chains vs. the test
application time. In the example timing diagram in Figure
3, scan chains are shifted at frequency F, of clock clk, .
Note that memory elements in scan chain SC, use the
faster frequency F, during the functional operation. This
frequency is reduced to F2 in the shift window through
clock suppression. Clock suppression in this case sup-
presses every other pulse of clock sys-clkl to generate
slower clock clk, of frequency F,. Scan chain SC, is
clocked by clk, which is driven by sys-clk,. Since the
frequency of sys-clk, is F2, no modification of this clock
is necessary for the shift window. Finally, scan chain SC, is
driven by a slower clock sys-clk, in the system mode.
Clock multiplexing is used to drive clk, with sys-clk, of
frequency F2 during the shift window. Timing diagram of
clk, shows the effect of multiplexing in the faster clock.
The programmable capture window comprises of cap-
tures in different clock domains and some shift operations
to create inter-domain at-speed capture. The functional
clock of each of the domains is used to obtain a shift fol-
lowed by a capture. These two consecutive events using the
functional clock guarantee that every intra-domain path can

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Load-unload window: Programmable capture window:
One of the important advantages of the programmable
Vector N t Vector N
capture window is the robustness against the clock skew.
4

I'
Figure 3 illustrates that whenever any clock domain is cap-
turing data, other clock domains do not have an active
edge. Thus, the capture edge, unlike in previously proposed
solutions, is not susceptible to inter-domain clock skew. In
addition, the capture window can be programmed to per-
form multiple captures in each domain as well as control
slow scan enables. Performing multiple captures reduces
the risk of delay test invalidation and false paths that might
occur due to illegal states in scan chains resulting from fill-
ing them with pseudo-random values from the PRPG. Slow
scan enables, by providing multiple cycles of the fastest
clock for the scan enable signals to settle, reduce con-
straints on their design. They no longer need to be routed as
clock signals. Note that programmability of capture win-
dow can also be used to handle a circuit containing multi-
ple clock domains of the same frequency.
In order to generate appropriate clock control and scan
sen3 enable signals, the pattern and shift counters have to oper-
ate using the fastest clock. Also, unlike the previous con-
troller, the number of cycles in the shift window N s c , is
not necessarily equal to the length of the longest scan
Figure 3: Multi-frequency logic BIST timing diagram. chain. Nsc depends on the longest effective scan length as
determined by the frequency used for shifting the scan
be tested at-speed; i.e., the time between the launch and chains. Similarly Nee, the number of fastest clock cycles
capture events is equal to one functional clock period. Also in the capture window is usually more than one.
to test inter-domain paths, at-speed clock edges are placed On the completion of scan chain loading, a sequence of
appropriately as shown in Figure 3. events is launched in the capture window to perform at-
The exact placement of clock edges for at-speed test of speed testing of intra- and inter-domain logic. Once a pre-
all nine relations is detailed in Table 1. Each table cell determined number of patterns are applied, the contents of
T[i, j ] , corresponding to launch clock clki and capture the MISR can be, as explained earlier, scanned out and
clock clkj, lists the position of the launch pulse of clk, fol- compared externally or compared with an on-chip golden
lowed by the capture pulse of clkj. All the positions are signature.
described in terms of pulses of the fastest clock sys-clk, .
For example, the capture edge for clk, is the rising edge of
111. GENERATING
A BIST-READY CIRCUIT
second clock pulse of clk, in the capture window, which is
equivalent to the rising edge of the fifth clock pulse of In addition to having scan, a BIST-ready circuit should
.
sys-clk, As can be seen, in the capture window clock be random pattern testable and should have no unknown
suppression is used to suppress some pulses of elkl and values propagating to observable points. In this section,
clk, while no pulses of clk, are suppressed. The scan those and other barriers to the implementation of logic
enable signals for each of the clock domains switch to sys- BIST will be discussed and automated solutions to over-
tem mode prior to their respective capture edges. Since the come them will be presented.
scan enable signals have to be routed to all the scan cells in
the circuit, their design constraints can be relaxed by opting A. Random-pattern resistance
for slow scan enables. In the example timing diagram
shown in Figure 3, scan enable Senl is designed to be fast, Logic BIST is in general based on pseudo-random pat-
i.e. it has half-a-cycle of the fastest clock to settle whereas terns. Most circuits, however, have inherent random-pattern
the scan enables Sen2 and Sen3 are designed to be slow, i.e. resistance, which results in relatively poor test coverage. To
they have one-and-half-a-cycleof the fastest clock to settle. achieve test coverage approaching that of ATPG, control
and observe points are added to the circuit to increase its
Table I: Edge placement for intra- and inter-domain at-speed test. susceptibility to random pattern testing.
Capture clock Control points
A control point is inserted on a signal that has a very
high probability of logic 0 or I if this predominant value
causes poor controllability or observability of a sufficiently

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 BIST-mode
Scan-enable

From -
points previous
scan cell
Additional logic Scan cell
Figure 4 Connecting observe points to existing scan cells.

value, since they are only asserted in certain phases, they

do not block fault propagation for the entire test session. In
addition to the low area overhead of the control points in
MTPI, typically fewer are required than when test points
OR gate can similarly be used. are selected using other methods. MTPI’s control points are
3. AND or OR gates can be inserted to force a constant 0 also unlikely to introduce timing problems in test mode;
since they force constant values when activated, and the
signals driving them are only changed during the relatively
long scan load/unload cycle. Note that inserting control
points can affect a circuit’s timing since they add delays
along functional paths. However, it is possible to prevent
insertion of control points along critical paths or blocks.

B. X generators
An essential requirement for a BIST-ready circuit is
that it should not generate any observable unknown states.
If an X propagates to the MISR, it corrupts the signature
and makes it impossible to distinguish faulty and fault-free
circuits. Therefore, test logic must be inserted to suppress
unknown states or prevent them from propagating to an
observable point. Typical potential X generators include
the following:
1. Non-scan flip-flops (FFs).
2. RAMS and CAMS.
3. Combinational loops.
4.Undriven primary inputs.
5. Bus contention.
6. Violation on a wired gate.
Potential X generators can be identified by a design rule
checker. Preventing those X sources from propagating to
the MISR can be accomplished using several methods
which trade area overhead and loss of test coverage.
Bounding X generators
After identifying potential X generators, analysis is per-
formed to determine which of those X sources need to be
bounded. An X generator only needs to be bounded if its
value can propagate to an observable point, or if an observe
point can be inserted such that the X generator becomes
observable. A trade-off can be used to prevent X sources
which are already blocked at a nearby location from being
bounded. Since in this case, the X generator will only be
observable if an observe point is added between the X
source and the locations at which it is blocked, simply
restricting all gates in this region from being considered as

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observe point candidates. eliminates this problem. The logic BIST session follows a memory BIST run, then the
threshold used to determine whether to re-bound a blocked RAM can be disabled at the end of the memory BIST ses-
X generator or exclude its blocked fanout region from con- sion. This forces the outputs of the RAM to have constant
sideration for observe points can be set by the user. values throughout the logic BIST run. While this method
For X generators which must be bounded, this can be has low area overhead, faults propagating to the RAM will
done by inserting one or more control points before the X be blocked if no observe points are inserted on the RAM’s
can propagate to an observable p i n t . For example, if a inputs. Furthermore, constant values will be applied from
non-scan FF has 2 outputs (Q and Q), one control point can the RAM, which can decrease the testability of faults in the
be inserted on each of the outputs and activated in test logic driven by the RAM.
mode. Alternatively, if the FF has asynchronous setheset It may also be possible to bypass some RAMs with low
pins, a control point can be added to force the FF to 0 or 1 hardware overhead and without adding any logic on their
during the test. While a control point can be added to force inputs and outputs. If the RAM supports pass-through
a constant value, it is recommended for higher test cover- where the same address is written and read simultaneously,
age to insert a MUX control point driven by a nearby exist- this mode can be used to make the memory transparent.
ing scan cell, as explained in the control points section. Test logic would be required to force the memory into this
This method for X bounding ensures that no X’s will be mode during the BIST session. The main disadvantage of
observed. However, it does‘not provide means for observ- this method is that while it allows the data inputs to pass
ing faults which can only propagate to an observable point through, faults propagating to the address lines may not be
through the now-blocked X source. This can result in loss tested. Furthermore, if multiple RAMs operate in this
of test coverage. If the number of such faults for a given mode, combinational loops may form. It is therefore rec-
bounded X generator justifies the cost, one or more observe ommended to use the RAM bypass method discussed.
points can be added before the X source to provide an
observationpoint to which those faults can propagate. C. Handling of primary inputs and outputs
Handling embedded memories In logic BIST, only the scan chains are controlled and
observed by default. Since the tester does not drive the test,
Embedded memories, typically RAMs, can act as X it does not drive the primary inputs (PIS) or observe the pri-
generators. However, bounding their outputs can severely mary outputs (POs). If POs are not observed, loss of test
impact test coverage as faults which only propagate to the coverage will result since faults which only propagate to
RAM will not be testable. This includes faults propagating POs and not to scan cells will not be tested. More impor-
to the RAM’s data as well as address and control lines. The tantly, PIS must be driven; in addition to loss of coverage, a
preferred method for handling embedded RAMs is to floating PI is an X generator.
bypass them in test mode. The RAM inputs are connected
to scan cells for observation. The inputs can be connected Control points can be added on the PIS to force them to
to space compactors (XOR trees) before connecting them constant values during the BIST session. While this pre-
to the scan cells, to reduce the number of scan cells vents the PIS from generating X’s, loss in coverage may
required. Those same scan cells are used to drive the out- result due to the constant values forced. The recommended
puts of the RAMs in test mode. Therefore, in test mode, the solution is to use MUX control points and drive the PIS
RAM’s inputs and outputs become pseudo primary inputs from nearby existing scan cells. Therefore, PIS are handled
and outputs, respectively. This is illustrated in Figure 5. It exactly the same as X generators. Only PIS which are
is assumed that some other DFT methodology, typically directly driven by the BIST controller do not need to be
memory BIST, is used to test the RAM itself. bounded. To observe POs during the BIST session, observe
points are used to connect them to scan cells.

Iv. PRACTICAL EXPERIENCE WITH LOGIC BIST

A. Background and motivation

This section describes the practical aspects of introduc-
ing logic BIST into a department that designs large ASICs.
The designs have 200-800K NAND2 gate equivalents of
logic plus an equivalent area of RAMs. There are often
multiple clock domains with frequencies ranging from 2.5
MHz to 150 MHz. Register Transfer Level (RTL) VHDL is
Figure 5: RAM bypass. the design sourcing language. A simplified diagram of the
overall design flow is shown in Figure 6.
If the output multiplexors are not acceptable for timing One of the key design processes is daily execution of
or introduce an unacceptable hardware overheard, an alter- some design flows; design synthesis to gates including scan
native is to freeze the RAM after it is initialized. If the insertion, RTL simulation regression, and IkosTMgate level

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 Table 11: Design data.
I Design Y
I ASICl 1 ASIC2 1 ASIC3 1 ASIC4 I
Core comb. gate count 180K 356K 558K 748K
Number of RAMS 16 10 10 11
t75 MHZ clocks ,1 0 1 1 1 1 1 1 1
I
I I

125 MHz clocks 1 9 1 0 1 0 1 0 1

I 150 MHz clocks
I I I

lI o 1I 1 1I 1 1I 1 1
I

2Y2.5 MHz clocks [ 0 1 0 1 16 I 16 J

L
125/25 MHz clocks I
0 4 2 2
50 MHz clocks I 1 0 0 1

ogy is a small step. However, additional design work arises

as follows:
1, Generation of a BIST controller.
Figure 6: Design flow.
2. Multiplexing and balancing of clocks.
3. Insertion of many short scan chains for use in BIST
mode, and the ability to reconfigure them into.rela-
ure 6. Daily execution of these flows requires them to run tively few, long scan chains for use in ATPG mode.
overnight and therefore in less than 12 hours. 4. Test point insertion.
The DFT/used is nearly full scan, muxed-scan style 5. Handling of observable X generators.
with scan insertion performed on the gate level core netlist. 6. Bounding module inputs.
Scan insertion currently takes 1-2 hours of the allotted 12 7. Fault simulation to measure the fault grade and com-
hours for the flow. While ATPG is important, it is not a crit- pute the MISR signature.
ical path flow; ATPG with pattern compression takes 8. Timing analysis (TA) and resolution of any test point-
approximately one day. Normally, a 10-20% sample of the related TA issues.
ATPG scan pptterns are serially simulated on an IkosTM, 9. Gate level timing simulation verification of BIST
which takes approximately 30 hours. In what follows, issues related to clocks, test point
Silicon testing uses a suite of parametric tests followed insertion, and X generators will be described.
by functional 2Fsts and the scan ATPG tests. Stuck-at ATPG Multi-clock designs require careful balancing of the
grades are approximately 97% and pseudo stuck-at I p D ~ clock trees. Clock skew within a clock tree and between
grades are typplly 80% with 10 stops. The largest designs clock trees must typically be reduced to 0.3 ns at clock
have 40K scan cells, and ATPG of these designs generates speeds of 75 MHz. Such clock control can be achieved
approximately1 5K scan patterns. Assuming that each scan
through ASIC layout clock tree synthesis (CTS) tools. The
cell generates 3 bits of scan test data per scan pattern, these clock multiplexing inherent in a multi-clock logic BIST
5K scan patterns translate to 600 Mb of scan test data. controller is therefore safe as long as the ASIC CTS mac-
These designslhave 8 parallel scan chains and ATPG pat- ros are placed directly on the output of the BIST controller
terns are applied at 20-50 MHz, giving silicon run times of clock multiplexors.
1.3 - 0.5 seconhs. Scan overhead is approximately 9% extra
logic which trhslates to a 4% chip area overhead. MTPI test point insertion uses simple AND or OR gates
I for control points, driven by the test phase control signal.
B. BET implkmentation Selecting gates of sufficient drive ensures correct operation
I
of these static signals. MTPI observe points are imple-
Logic BIST was implemented on a trial basis into four mented as new output signals, new scan cells, or connected
designs. These' are large designs with multiple clocks. into existing scan cells. Each of these three observe point
Table I1 gives gome vital statistics of the designs. The 75 types also has the option of observe point sharing via XOR
MHz and I50 MHz clocks are generated within the trees used as space compactors. Observe point signals must
designs. Although there are lower frequency clocks, all operate at speed so they must be captured close to their
logic works at 75 MHz. For ATPG testing, all clocks run at source; typically within a 20K gate region. The sparsity of
50 MHz and this single-frequency multi-clock test mode observe points within 400-8OOK gate designs is such that
was used for the current logic BIST implementation. observe point sharing would require non-local XOR com-
ASICl clocks run at 125 MHz. The other ASICs' clocks paction trees which would not work at speed. For large
run at 75 MHZ. j designs, observe points must either be connected into local
Logic BIST was implemented using the STUMPS pre-existing scan cells or connected into new additional
architecture, described in Section 11. Moving from a scan local scan cells. The current logic BIST implementation
ATPG methodology to a STUMPS logic BIST methodol- utilized new scan cell observe points for ASICI, and
I

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observe points connected into pre-existing scan cells (using Table 111: Summary of logic BIST results.
the XORIMUX circuit of Figure 4) for the larger ASICs.
The RAMS in the designs can shadow up to 3% -of the
faults. Therefore RAM bypass mode was used as shown in
Figure 5. Using 10 scan cells per RAM leads to a bypass
cost of approximately 125 gates per RAM. Removal of the
other X generators can be done either by manual alteration
of the source VHDL, or automatic bounding as described
in Section 111. Manual VHDL source fixing of X generators
is not practical within the 1-2 person month resource limit
so automatic X bounding was used.
The only practical way to implement logic BIST is
automation of the design tasks together with a methodol-
BIST pattern count 65K 262K 262K 262K
ogy which minimizes the probability of failing timing anal-
ysis and simulation. Our STUMPS implementation BIST stuck-at fault grade
96.0 95.7 95.3 95.6
therefore utilized a tap controller whose RTL was automat- (%)
, I

ically generated. The BIST controller described in Section BIST gates overhead (%) 3.4 2.6 2.1 1.58
I1 was used; its RTL, was also automatically generated. BIST chip area overhead
Finally, the automatic multi-phase test point insertion, X .3 .3 o.8
bounding, and module input bounding described in Section
. ,
(%)
Scan + test point insertion
111 were used. This combination allowed complete automa- 0.7 3.3 6.7 14.5
tion of the logic BIST implementation, thereby freeing the time (hr) \ I
I I I I

1-2 person months of resource to handle issues of timing Fault simulation time (hr)
. . I 0.9 I 3.4 I 5.2 I 4.0
analysis and simulation verification. IkosTMsimulation time
21 n/a n/a
0-4
C. BIST implementation results I

The basic results of the logic BIST implementation are BIST silicon run time
given in Table 111. These results represent typical achieved (sec)
values, not necessarily the optimum possible. Fault grades ATPG grade [%)
are quoted for the design core only but all logic in the ATPG pattern volume
design core is counted, including the bounding multiplex- (Mb)
ors and test point logic. The fault list used is the same as ATPG top-up pattern vol-
that used in ATPG, so all faults in the core are included. ume (Mb)
. .
Thus, no credit is given for possible detected faults, scan
enable faults are not implicitly detected, and faults associ- ATPGfrequency(MH2) 50 40 20 50
ated with tied logic are included as not detected. As can be ATPG silicon run time
.02 0.36 .94 0.7
seen, BIST fault grades of 95-96% are achievable with (sec)
\ I
I I I I

approximately 2% logic overhead. BIST fault simulation

time is within the goal. However, scan and test point inser- Table IV BIST overhead for ASICB
tion time ranges from 1- 14 hours giving an additional RTL- Overhead as %
to-gates time of 0.5-12.5 hours versus the goal of 2 hours. BIST component NAND2 gate of scan-inserted
This additional time is mainly the time spent performing equivalents
netlist
test point insertion, which includes fault grading. ATPG is
performed on the BISTed cores under the same conditions BIST controller I 3489 0.43%
in which BIST is run. The ATPG comparative grades of 97-
98% indicate an expected grade shortfall with using logic
(Core inmtboundingl -
304 I 0.04% I
CAM bounding 1246 0.15%
BIST. Note that while the BIST silicon run times are within
RAM bounding 1140 0.14%
the 1 second goal, they are 2-3 times longer than the ATPG
pattern silicon run times. In the future as ASIC clock fre- X bounding 0.04%
quencies rise to 0.5 GHz and beyond, BIST silicon run 592 control points 0.15%
times will become less than ATPG pattern run times. Logic 1200 observe points 0.63%
BIST test can be.topped up with ATPG of the residual
faults. For these designs, the ATPG top-up pattern volume Total 12762 1.58%
is 25-65% of a full ATPG test.
A breakdown of the BIST overhead for ASIC4 is given Sensitivity of the BIST fault grades to the number of
in Table IV. The biggest contributors are the observe points added test points is shown in Figure 7 for design ASIC3,
and BIST controller. The BIST grades rise sharply as control and observe points

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 I
are added. In the 94-96% region, the grade is relatively This is pre- or post-layout gate level timing simulation of
insensitive to the number of control points but rises signifi- the 65K BIST patterns in full serial mode. This long simu-
cantly as obsyrve points are added. Sensitivity of the grade lation time meant that any debug had to be done using a
to the number of BIST patterns is shown in Figure 8 for BIST controller setup for just a few patterns. Automatic
design ASIC?. Significant grade increases occur for pattern checking of expected against simulated values for key
' counts up to 256K patterns and beyond. points in the BISTed design also facilitated debug. Key
points are the PRPG state, stumps scan-in points, stumps
scan-out points and MISR signature.
ASICl IkosTMsimulation found one timing issue. At
the end of the BIST run, the MISR signature is scanned out
through a relatively slow chip pin driver. Driver delay vari-
ation between min and max timing made the MISR signa-
ture slip by one cycle between these conditions. The
solution to this was to slow the clock to 50 MHz during
scan of the MER.
Addressing the design process goals of logic BIST, the
new design flow is shown in Figure 9. The changed compo-
nents are highlighted. From the viewpoint of the main
design processes, this new design flow is essentially
unchanged. The only change to these main processes is the
addition of automatic bounding and test point insertion to
the scan insertion step. The DFT engineer, however, has the
extra tasks of RTL VHDL generation of the TAP and BIST
controller and the job of getting satisfactory results for gate
level BIST fault simulation and functional and timing sim-
ulation. Finally, any timing issues with the inserted test
points will also result in additional engineering time.

0 100000 200000 300000 400000 500000 600000

Number of EST patterns

Figure 8: ASIC4 logic BIST grades versus patterns.

Figure 9 Design flow with logic BIST.

An assessment of the success of current implementa-

tions of logic BIST in the designs is presented in Table V.
Most of the goals were achieved. However, the run time for
the design compile is too long and work is underway to
address this through design partitioning and distributed
processing. IkosTMsimulation times are also over the goal,
but in retrospect this goal was impractical. Future simula-
tions will mostly be partial simulations as is our current
practice with ATPG pattern IkosTMsimulations. Confi-

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 dence in using logic BIST is now high enough that it will these designs with low area overhead and high stuck-at
actually be used in new designs. fault coverage. The test application time as well as the fault
simulation time were shown to be low. Finally, with the use
of automation, it has been possible to implement logic
-
- Goal Description
Eliminate tester memory and frequency
Status BIST without impacting the product schedule.
The proposed scheme, together with the implementa-
G1 Achieved tion experience reported, show that logic BIST is a viable
- limitations and acceptable test solution for large industrial designs.
G2 I Provides at-speed scan testing I Achieved I Future work will report on practical issues of implementing
- Works for 1-2 million gate designs , .
G3 Expected multi-frequency at-speed logic BIST as well as measuring
the effectiveness of logic BIST test.
G4 BIST stuck-at grade 2 95%
- Achieved
G5 Logic BIST area 5 2% of logic
- Achieved ACKNOWLEDGEMENTS
G6 Silicon BIST run time c 1sec Achieved
The authors would like to thank The0 Powell and the
G7 Effort < 2 person month per design Expected
MOS design center engineers of Texas Instruments, as well
G8 Ability to use ATPG or logic BIST Achieved as Ian Burgess, Ralph Sanchez, and Kelly Scott of Mentor
G9 Minimal impact on design methodology Achieved Graphics, for their contributions and support.
G10 Automation of the logic BIST flow Achieved
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B. Bottoms, “The Third Millennium’s Test
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I 1 1 J E. J. McCluskey, “Built-In Self Test Techniques”,
IEEE Design &Test of Computers, pp. 21-28, Vol. 2,
No. 2, April 1985.
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