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UNIT – IV
FIELD EFFECT TRANSISTORS

FET is a semiconductor device like a BJT which can be used as an amplifier or switch. The Field
Effect Transistor is a semiconductor device which depends for its operation on the control of current
by an electric field. Hence, the name FET.
The field-effect transistor (FET) is a three-terminal device like BJT used for a variety of
applications that match, to a large extent, those of the BJT transistor. But the principle operation of
FET is completely different from BJT.
The field-effect transistor (FET) is a three-terminal device. The 3 terminals of FET are:
1. Gate ,
2. Drain &
3. Source.
The block diagram of FET & BJT is shown in figure below for comparison.

Figure: Current controlling elements for FET & BJT (a) Current-controlled and (b) voltage-controlled
amplifiers.

FET: Voltage controlled device

 As shown in figure above, in BJT the output current, IC is controlled by the base current IB.
Hence BJT is a current controlled device.
 In FET, the voltage applied between gate and source (VGS) controls the drain current, ID. Hence
FET is a voltage controlled device.
 Since the output current flow is controlled by an electric field (voltage) set up in the device by
an externally applied voltage between gate and source terminals. Hence the name field effect
transistors.

FET: Unipolar device

 BJT is a bipolar device, because the current is carried by both electrons and holes. But in FET,
current is carried by only one type of charge carriers, either electrons or holes. Hence FET is
called unipolar device.

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Classification of FETs:
Based on the construction, FET can be classified into 2 types. They are:

JFET classification:

JFET is of 2 types depending upon the type of channel / bar used or depending on the majority Charge
carriers.

 N – Channel JFET &

 P – Channel JFET.

 If N – type semiconductor bar is used to manufacture the FET, it is N – channel JFET.

 If P – type semiconductor bar is used to manufacture the FET, it is P – channel JFET.
 Ohmic contacts are made to the two ends of a semiconductors bar of n-type or p-type
semiconductor. Current is caused to flow along the length of the bar, because of the voltage
supply connected between the ends.
 If it is n - channel JFET, the current is due to electrons only and if it is p-channel JFET, the
current is due to holes only.
The three lead of the device are:
1. Gate,
2. Drain &
3. Source.
These leads are similar to 1. Base 2. Collector 3. Emitter of BJT respectively.

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N-Channel JFET:
The structure and symbol of a N – channel JFET is shown in figure below.

 The arrow mark at the gate indicates the direction of current if the Gate source junction is
forward biased.
 On both sides of the n - type bar heavily doped (p+) region of acceptor impurities have been
formed by diffusion. These heavily doped P+ regions on either side are joined together to form
Gates (G).
 The top of the N – channel is connected through an ohmic contact to a terminal called as drain
(D), where as the lower end of the same material is connected through an ohmic contact to a
terminal called source (S).
 Immediately after the P+ region is diffused into the N – channel, they behave like an PN
junction diode in un – biased state and the depletion layers are formed about P+ region.
Source (S):
The source (S) is the terminal connected to the negative pole of the battery. Electronics which
are the majority carriers in the N-type bar enter the bar through this terminal.
Drain (D):
The drain (D) is the terminal is connected to the positive pole of the battery. The majority
carriers leave the bar through this terminal.
Gate (G):
Heavily doped P-type silicon is diffused on both sides of the N-type silicon bar by which PN
junctions are formed. These layers are joined together are called Gate (G).
Channel:
The region of N-type bar between the depletion regions is called the Channel. Majority
carriers move from the source to drain when a potential difference VDS is applied between the source
and drain.
Substrate or shield:
It is to protect the FET from the affect of electromagnetic fields outside the FET.

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UN – biased N – channel JFET:

In absence of any applied voltage, JFET has gate channel junction under no bias conditions,
the result is a depletion region at each junction as shown in figure below.

 The above depletion region between P+ and n – channel region is same as depletion region of
a diode under no bias conditions.
 Depletion region is the region which does not have any free charge carriers and therefore it
does not support conduction through the region. And no current flows through the region
under the absence of any applied voltage.
i.e., VGS = 0 & VDS = 0;
Working principle / operation of N – channel JFET:
Consider the circuit shown in figure below.

Drain is biased positively with respect to source & gate is biased negatively with respect to source.
(i) When VGS = 0V & VDS = 0V:
 When VGS = 0V & VDS = 0V i.e., when no voltage is applied between drain and source
and gate and source, then the thickness of depletion region at the PN junction is
uniform throughout the channel region as shown in figure above.

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(ii) When VGS = 0V & VDS > 0V i.e., some positive voltage is applied between drain and
source:
 When VGS = 0V & some positive voltage is applied between drain and source VDS .
 When VDS > 0V, the majority carriers (electrons) flow through the N–
Channel from source to drain. This makes the drain current to flow from the drain
towards the source.
 The path of charge flow clearly shows that the drain and source currents are
equivalent (i.e ID = IS)
 It is important to note that the depletion region is wider near the top of both P –
type materials as shown in figure below.

 The reason for the change in width of the depletion region can be best explained through the
help of the figure shown below.

 Assuming a uniform resistance in the n-channel, the resistance of the channel can be broken
down to the divisions appearing as shown in Fig. above.
 The current ID due to the applied voltage VDS will establish the voltage levels or drops through
the channel as indicated in figure above.

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 The result is that the upper region of the p-type material will be reverse biased by about 1.5
V, with the lower region only reverse-biased by 0.5 V.
 Recall from the discussion of the diode operation that the greater the applied reverse bias,
the wider the depletion region—hence the distribution of the depletion region as shown in
Figure above.
 As the p-n junction is reverse-biased for the length of the channel, it results in a gate current
of zero amperes i.e., IG = 0V as shown in the same figure above.
 The IG = 0 A is an important characteristic of the JFET.
 As the voltage VDS is increased from 0 to a few volts, the current will increase based on Ohm’s
law and the plot of ID versus VDS will appear as shown in Figure.

 The relative straightness of the plot shows that for the region of low values of VDS, the
resistance is essentially constant.
 As VDS increases and approaches a level referred to as VP in as shown in Figure above, the
depletion regions of Figure will widen, causing a noticeable reduction in the channel width.
The reduced path of conduction causes the resistance to increase and the current maintains
almost constant level, even though the voltage VDS is varied beyond VP as shown in figure
below.

 The more horizontal the curve, the higher the resistance, showing that the resistance is
approaching “infinite” ohms in the horizontal region.
 If VDS is increased to a level where it appears that the two depletion regions would “touch” as
shown in Figure, a condition called as pinch-off will results.
 The level of VDS, that establishes the pinch – off condition is called as the pinch-off voltage
and is denoted by VP as shown in Figure above.

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 ID maintains a saturation level defined as IDSS for VDS = VP. In reality a very small channel still
exists, with a current of very high density.
Note:
 IDSS is the maximum drain current for a JFET and is defined by the conditions, V GS = 0V & VDS >
| VP |.
(iii)When VGS < 0V:
 The voltage from gate to source, denoted VGS, is the controlling voltage of the JFET. Similar to
various curves for IC versus VCE were established for different levels of IB for the BJT transistor,
curves of ID versus VDS for various levels of VGS can be developed for the JFET.
 For the n-channel device the controlling voltage VGS is made more and more negative from its
VGS = 0 V level.
 In other words, the gate terminal will be set at lower and lower potential levels as compared
to the source.
 The negative voltage of -1 V applied between the gate and source terminals increases the
depletion region around the PN junction when compared to VGS = 0 V as shown in figure
below.

Figure: Application of negative voltage to the gate of a JFET & VDS > 0V.

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CHARACTERISTICS OF N-CHANNEL JFET

The family of curves that shows the relation between current and voltage are known as characteristic
curves.There are two important characteristics of a JFET.
1) Drain or VI Characteristics
2) Transfer characteristics
1. Drain Characteristics:-
Drain characteristics shows the relation between the drain to source voltage Vds and drain current
Id. In order to explain typical drain characteristics let us consider the curve with Vgs= 0.V.
1) When Vds is applied and it is increasing the drain current ID also increases linearly up to knee point.
2) This shows that FET behaves like an ordinary resistor.This region is called as ohmic region.
3) ID increases with increase in drain to source voltage. Here the drain current is increased slowly as
compared to ohmic region.

4) It is because of the fact that there is an increase in VDS .This in turn increases the reverse bias
voltage across the gate source junction .As a result of this depletion region grows in size thereby
reducing the effective width of the channel.
5) All the drain to source voltage corresponding to point the channel width is reduced to a minimum
value and is known as pinch off.The drain to source voltage at which channel pinch off occurs is called
pinch off voltage(Vp).
PINCH OFF Region:-
1) This is the region shown by the curve as saturation region.
2) It is also called as saturation region or constant current region. Because of the channel is occupied
with depletion region , the depletion region is more towards the drain and less towards the source,
so the channel is limited, with this only limited number of carriers are only allowed to cross this
channel from source drain causing a current that is constant in this region. To use FET as an amplifier
it is operated in this saturation region.
3) In this drain current remains constant at its maximum value IDSS.
4) The drain current in the pinch off region depends upon the gate to source voltage and is
given by the relation
Id =Idss [1-Vgs/Vp]2
This is known as shokley’s relation.

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BREAKDOWN REGION:-
1) The region is shown by the curve .In this region, the drain current increases rapidly as the drain to
source voltage is increased.
2) It is because of the gate to source junction due to avalanche effect.
3) The avalanche break down occurs at progressively lower value of VDS because the reverse bias
gate voltage adds to the drain voltage thereby increasing effective voltage across the gate junction
This causes
1. The maximum saturation drain current is smaller
2. The ohmic region portion decreased
4) It is important to note that the maximum voltage VDS which can be applied to FET is the lowest
voltage which causes available break down.
3. TRANSFER CHARACTERISTICS:-
These curves shows the relationship between drain current ID and gate to source voltage
VGS for different values of VDS.
1) First adjust the drain to source voltage to some suitable value , then increase the gate to source
voltage in small suitable value.
2) Plot the graph between gate to source voltage along the horizontal axis and current ID on the
vertical axis. We shall obtain a curve like this.
3) As we know that if Vgs is more negative curves drain current to reduce . where Vgs is made
sufficiently negative, Id is reduced to zero. This is caused by the widening of the depletion region to
a point where it is completely closes the channel. The value of Vgs at the cutoff point is designed as
Vgsoff

4) The upper end of the curve as shown by the drain current value is equal to Idss that is when Vgs =
0 the drain current is maximum.
5) While the lower end is indicated by a voltage equal to Vgsoff
6) If Vgs continuously increasing , the channel width is reduced , then Id =0
7) It may be noted that curve is part of the parabola; it may be expressed as
Id=Idss[1-Vgs/Vgsoff]2

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FET AS A VOLTAGE –VARIABLE RESISTOR (VVR):

FET is operated in the constant current portion of its output characteristics for the linear applications
.In the region before pinch off , where Vds is small the drain to source resistance rd can be controlled
by the bias voltage Vgs.The FET is useful as a voltage variable resistor (VVR) or Voltage Dependent
resistor.
In JFET the drain source conductance gd = Id/Vds for small values of Vds which may be
expressed as gd = gdo [ 1-( VgsVp)1/2 ] where gdo is the value of drain conductance when the bias
voltage Vgs is zero.Small signal FET drain resistance rd varies with applied gate voltage Vgs and FET
act like a VARIABLE PASSIVE RESISTOR.
When VDS < VP, when VGS is constant. i.e., FET acts as a resistor.In this region FET is used as a Voltage
controlled resistor. Or Voltage variable resistor. Or Voltage dependant resistor

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IMPORTANT RELATIONSHIPS:

P – CHANNEL JFET:

The P-channel Junction Field Effect Transistor operates the same as the N-channel above, with the
following exceptions:

1. Channel current is positive due to holes,

2. The polarity of the biasing voltage needs to be reversed.

Applications of JFET:

1. FET is used as a buffer in measuring instruments, receivers since it has high input impedance
and low output impedance.
2. FET’s are used in Radio Frequency amplifiers in FM (Frequency Mode) tuners and
communication equipment for the low noise level.
3. Since the input capacitance is low, FET’s are used in cascade amplifiers in measuring and test
equipments.
4. It can be used as a voltage controlled resistance because resistivity of the channel varies with
VDS.
5. FET’s are used in mixer circuits in FM and TV receivers, and communication equipments
because inter modulation distortion is low.
6. It is used in oscillator circuits because frequency drift is low.
7. As the coupling capacitor is small, FET’s are used in low frequency amplifiers in hearing aids
and inductive transducers.
8. FET’s are used in digital circuits in computers, LSD and a memory circuit because of it is small
size.
9. Junction field-effect transistor (JFET), is based on a PN junction structure and finds
application particularly in analog and RF circuit design
10. JFETs make good digital and analog switches. Off resistance is very high.

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MOSFET (METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR)

MOSFET CLASSIFICATION:

DEPLETION-TYPE MOSFET:
The channel between source and drain is established at the time of manufacturing in
depletion – type - MOSFETs.
Basic Construction:
The basic construction of the n-channel depletion -type MOSFET is shown in figure below.
 A slab/Bar of p-type material (lightly doped) is formed from a silicon base and is called as the
substrate. Two heavily doped n+ regions are diffused in a lightly doped substrate of p-type
material made of silicon. One n+ region is called source ‘S’ & the other n+ region is called Drain
‘D’.
 In addition to the above constructions, an n – channel is diffused is diffused between source
and drain as shown in figure below.
 The gate is also connected to a metal contact surface but remains insulated from the n-
channel by a very thin silicon dioxide (SiO2) layer. SiO2 is a particular type of insulator referred
to as a dielectric that sets up opposing (as revealed by the prefix di) electric fields within the
dielectric when exposed to an externally applied field.

 There is no direct electrical connection between the gate terminal and the channel of a
MOSFET as shown in figure above.

Note: It is the insulating layer of SiO2 in the MOSFET construction that accounts for the very
desirable high input impedance of the device.

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The circuit symbols for an n – channel and p – channel depletion MOSFET are shown in figure below.

Working:
As channel is established at the time of manufacturing,
(i) When VGS = 0V & VDS > 0V:

 When VGS = 0V & VDS > 0V i.e., drain to source voltage at some positive voltage;
with respect to source, the electrons (majority charge carriers) flow through the n
– channel from source to drain. Therefore the conventional current direction I D
flows through the channel from drain to source as shown in figure below.

(ii) When VGS < 0V (i.e., VGS is made negative):

 If gate voltage VGS is made negative with respect to source i.e., VGS = - 1 V. The negative
voltage at the gate repels the electrons toward the p-type substrate (like charges repel)
and attract holes from the p-type substrate (opposite charges attract) as shown in Figure
below.

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 Depending on the magnitude of the negative bias established by VGS, recombination

between electrons and holes will occur that will reduce the number of free electrons in
the n-channel available for conduction.
 The more negative the bias or voltage applied at the gate terminal, the higher the rate of
recombination. So, there will be less number of electrons in the channel after
recombination to take part in conduction process. And the resulting level of drain current
ID, is therefore reduced with increasing negative bias for VGS as shown in Figure below.
 For VGS = - 1 V, - 2 V, and so on, to the pinch-off level of - 6 V. The resulting levels of drain
current and the plotting of the transfer curve proceeds exactly as described for the JFET.

Figure: Transfer characteristics of an n – channel Depletion MOSFET with IDSS = 10 mA & VP = -4 V.

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Transfer characteristics:

Figure: Drain and transfer characteristics for an n-channel depletion-type MOSFET.

 For positive values of VGS, the gate will draw additional electrons i.e., minority carriers (free
carriers) from the P – type substrate due to reverse leakage current and establishes new
carriers through the collision and increases the number of free electrons in the channel. So,
as the number of free electrons or carriers in the channel increases due to applied positive
voltage at gate, the level of drain current ID through the channel also increases as shown in
figure above.
 As the gate to source voltage continues to increase in the positive direction, the drain current
level will increase at rapid rate as shown in figure above.
 And if we further increase the positive voltage at VGS, the reverse bias increases and leads to
breakdown for a particular VGS and a maximum current flows which damages the MOSFET.
 As shown in figure above, the application of a positive gate-to-source voltage has “enhanced”
the level of free carriers in the channel compared to that of the gate to source voltage with
VGS = 0 V. For this reason the region of positive gate voltages on the drain or transfer
characteristics is often referred to as the enhancement region, with the region between cutoff
and the saturation level of IDSS referred to as the depletion region.
P - Channel Depletion-Type MOSFET:
The construction of a p-channel depletion-type MOSFET is exactly the reverse of n – channel
depletion MOSFET as shown in figure below.
That is, there is now an n-type substrate and a p-type channel, as shown in Figure.

Figure: p-Channel depletion-type MOSFET

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 The terminals remain same as n – channel depletion MOSFET, but all the voltage polarities
and the current directions are reversed, as shown in the same figure above.
 The drain characteristics would appear exactly as n – channel depletion MOSFET, but with
VDS having negative values, ID having positive values as indicated (since the defined direction
is now reversed), and VGS having the opposite polarities as shown in Figure below (c).

Figure: p-Channel depletion-type MOSFET with IDSS _ 6 mA and VP__6 V.

 The reversal in VGS will result in a mirror image (about the ID axis) for the transfer
characteristics as shown in Figure (b).
 In other words, the drain current will increase from cutoff at VGS = VP in the positive VGS region
to IDSS and then continue to increase for increasingly negative values of VGS.
 Shockley’s equation is still applicable and requires simply placing the correct sign for both VGS
and VP in the equation.
ENHANCEMENT-TYPE MOSFET
The symbols for n – channel & p – channel enhancement MOSFET are shown in figure below.

Basic Construction:
The basic construction of the n-channel enhancement-type MOSFET is shown in figure below.
 A slab/Bar of p-type material (lightly doped) is formed from a silicon base and is called as the
substrate. Two heavily doped n+ regions are diffused in a lightly doped substrate of p-type
material made of silicon. One n+ region is called source ‘S’ & the other n+ region is called Drain
‘D’.

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 They are separated by 1 milli inch (10 -3 inch). A thin insulating layer of SiO2 is grown over the
surface of the substrate and holes are cut into the oxide layer below the n+ regions to provide
contacts for the source and drain regions in the diffused areas.
 Then a thin layer of metal aluminum is formed over the layer of SiO2. Thus the metal layer
covers the entire channel region and it forms the gate ‘G’.
 The metal area of gate, in combination with insulating oxide layer of SiO 2 and semiconductor
channel forms the parallel plate capacitor, when VGS = 0V & VDS = 0V
 The device is called insulated gate FET because of insulating layer of SiO2. This layer gives high
impedance for the MOSFET.
 As there is no continuous channel in an enhancement mode MOSFET as in the depletion-type
MOSFET, the substrate is sometimes internally connected to the source terminal, while in
other cases a fourth lead is made available for external control of its potential level.
 The absence of a channel between the two n-doped regions is the primary difference between
the construction of depletion-type and enhancement-type MOSFETs.
 SiO2 layer is still present to isolate the gate metallic platform from the region between the
drain and source, but now it is simply separated from the p-type material.
The construction of an enhancement-type MOSFET is quite similar to that of the depletion-type
MOSFET, except for the absence of a channel between the drain and source terminals as shown
above.
Basic Operation and Characteristics
1. When VGS = OV & VDS = 0V:
 The MOSFET acts as a capacitor, having insulating material as oxide layer (SiO2) in
between the metal contact of gate and the lightly doped in P - substrate material in n
– channel enhancement MOSFET and the metal contact for gate and lightly doped
substrate of silicon acts as parallel plates. And the current form drain o source region
is 0 Amperes.
2. When VGS = 0V & and a voltage applied between the drain and source of the device as shown
in figure below.

 With VGS = 0 V & VDS > 0 V (some positive voltage); and substrate (SS) directly
connected to the source, there are two reverse-biased p-n junctions between the n-
doped regions and the p-substrate to oppose any flow of carriers between drain and
source as shown in figure above.

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 Due to the absence of an n-channel ,between source and drain conduction does not
takes place between drain and source and the current is zero amperes
Note: For VGS = 0 V & VDS = 0 V; VGS = 0 V & VDS > 0 V, the enhancement MOSFET is quite
different from the depletion- type MOSFET and JFET where ID = IDSS. The enhancement mode
MOSFET behave as capacitor and does not conduct (ID = 0A).
3. When VGS > 0V & VDS > 0V:
 When both VDS and VGS have been set at some positive voltage greater than 0 V,
making the drain and gate at a positive potential with respect to the source. The
positive potential applied at the gate will repel the holes (since like charges repel) in
the p-substrate along the edge of the SiO2 layer to leave the area and enter deeper
regions of the p-substrate, as shown in the figure below. The result is a depletion
region near the SiO2 insulating layer void of holes.

 If the gate voltage VGS is further increased, so, it attracts the electrons which are minority
charge carriers from P – substrate to the positive gate and accumulate in the region near the
surface of the SiO2 layer and forms the inversion layer beneath the SiO2 layer of gate terminal
as shown in figure above.
 The SiO2 layer and its insulating qualities will prevent the negative carriers from being
absorbed at the gate terminal.

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Threshold voltage (V Th):

The minimum value of voltage VGS, for which the channel is established and creates a path for
conduction between source and drain, is called Threshold voltage (V T).
 As VGS is increased beyond V Th (Threshold voltage), the density of free carriers in the induced
channel will increase resulting in an increased level of drain current.
 If VGS = constant (> V Th), and VDS is increased then the drain current will reach a saturation
level as occurred for JFET.
The leveling of drain current ID, is due to pinching off process by the narrower channel at the drain
end of the channel as shown in figure below.

Applying KVL to terminal voltages of MOSFET of figure above, we get

VDS – VDG – VGS = 0
VDG = VDS – VGS (VTh)
From equation above,
 If VGS (VTh) = constant (> V Th), and VDS is increased, at some value of VDS, the gate voltage will
become less positive with respect to drain and causes a reduction in effective channel width.
 As a result, the channel is pinched – off and saturation condition will be established like JFET
and depletion-type MOSFET.
 In other words, any further increase in VDS at the fixed value of VGS will not affect the
saturation level of ID until breakdown condition occurs.
 The drain characteristics of Figure below shows that for the device of figure above with VGS
= 8 V, saturation occurs at a level of VDS = 6 V.

The saturation level for VDS is related to the level of applied VGS by

 As the positive voltage on gate increases, the induced negative charge in the semiconductor
increases. Hence the conduction increases and current flows from source to drain through
the induced channel. Thus the drain current is enhanced by the applied positive gate voltage
as shown in figure below.

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Drain characteristics for an N – channel enhancement type MOSFET:

Transfer characteristics for an N – channel enhancement type MOSFET:

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FET Biasing Methods

Unlike BJTs, thermal runaway does not occur with FETs. However, the wide differences in maximum
and minimum transfer characteristics make ID levels unpredictable with simple fixed-gate bias
voltage. To obtain reasonable limits on quiescent drain currents ID and drain-source voltage VDS,
source resistor and potential divider bias techniques must be used. With few exceptions, MOSFET
bias circuits are similar to those used for JFETs. Various FET biasing circuits are discussed below.
FIXED BIAS

FET has such a high input impedance that no gate current flows and the dc voltage of the gate set by
a voltage divider or a fixed battery voltage is not affected or loaded by the FET.
Fixed dc bias is obtained using a battery VQG. This battery ensures that the gate is always
negative with respect to source and no current flows through resistor RG and gate terminal that is IG
=0. The battery provides a voltage VGS to bias the N-channel JFET, but no resulting current is drawn
from the battery VGG. Resistor RG is included to allow any ac signal applied through capacitor C to
develop across RG. While any ac signal will develop across RG, the dc voltage drop across RG is equal
to IG RG i.e. 0 volt.
The gate-source voltage VGS is then
VGS = - VG – VS = – VGG – 0 = – VGG
The drain -source current ID is then fixed by the gate-source voltage as determined by
equation.This current then causes a voltage drop across the drain resistor RD and is given as

VRD =ID RD
and output voltage, Vout = VDD – ID RD

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SELF-BIAS
This is the most common method for biasing a JFET. Self-bias circuit for N-channel JFET is shown in
figure.

Since no gate current flows through the reverse-biased gate-source, the gate current IG =0 and,
therefore,vG = iG RG = 0 With a drain current ID the voltage at the S is Vs= ID Rs
voltage drop across resistance Rs provides the biasing voltage VGg and no external source is required
for biasing and this is the reason that it is called self-biasing.The operating point (i.e zero signal ID
and VDS) can easily be determined from equation and equation given below
VDS = VDD – ID (RD + RS)
Thus dc conditions of JFET amplifier are fully specified. Self-biasing of a JFET stabilizes its quiescent
operating point against any change in its parameters like transconductance. Let the given JFET be
replaced by another JFET having the double conductance then drain current will also try to be double
but since any increase in voltage drop across Rs, therefore, gate-source voltage, VGS becomes more
negative and thus increase in drain current is reduced.
POTENTIAL-DIVIDER BIASING
A slightly modified form of dc bias is provided by the circuit shown in figure. The resistors RGl and
RG2 form a potential divider across drain supply VDD. The voltage V2 across RG2 provides the
necessary bias. The additional gate resistor RGl from gate to supply voltage facilitates in larger
adjustment of the dc bias point and permits use of larger valued RS.

G.Balakrishna,ECE Dept,SITAMS
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The gate is reverse biased so that IG = 0 and gate voltage

VG =V2 = (VDD/R G1 + R G2 ) *RG2
VGS = VG – VS = VG - ID RS
The circuit is so designed that ID, Rs is greater than VD so that VGS is negative. This provides correct
bias voltage.
The operating point can be determined as
ID = (V2 – VGS)/ RS
And
VDS = VDD – ID (RD + RS)
JFET model:
Small signal model of JFET / Low frequency equivalent circuit:
The JFET parameters are the major components of low frequency small signal model of JFET.
We know that,
The change in drain current ID, due to change in gate to source voltage, VGS is given by
transconductance factor gm. i.e.,

= ∆ ID = gm x VGS [ ∵ from above equation ]

 The relation of ID and VGS is included as current source gm x VGS connected from drain (D) to
source (S).
 The drain resistance rd, determines the output impedance Z0 of JFET.
 The input impedance is represented by open circuit at its input terminals. Since gate current
IG is ‘0’.
JFET low frequency A.C equivalent circuit for N – channel JFET (Current Source model):

Figure: JFET low frequency A.C equivalent circuit for N – channel JFET.

Approximate A.C equivalent circuit for N – channel JFET:

G.Balakrishna,ECE Dept,SITAMS
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Note: The lower subscript represent A.C levels.

 If the value of external drain resistance RD is very small as compared to value of output
impedance (rd), it is possible to replace rd by open circuit. This gives approximate A.C
equivalent circuit of JFET amplifier.
Problems:

1. When a reverse gate voltage is 12V, gate current is 1mA. Determine the resistance between
gate & source.

2. When reverse Gate voltage changes from 4.0 to 3.9V, the drain current changes from 1.3 to
1.6 mA. Find the Trans conductance.

Solution:

3. A FET has a drain current of 4mA. If IDSS = 8mA and VGS off = -6V. Find values of VGS
and VP.

G.Balakrishna,ECE Dept,SITAMS
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1. The readings obtained from a JFET are as follows: -

Drain to source voltage (volts) = 5 12 12

Gate to source voltage (volts) = 0 0 -0.25
Drain current Id (mA) = 8 8.2 7.5

Determine (i) AC drain resistance (ii) Trans. Conductance (iii) Amplification Factor
SOLUTION:

G.Balakrishna,ECE Dept,SITAMS