Chandana K N et al, / (IJCSIT) International Journal of Computer Science and Information Technologies, Vol.

6 (3) , 2015, 2717-2719

Link Initialization and Training in MAC Layer of

PCIe 3.0
Chandana K N , Karunavathi R K
Department of E&CE, Bangalore Institute of Technology
Bangalore, Karnataka, India

Abstract— The serial protocols like PCI Express and USB relevant state transitions so that there can be multiple state
have evolved over the years to provide very high operating transitions conditions to transition to the same next state.
speeds and throughput. This evolution has resulted in their For some of the sub-states, there are multiple state
physical layer protocol becoming very complex. One of the transition paths that lead to different next states. To trigger
most essential processes at physical layer is link initialization
and training process. In the PCI Express devices, this process
all the required state transitions and transition conditions,
establishes many important tasks such as link width we use a mixture of directed and constrained random
negotiation, link data rate negotiation, bit lock per lane, stimulus generation. As each and every statement in the
symbol lock/block alignment per lane, etc. All these functions PCIe Base Specification description of LTSSM requires
are accomplished by Link Training & Status State Machine attention, we create a detailed coverage for all sub-states
(LTSSM), which observes the stimulus from remote link that includes all state transition paths, transition
partner as well as the current state of the link, and responds reasons/conditions, transmit rules, stimulus etc.
accordingly.
II. LITERATURE REVIEW
Keywords—Encoding, Link Training and Status State All In the world of communication protocols, PCI-
Machine, Ordered Sets, PCIe 3.0, Scrambling, Verification Express presents throughput in 2.5 GT/s, 5.0 GT/s and 8.0
Introduction
GT/s. It is important to not forget the purpose of each
I. INTRODUCTION protocol. PCIe is a high-speed serial computer expansion
bus standard designed to replace the older PCI, PCI-X, and
The PCIe 3.0 architecture utilizes very efficient and AGP bus standards. PCIe has numerous improvements over
productive algorithms for maintaining reliable link, highly the older standards, including higher maximum system bus
optimized power consumption and extremely fast and throughput, lower I/O pin count and smaller physical
flawless data transfer rate. The Link Training Status State footprint, better performance scaling for bus devices, a
Machine has been employed as the foremost workhorse in more detailed error detection and reporting mechanism and
these regards. Its functions and provisions contribute native hot-plug functionality. More recent revisions of the
matchlessly towards the super speed high class PCIe standard provide hardware support for I/O
performance. The LTSSM tunes and trains the PCIe link for virtualization [1],[2],[3],[4].
reliable data transfer. It also implements various algorithms As the SuperSpeed USB 3.0 protocols are intended for
for link’s reliability maintenance and is also responsible to dual simplex transmission lines, for the sake of parallel
recover the link from any errors as may arise. It also plays transactions, there is an absolute need of having the
key role in power management by greatly reducing link’s architecture which supports such protocols. [5] [6] have
power consumption and nullifying any conditions that developed a fully synthezied LTSSM (Link Layer and
waste power. The LTSSM also performs operations for Transition State Machine) and also interfaced it with
making the link ready for data transaction in the very previously developed MAC layer. The layered architecture
beginning when the device is plugged in. Hence LTSSM is of USB 3.0 communication protocols itself turned out
the Data Flow GatewayControl for the device. The work helpful in structuring verification effort to enhance it.
also includes the development and verification of MAC [7] describes a method to implement the data link layer
Layer of PCIe 3.0 device. The LTSSM communicate and of the PCIe 3.0. The data link layer is involved in the
co-ordinates with almost all the layers of the device namely exchange of packets at the DLL level with a state machine
the PHY, the MAC, the link layer and also the master for flow control and initialization.
controller. A novel Multi-mode Serial Link Controller (MMSLC)
We use a PCI Express LTSSM whitebox reference for logic physical layer (PHY) and data link layer (DLL) of
model, which is a part of the bigger UVM-based testbench USB 3.0, PCle 2.0 and SATA 3.0 is introduced in [8]. This
environment. The LTSSM reference model observes the approach exploits the relationship between protocols'
same physical layer traffic as the DUT, behaves as per the similarity with circuit flexibility and its real-time
PCI Express Base Specification and also predicts the requirements with effective circuit area usage, as verified in
possible state transitions. As opposed to the Black Box this paper. Our results show that this architecture is capable
tetsbench which has no idea about the state of DUT’s of achieving the high-speed requirements of around
internal blocks, this model is aware of DUT’s LTSSM state 500MHz symbol rate for serial link protocols and realize
and values of useful LTSSM parameters. area reduction over conventional link controllers running
The PCI Express defines the state behaviour and each protocol individually.

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 Chandana K N et al, / (IJCSIT) International Journal of Computer Science and Information Technologies, Vol. 6 (3) , 2015, 2717-2719

With the evolution of modern verification configured Link and Lane number as well as the
methodologies, system-level verification using constrained- previously supported data rate(s).Recovery allows a
random stimulus is a high priority, especially in very large configured Link to change the data rate of operation if
communication applications. A key goal to address is desired, re-establish bit lock, Symbol lock or Block
providing fast, effective test coverage. In order to generate alignment, and Lane-to-Lane de-skew.
stimulus automatically to cover all coverage bins more
quickly in the verification process, especially in very large
communication applications, a novel method which
combines the benefits of GA and coverage-driven
verification methodology is proposed. By analyzing the real
time coverage results from the simulation and thereafter
intelligently modifying the corresponding stimulus, this
novel method iteratively improves coverage. As a result, the
GA can more effectively generate stimulus. The
experimental results from both a C-based testbench and a
real application (PCIe system) prove that the proposed GA
method can streamline the verification effort and sharply
reduce simulation time to achieve thorough coverage [10].
The SystemVerilog Language Reference Manual
and Universal Verification Methodology User’s Guide has
been referred wherever required for language constructs
[11][12].

III. LINK INITIALIZATION AND TRAINING

The architecture of PCIe is classified in terms of three
discrete logical layers: the Transaction Layer, the Data Link
Layer, and the Physical Layer. Link Initialization and
Training is a Physical Layer control process that configures Fig 1 LTSSM Location
and initializes a device’s Physical Layer, port and
associated Link so that normal packet traffic can proceed on 5. L0 L0 is the normal operational state where data and
the Link. This process is automatically initialized after reset control packets can be transmitted and received. All
without any software involvement. A sub-set of Link re- power management states are entered from this state.
training is initiated automatically as a result of wake up 6. L0s L0s is intended as a power savings state. L0s
event from a low power mode or due to an error condition allows a Link to quickly enter and recover from a
that render the Link inoperable. The location of Link power conservation state without going through
Training and Status State Machine (LTSSM) is the Physical Recovery.
Layer sub-block responsible for the Link Initialization and 7. L1 L1 is intended as a power savings state. The L1
Training process as shown in Fig 3-1. state allows an additional power savings over L0s at
the cost of additional resume latency.
The top level states of the LTSSM are shown in Fig 3- 8. L2 Power can be aggressively conserved in L2. Most
2. Each state consists if sub-states, that taken together, of the Transmitter and Receiver may be shutOff. Main
comprise that state. The first LTSSM state that is entered power and clocks are not guaranteed, but Aux power is
after exiting fundamental reset or Hot reset is the Detect available.
State. The LTSSM consists of 11 top level states as briefed 9. Disabled The intent of the Disabled state is to allow a
below: configured Link to be disabled until directed or
Electrical Idle is exited (i.e., due to a hot removal and
1. Detect The purpose of this state is to detect when a far insertion) after entering Disabled.
end termination is present. This state can be entered at 10. Loopback Loopback is intended for test and fault
any time if directed. isolation use. Only the entry and exit behavior is
2. Polling The Port transmits training Ordered Sets and specified, all other details are implementation specific.
responds to the received training Ordered Sets. In this Loopback can operate on either a per Lane or
state, bit lock and Symbol lock are established and configured Link basis.
Lane polarity is configured. 11. Hot Reset A Link can enter Hot Reset if directed by a
3. Configuration In this state, both the Transmitter and higher Layer. A Link can also reach the Hot Reset state
Receiver are sending and receiving data at the by receiving two consecutive TS1 Ordered Sets with
negotiated data rate. The Lanes of a Port configure into the Hot Reset bit asserted.
a Link through a width and Lane negotiation sequence.
4. Recovery In Recovery, both the Transmitter and
Receiver are sending and receiving data using the

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 Chandana K N et al, / (IJCSIT) International Journal of Computer Science and Information Technologies, Vol. 6 (3) , 2015, 2717-2719

descrambled in the MAC agents.

The transmit side of the PIPE agent encodes and
serializes the data packets on to the PIPE interface. The
receive side of the PIPE agent decodes and deserializes the
data packets from the PIPE interface.

V. CONCLUSION
The LTSSM has been designed and verified using
SystemVerilog UVM Methodology. This LTSSM has been
interfaced with the existing MAC Layer and proved
effective use. Following the latest PCIe 3.0 specifications,
the designed LTSSM can easily be hooked up with other
layers. The functionality of LTSSM is also verified, via
simulation, along with integrated MAClayer. The layered
architecture of PCIe 3.0 communication protocols itself
turned out helpful in structuring verification effort to
enhance it. The layers can be verified separately with
minimal overhead in the test development effort.
Fig 2 Main State Diagram for LTSSM
ACKNOWLEDGMENT
IV. VERIFICATION ARCHITECTURE The authors wish to thank Mindtree Limited. This work
The LTSSM has been designed and verified using UVM was supported in part by a grant from Mindtree Limited.
methodology. The verification architecture is as shown in
Fig 4-1 REFERENCES
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