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Verilog HDL Basics Lab Assignments: Lab Work 1. Study of Module Declaration and Module Instantiation Principles

This document outlines 7 lab assignments on Verilog HDL basics. The labs cover module declarations and instantiation, simulation control, port connections, gate-level design, dataflow design, behavioral design, and RTL design. The tasks include writing module definitions, stimulus modules, gate-level descriptions of basic components like latches and adders, and behavioral and RTL level descriptions of counters, decoders and other common circuits. Students are asked to simulate their designs using a simulator and verify the outputs match given test cases.

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Sindhu Rajan
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110 views

Verilog HDL Basics Lab Assignments: Lab Work 1. Study of Module Declaration and Module Instantiation Principles

This document outlines 7 lab assignments on Verilog HDL basics. The labs cover module declarations and instantiation, simulation control, port connections, gate-level design, dataflow design, behavioral design, and RTL design. The tasks include writing module definitions, stimulus modules, gate-level descriptions of basic components like latches and adders, and behavioral and RTL level descriptions of counters, decoders and other common circuits. Students are asked to simulate their designs using a simulator and verify the outputs match given test cases.

Uploaded by

Sindhu Rajan
Copyright
© © All Rights Reserved
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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VERILOG HDL BASICS

LAB ASSIGNMENTS

Lab work 1. Study of Module Declaration and Module Instantiation Principles


Write the module declaration for T Flip-Flop with information input - T, clock input – clk, Q and
Q_bar outputs. Do not care about module internals. Write the Verilog description of 4 –bit
counter instantiating the previously declared TFFs.

Lab work 2. Study of Basic Operations for Simulation Control

Task 1
Practice the following numbers
a) A 4 bit hexadecimal number with 2 least significant bits unknown.
b) Decimal number 299 as a sized 16 bit number.
c) An unsized hex number 1112.

Task 2
Declare the following in VERILOG.
a) A 16 bit vector net data_in.
b) A 8 bit register named data_out
c) An integer called sweep_value;

Task 3
A number contained in a reg variable idata is 4’b1001. Write a statement to display its value on
the screen. Use the system task $display.

Lab work 3. Study of Port Connection Rules


Write the module definition for 1 bit full adder with a and b inputs, cin carry-in input, sum and
cout outputs. Declare a top-level module stimulus and instantiate the full adder. Write the correct
port types in the top-level module.

Lab work 4. Study of Gate-Level Design Principles

Task 1
Write the Verilog description for RS latch using NOR gates. Include delays for 1 unit when
instantiating the NOR gates. Write the stimulus module for the RS latch, using the following
table, and verify output.

set reset qn+1


0 0 qn
0 1 0
1 0 1
1 1 ?

Verilog HDL Basics Lab Assignments Page 1 of 3


Task 2
Write the Verilog description for D latch using NAND gates. Include delays for 1 unit when
instantiating the NAND gates. Write the stimulus module for the D latch, using the following
table, and verify output.

D clk qn+1
0 0 qn
1 0 qn
0 1 0
1 1 1

Task 3
Design a 2 to 1 multiplexer using bufif0 and bufif1 gates.
The delay specification for gates b_1 and b_2 as follows:

Min Typ Max


Rise 1 2 3
Fall 3 4 5
Turnoff 5 6 7

Check the results using VCS for simulations.

Task 4
Write the gate-level description of one-bit full adder. Apply the stimulus and check the results
using VCS simulator.

Lab work 5. Study of Dataflow Design Principles

Task 1
Write the dataflow description of negative edge triggered D Flip Flop with asynchronous clear.
Simulate the design using VCS and verify the simulation results.

Task 2
Design a 4 bit adder with carry lookahead. Use dataflow statements to describe the functionality.
Apply stimulus and check the results by VCS simulations.

Task 3
Write the dataflow description of master-slave JK Flip Flop with low active clear signal. Data
gets latched on positive edge of clock, and the output of the Flip Flop appears on the negative
edge of clock.

Verilog HDL Basics Lab Assignments Page 2 of 3


Task 4
Write the dataflow description for the 4-bit synchronous counter. Use the master-slave JK Flip
Flop to design the counter. Counting is disabled when enable signal is low. Check the
functionality of the counter by VCS simulations.

Lab work 6. Study of Behavioral Design Principles

Task 1
Declare a register called oscillate. Initialize it to 0 and make it toggle very 30 time units. Do not
use always statement. (hint: use the forever loop).

Task 2
Define a function to multiply two 4-bit numbers a and b. The output is an 8-bit value. Invoke the
function by using stimulus and check the simulation results by VCS simulations.

Task 3
Using the wait statement, design a level-sensitive latch that takes clock and d as inputs and q as
output. q = d whenever clock = 1.

Task 4
Define a task to compute the factorial of a 4-bit number. The output is a 32-bit value. The result
is assigned to the output after a delay of 10 time units

Task 5
Design a negative edge-triggered D-flipflop (DFF) with synchronous clear, active high. Use
behavior statement only. Design a clock with a period of 10 units and test the DFF.

Lab work 7. Study of RTL Design Principles

Task 1
Design a 3-to-8 decoder, using a Verilog RTL description. A 3-bit input a[2:0] is provided to the
decoder. The output of the decoder is out [7:0]. The output bit indexed by a[2:0] gets the value 1,
the other bits are 0. Synthesize the decoder, using any technology library available to you. Apply
identical stimulus to the RTL and the gate-level netlist and compare the output.

Task 2
Write the RTL description for 4-bit full adder with carry lookahed. Synthesize the full adder,
using a demo technology library. Apply stimulus to the RTL and the gate-level netlist and
compare the output.

Verilog HDL Basics Lab Assignments Page 3 of 3

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