Sequential Circuits

and
Latches

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 Sequential Logic Circuits

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 Sequential Logic Circuits

Combinational Logic Circuits
− Output is a function of the inputs only.
− Do not have “history”

Sequential Logic Circuits
− Output is a function of the inputs and the
present state.
− Have “history”
− Maintain state information
− Require memory elements
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 Sequential Logic Circuits

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 Basic Memory Elements

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 Basic Memory Elements

Latch
− Clock input is level sensitive.
− Output can change multiple times during a
clock cycle.
− Output changes while clock is active.

Flip Flop
− Clock input is edge sensitive.
− Output can change only once during a clock
cycle.
− Output changes on clock transition.
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 Latch and Flip Flop

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 Basic Memory Elements

Both latches and flip flops use feedback to

achieve “memory”.

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 A Simple Memory Element

A B

(what is the problem with this circuit?)

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 SR Latch

(NOR gate implementation)

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 SR Latch

Qa Qb
Qa

Qb

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 SR Latch

Resetting the SR Latch

(Qa = 0)

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 S = 0, R = 1
SR Latch: S = 0, R = 1
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10

1
R
0

1
S
0

1
Qa ?
0

1
Qb ?
0

Time
Qa = 0
Qb = 1

R = 1 → Qa = 0

S = 0 & Qa = 0 → Qb = 1

Latch is reset.
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 SR Latch

Setting the SR Latch

(Qa = 1)

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 S = 1, R = 0
SR Latch: S = 1, R = 0
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10

1
R
0

1
S
0

1
Qa ?
0

1
Qb ?
0

Time
Qa = 1
Qb = 0

S = 1 → Qb = 0

R = 0 & Qb = 0 → Qa = 1

Latch is set.
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 SR Latch

Storing the value in the SR Latch

(Qa+ = Qa)

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 SR Latch: S = 0, R = 0; Qa = 0
S = 0, R = 0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10

1
R
0

1
S
0

1
Qa ?
0

1
Qa = 0 Qb ?
0

Time
Qa = 0 Qb = 1

S = 0 & Qa = 0 → Qb = 1
Latch stores the

R = 0 & Qb = 1 → Qa = 0 value of Qa

Behavior of latch is consistent.

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 SR Latch: S = 0, R = 0; Qa = 1
S = 0, R = 0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10

1
R
0

1
S
0

1
Qa ?
0

1
Qb ?
0

Time

Qa = 1 Qa = 1
Qb = 0

S = 0 & Qa = 1 → Qb = 0
Latch stores the

R = 0 & Qb = 0 → Qa = 1 value of Qa

Behavior of latch is consistent.

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 SR Latch

The undefined state of the SR Latch

(Qa = Qb = 0)

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 SR Latch: S = 1, R = 1
S = 1, R = 1
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10

1
R
0

1
S
0

1
Qa ?
0

1
Qb ?
0

Time
Qa = 0
Qb = 0

S = 1 → Qb = 0; R = 1 → Qa = 0

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 SR Latch: S = 1, R = 1 S = 1, R = 1
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10

1
R
0

1
S
0

1
Qa ?
0

1
Qb ?
0

Time
Qa = 0
Qb = 0

S = 1 → Qb = 0; R = 1 → Qa = 0

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 SR Latch: The undefined state

What if both S and R transition from 1 to 0

at the same time?

(S = 1 → 0 & R = 1 → 0)

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 SR Latch: The undefined state
S=1→0
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
R=1→0
1
R
0

1
S
0

1
Qa ?
0

1
Qb ?
0

Time
Qa = ?
Qb = ?

If S and R both transition to 0 simultaneously,

− Output is unpredictable
− Dependent on speed of the 2 NOR gates.
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 SR Latch: The undefined state

If the top NOR gate is faster,
− then R = 0 & Qb = 0 → Qa = 1
− and then S = 0 & Qa = 1 → Qb = 0.
− Stores Qa = 1, Qb = 0 (set).

R
Qa

Qb
S

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 SR Latch: The undefined state

If the bottom NOR gate is faster,
− then S = 0 & Qa = 0 → Qb = 1
− and then R = 0 & Qb = 1 → Qa = 0.
− Stores Qa = 0, Qb = 1 (reset).

R
Qa

Qb
S

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 SR Latch

(NAND gate implementation)

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 SR Latch

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 Gated SR Latch

(NAND Gate Implementation)

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 Gated SR Latch

S'

R'

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 Gated SR Latch: State Equation

State Equation: Q+ = S + R'.Q
− Q is the present (or current) state.
− Q+ is the next state.

After the transition of the output Q.
− The next state is a function of the inputs and
the present state.

Inputs: S and R

Present State: Q

− Note: Q is also denoted as Q(t)

− and Q+ is also denoted as Q(t+1).
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 Gated D Latch

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 Gated D Latch

S
S'

R R'

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 Gated D Latch: Clk = 0
Clk = 0

Clk = 0 → S' = R' = 1 Latch stores the

S' = R' = 1 → Q+ = Q value of Q

− Next state = present

state
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 Gated D Latch: Clk = 1
Clk = 1

Clk = 1 → S' = D', R' = D Output (Q) follows

S' = D', R' = D → Q+ = D the input (D)

− Next state = input

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 Gated D Latch

State Equation: Q+ = D
− Q+ is the next state
− D is the input

Eliminates the unstable case

− S' = R' = 0 cannot occur.

S' = R' = 0 is the same as S = R = 1.
− The values of S' and R' are always
complementary when the clock is high (active).
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 Gated D Latch: Issues

Must satisfy setup and hold times.
− Otherwise, the output will be unpredictable or
metastable. tsu
th

Clk

Glitches on D are passed to Q when clock is high.

− Use edge-triggered or Master-Slave D Flip-Flop to
overcome this undesirable behavior.
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 Latches: Symbols

Q Q Q

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 Flip-Flops and Registers

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 Basic Memory Elements

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 Basic Memory Elements

Basic Latch
− A feedback connection of two NOR gates or two
NAND gates, which can store one bit of information.

Can be set to 1 or reset to 0.

Gated Latch
− A basic latch that also includes input gating and a
control input signal (i.e. the clock).

Flip-Flop
− A storage element based on the gated latch principle,
which can have its output state changed only on the
edge of the controlling clock signal.
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 D Flip-Flop

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 D Flip-Flop

Master-Slave Flip-Flop

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 D Flip-Flop: Master-Slave

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 D Flip-Flop: Master-Slave
Master active
Slave active

Clock

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 D Flip-Flop

Positive Edge-triggered Flip-Flop

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 D Flip-Flop: Edge-Triggered

positive edge

negative edge

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 D Flip-Flop: Symbols

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 D Flip-Flop: Function Table

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 Basic Memory Elements

Comparison of Level-Sensitive and Edge-

Triggered Memory Elements

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 D D Q Qa
Gated D Latch
Clock Clk Q Qa

Note that the Latch, D Q Qb

Positive Edge-triggered FF, Positive Edge-triggered
and Negative Edge-triggered FF Q Qb D Flip-Flop
each have a unique symbol

D Q Qc
Negative Edge-triggered
Q Qc D Flip-Flop

(a) Circuit

Clock

Qa Gated D Latch

Qb + Edge-triggered D FF

Qc - Edge-triggered D FF

(b) Timing diagram

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 Flip-Flops
Asynchronous Preset and Clear Signals

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 Asynchronous Preset and Clear
Preset

D
Q

Clock

Clear

(a) Circuit
master slave
Preset

D Q

Clear

(b) Graphical symbol

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 Flip-Flops

JK Flip-Flop

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 JK Flip-Flop

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 JK Flip-Flop

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 Flip-Flops

T Flip-Flop

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 T Flip-Flop

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 T Flip-Flop

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 Flip Flop Excitation Table
• Excitation Table: A table that lists the required
inputs for a given change of state.
• Used to write the next state function.

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 D-FF to a T-FF

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 SR-FF to a D-FF

The desired signal S and R can be obtained as functions of T and current FF

state Q from the Karnaugh maps:

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 Exercise
• What is the function of a D flip-flop, whose
inverted output is connected to its input ?
• Design a circuit to divide input frequency by
2.

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• Consider a circular disk as shown in the figure below with two
sensors mounted X, Y and a blue shade painted on the disk for
an angle of 45 degree. Design a circuit with minimum number of
gates to detect the direction of rotation.

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 Registers

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 Registers

Register
− Consists of N Flip-Flops
− Stores N bits
− Common clock used for all Flip-Flops

Shift Register
− A register that provides the ability to shift its
contents (either left or right).
− Must use Flip-Flops

Either edge-triggered or master-slave
− Cannot use Level-sensitive Gated Latches
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 Registers

4-bit Register

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 Registers

4-bit Register with Parallel Load

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 2-to-1 Multiplexer
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 Registers

4-bit Serial-In Serial-Out Shift Register

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 4-bit SI/SO Shift Register

common clock Edge-triggered

Flip-Flop

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 Registers
Parallel-In Parallel-Out Shift Register

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 Parallel output

Q3 Q2 Q1 Q0

D Q D Q D Q D Q

2-to-1
Multiplexer Q Q Q Q

Serial Clock
input Shift/Load Parallel input

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 Registers

Parallel-In Parallel-Out Bi-directional Shift

Register

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 4-bit PI/PO Bi-directional
Shift Register

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 Counters

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 3-bit Counter: State Diagram

000

111 001

110 010

101 011

100

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 Counters
Asynchronous Counters

(Ripple Counters)

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 4-bit (up) Counter

Let each bit in the counter be represented by the
output of a flip-flop.
Count A3 A2 A1 A0 Count A3 A2 A1 A0
0 0 0 0 0 8 1 0 0 0
1 0 0 0 1 9 1 0 0 1
2 0 0 1 0 10 1 0 1 0
3 0 0 1 1 11 1 0 1 1
4 0 1 0 0 12 1 1 0 0
5 0 1 0 1 13 1 1 0 1
6 0 1 1 0 14 1 1 1 0
7 0 1 1 1 15 1 1 1 1
0 0 0 0 0

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 4-bit (up) Counter: T Flip-Flops

Counter does not Asynchronous

use a common clock. Counter

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 4-bit (up) Counter: T Flip-Flops

Clock

A0

A1

A2

A3

Count 0 1 2 3 4 5 6 7 8

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 4-bit (up) Counter: D Flip-Flops

Counter does not Asynchronous

use a common clock. Counter

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 Counters
Synchronous Counters

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 4-bit (up) Counter

As before, let each bit in the counter be represented
by the output of a flip-flop.
Count Q3 Q2 Q1 Q0 Count Q3 Q2 Q1 Q0
0 0 0 0 0 8 1 0 0 0
1 0 0 0 1 9 1 0 0 1
2 0 0 1 0 10 1 0 1 0
3 0 0 1 1 11 1 0 1 1
4 0 1 0 0 12 1 1 0 0
5 0 1 0 1 13 1 1 0 1
6 0 1 1 0 14 1 1 1 0
7 0 1 1 1 15 1 1 1 1
0 0 0 0 0

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 4-bit (up) Counter: T Flip-Flops
1 T Q T Q T Q T Q
Synchronous Q0 Q1 Q2 Q3
Counter
Clock Q Q Q Q

Counter uses a common clock.

Clock

Q0

Q1

Q2

Q3

Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1

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 4-bit (up) Counter: JK Flip-Flops

Counter uses Synchronous

a common clock. Counter

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 4-bit Counter: D Flip-Flops
Enable D Q Q0

How does the XOR gate Q1

function when the Enable
D Q
signal is a logic-1? Q

D Q Q2

D Q Q3

Q
Output
Clock carry

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 Exercise
• Design a counter that counts in the sequence 0,
1, 3, 6, 10, 15 using
• a) D, b) SR, c) JK and d) T flip-flops.
• Design a counter with the following repeated
binary sequence: 0, 4, 2, 1, 6. Use T flip-flops.

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 Synchronous Counters

Binary Counter with Parallel Load

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 4-bit Counter with Parallel Load
Enable 0 Q0
D0 1 D Q
Q

0 Q1
D1 1 D Q
Q

0 Q2
D2 1 D Q
Q

0 Q3
D3 1 D Q
Q
Is the Load signal
active-high or active-low? Output
carry
Load
Clock

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 4-bit Counter with Parallel Load

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 Synchronous Counters

Modulo-6 Counter

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 Modulo-6 Counter: D Flip-Flops

1 Enable
0 D0 Q0
3-bit counter
0 D1 Q1
with Parallel Load
0 D2 Q2
Counter resets to zero
Load
when count reaches six.
Clock
Clock

Clock

Q0

Q1

Q2

Count 0 1 2 3 4 5 0 1

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 Modulo-6 Counter: T Flip-Flops
1 T Q T Q T Q
Q0 Q1 Q2

Clock Q Q Q

asynchronous clear signal Counter cleared when

count reaches six.

Clock

Q0

Q1

Q2

Count 0 1 2 3 4 5 0 1 2

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 Exercise
• Design a mod-5 counter which has the following
binary sequence: 0, 1, 2, 3, 4. Use JK flip-flops.

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 Counters
BCD (Decimal) Counter

(Modulo-10 Counter)

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 BCD Counter: State Diagram

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 BCD Counter: JK Flip-Flops

Asynchronous
Counter

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 BCD Counter: D Flip-Flops

Synchronous
Counter

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 Synchronous Counters

Up / Down Counter

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 4-bit Up / Down Counter

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 Introduction to Sequential Logic Circuits
(Finite State Machines)
and
FSM Analysis

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 Combinational vs. Sequential

Combinational Logic Circuit
− Output is a function of the inputs.
− Does not have state information.
− Does not require memory.

Sequential Logic Circuit
− Output is a function of the present state (and
of the inputs).
− Has state information
− Requires memory.
− Uses Flip-Flops to implement memory.
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 Synchronous vs. Asynchronous

Synchronous Sequential Circuit
− Clocked
− All Flip-Flops use the same clock and
change state on the same triggering
edge.

Asynchronous Sequential Circuit
− No clock
− Can change state at any instance in time.
− Faster but more complex than
synchronous sequential circuits.
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 Finite State Machine: Models

Moore Machine
− Outputs are a function of the present state.
− Outputs are independent of the inputs.
− State diagram includes an output value for each state.

Mealy Machine
− Outputs are a function of the present state and the
input.
− State diagram includes an input and output value for
each transition (between states).

There is an equivalent Mealy machine for each
Moore machine.
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 Finite State Machine: Models

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 FSM: State Diagram (Moore)
Output
State

A
Input

C B

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 FSM: State Diagram (Mealy)

State

Output

Input
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 Finite State Machine Analysis

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 FSM Analysis: Procedure
• Determine the Flip-Flop input equations
 In terms of the present state and input variables
• Determine the FSM output equation(s)
• Determine the next state values in the state table
 Assume binary encoding
 Use Flip-Flop Characteristic Equation
• Construct the state table
 Assign a state to each binary state assignment
• Draw the corresponding state diagram
• Determine the behavior of the FSM
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 FSM Analysis
Example:

FSM using D Flip-Flops

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 FSM Analysis: Example (D FF)

input

state

output
What type of
FSM is this?

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 FSM Analysis: Example (D FF)

Determine the FF input equations

and the FSM output equation(s)

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 FSM Analysis: Example (D FF)

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 FSM Analysis: Example (D FF)

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 FSM Analysis: Example (D FF)

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 FSM Analysis
Example:

FSM using JK Flip-Flops

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 FSM Analysis: Example (JK FF)

state
input

What type of
FSM is this?
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 FSM Analysis: Example (JK FF)

Determine the FF input equations

and the FSM output equation(s)

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 FSM Analysis: Example (JK FF)

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 FSM Analysis: Example (JK FF)

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 FSM Analysis
Example:

FSM using T Flip-Flops

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 FSM Analysis: Example (T FF)

input
output
state

What type of
FSM is this?

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 FSM Analysis: Example (T FF)

Determine the FF input equations

and the FSM output equation(s)

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 FSM Analysis: Example (T FF)

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 FSM Analysis: Example (T FF)

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 Sequential Logic Circuits:

FSM Design

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 FSM Design: Procedure
• Understand specifications
• Derive state diagram
• Create state table
• Perform state minimization (if necessary)
• Encode states (state assignment)
• Create state-assigned table
• Select type of Flip-Flop to use
• Determine Flip-Flop input equations and FSM output
equation(s)
• Draw logic diagram
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 FSM Design

• Moore Machines

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 FSM Design (Moore)
• Example:

• Design a FSM that detects a sequence of three or

more consecutive ones on an input bit stream.

• The FSM should output a 1 when the sequence is

detected, and a 0 otherwise.

A circuit that detects the occurrence of a particular pattern

on its input is referred to as a sequence detector.

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 FSM Design: Example (Moore)

Input: 011101011011101…
Output: 000100000000100…

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 FSM Design: Example (Moore)

State
Diagram

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 FSM Design: Example (Moore)

QA QB QA+ QB+

State Table
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 FSM Design: Example (Moore)

The choice of Flip-Flop determines the complexity of the
combinational logic required in the design of the state machine.

Each type of Flip-Flop has a unique characteristic equation.

SR Flip-Flop
JK Flip-Flop
− Q+ = S + R'.Q − Q+ = J.Q' + K'.Q

D Flip-Flop
T Flip-Flop
− Q+ = D − Q+ = T '.Q + T.Q'

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 FSM Design (Moore)

• Synthesis using D Flip-Flops

• (Q+ = D)

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 FSM Design: Example (Moore)
Flip-Flop
Input
QA QB QA+ QB+ DA DB

Q+ = D
next state flip-flop input
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 FSM Design: Example (Moore)

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 FSM Design: Example (Moore)

QA

QB

Q'B

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 FSM Design (Moore)

• Synthesis using JK Flip-Flops

• (Q+ = J.Q' + K'.Q)

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 FSM Design: Example (Moore)

Excitation Table

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 FSM Design: Example (Moore)

QA QB QA+ QB+

Q+ = J.Q' + K'.Q
next state flip-flop inputs
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 FSM Design: Example (Moore)

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 FSM Design: Example (Moore)

QA

Q'A

QB

Q'B

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• Example: FSM Design (Moore)

• Design a Finite State Machine (FSM) that meets

the following specifications:

1. The circuit has one input, w, and one output, z.

2. All changes in the circuit occur on the positive edge of the clock.

3. The output z is equal to 1 if the pattern 101 is detected on the

input w. Otherwise, the value of z is equal to 0. Overlapping
sequences should not be detected.

This is another example of a sequence detector.

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 FSM Design: Example (Moore)

Input (w): 0 0 0 1 0 1 0 1 1 0 1 1 0 1 1 …
Output (z): 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 …

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 FSM Design: Example (Moore)
Start State

State
Diagram

End State

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 FSM Design (Moore)
• Example:
• Design a Finite State Machine (FSM) that meets
the following specifications:

1. The circuit has one input, w, and one output, z.

2. All changes in the circuit occur on the positive edge of the clock.

3. The output z is equal to 1 if the pattern 101 is detected on the

input w. Otherwise, the value of z is equal to 0. Overlapping
sequences should be detected.

This is another example of a sequence detector.

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 FSM Design: Example (Moore)

Input (w): 0 0 0 1 0 1 0 1 1 0 1 1 0 1 1 …
Output (z): 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 …

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 FSM Design: Example (Moore)
Start State

State
Diagram

End State

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 FSM Design (Moore)
• Example:
• Design a Finite State Machine (FSM) that meets
the following specifications:

1. The circuit has one input, w, and one output, z.

2. All changes in the circuit occur on the positive edge of the clock.

3. The output z is equal to 1 if the pattern 110 or the pattern 010 is

detected on the input w. Otherwise, the value of z is equal to 0.
Overlapping sequences should be detected.

This is example of a sequence detector that can detect 2 sequences.

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 FSM Design: Example (Moore)

Input (w): 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1 …
Output (z): 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 …

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 FSM Design: Example (Moore)

State
Diagram

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 Sequential Logic Circuits:

State Assignment
And
State Minimization

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 State Assignment Problem

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 State Assignment Problem

Some state assignments are better than others.

The state assignment influences the complexity of the
state machine.
− The combinational logic required in the state machine
design is dependent on the state assignment.

Types of state assignment

− Binary encoding: 2N states → N Flip-Flops
− Gray-code encoding: 2N states → N Flip-Flops
− One-hot encoding: N states → N Flip-Flops
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 FSM: State Assignment
Example:

Design a FSM that detects a sequence of two or more

consecutive ones on an input bit stream.

The FSM should output a 1 when the sequence is

detected, and a 0 otherwise.

This is another example of a sequence detector.

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 FSM: State Assignment

Input: 011101011011101…
Output: 001100001001100…

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 FSM: State Assignment
Reset

w = 1
w = 0 AS⁄0z/=00 BS⁄ 1z /= 00

w = 0

w = 0 w = 1

CS⁄ 2z /=11
State
Diagram

w = 1

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 FSM: State Assignment

Present State Next State Output

w=0 w=1
S0 S0 S1 0
S1 S0 S2 0
S2 S0 S2 1

State Table

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 FSM: State Assignment #1
State Assigned Table
Present State Next State Output
w=0 w=1
QA QB QA+ QB+ QA+ QB+ z
S0 0 0 S0 0 0 S1 0 1 0
S1 0 1 S0 0 0 S2 1 0 0
S2 1 0 S0 0 0 S2 1 0 1
1 1 d d d d d

Using Binary Encoding

for the State Assignment
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 FSM: State Assignment #1
State Assigned Table

Present State Next State FF Inputs

w=0 w=1 w=0 w=1
QA QB QA+ QB+ QA+ QB+ DA DB DA DB
S0 0 0 0 0 0 1 0 0 0 1
S1 0 1 0 0 1 0 0 0 1 0
S2 1 0 0 0 1 0 0 0 1 0
1 1 d d d d d d d d

Characteristic Equation: D = Q+

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 FSM: State Assignment #1

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 FSM: State Assignment #1

K-Map and Boolean expression for z

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 FSM: State Assignment #1

Y2 y2
DA = w.(QA + QB) D Q zz

A
Q z = QA

Y1 y1
w
w D Q

DB = w.QA'.QB' B
Q

Clock
Resetn

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 FSM: State Assignment #2
State Assigned Table
Present State Next State Output
w=0 w=1
QA QB QA+ QB+ QA+ QB+ z
S0 0 0 S0 0 0 S1 0 1 0
S1 0 1 S0 0 0 S2 1 1 0
S2 1 1 S0 0 0 S2 1 1 1
1 0 d d d d d

Using Gray-code Encoding

for the State Assignment
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 FSM: State Assignment #2
State Assigned Table

Present State Next State FF Inputs

w=0 w=1 w=0 w=1
QA QB QA+ QB+ QA+ QB+ DA DB DA DB
S0 0 0 0 0 0 1 0 0 0 1
S1 0 1 0 0 1 1 0 0 1 1
S2 1 1 0 0 1 1 0 0 1 1
1 0 d d d d d d d d

Characteristic Equation: D = Q+

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 FSM: State Assignment #2

K-Map and Boolean expression for DA, DB and z

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 FSM: State Assignment #2
Y2 y2
DA = w.QB D Q zz
A
Q
z = QA

Y1 y1
DB = w w D Q
B
Clock Q

Resetn

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 FSM: State Assignment #3
State Assigned Table

Present State Next State

w=0 w=1
QA QB QC QA+ QB+ QC+ QA+ QB+ QC+
S0 0 0 1 S0 0 0 1 S1 0 1 0
S1 0 1 0 S0 0 0 1 S2 1 0 0
S2 1 0 0 S0 0 0 1 S2 1 0 0

For each state only one flip-flop is set to 1.

The remaining combination of state variables are not used.

Using One-hot Encoding

for the State Assignment Characteristic Equation: D = Q+

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 FSM: State Assignment #3

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 FSM: State Assignment #3
DA = w.QC' D Q z
A
Q z = QA

DB = w.QC D Q
B
Q

DC = w.' w D Q
C
Clock Q

Resetn

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 Exercise
• A sequential circuit uses two D flip-flops as
memory elements. The behaviour of the circuit
is described by the following equations:
• D1 = Q1 + x'*Q2
• D2 = x*Q1' + x'*Q2
• Z = x'*Q1*Q2 + x*Q1'*Q2'
• Derive the state table and draw the state
diagram of the circuit.

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• Derive the state output and state diagram for the
sequential circuit shown in

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 State Minimization

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 FSM: State Minimization

Definition:
Two states Si and Sj are said to be equivalent if and only if for
every possible input sequence, the same output sequence will be
produced regardless of whether Si or Sj is the initial state.

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 FSM: State Minimization

Definition:

A partition consists of one or more blocks, where each block

comprises a subset of states that may be equivalent, but the states in
a given block are definitely not equivalent to the states in other
blocks.

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 State Minimization: Partitioning

State Minimization through Partitioning:
– Form an initial partition (P1) that includes all states.
– Form a second partition (P2) by separating the states
into two blocks based upon their output values.
– Form a third partition (P3) by separating the states into
blocks corresponding to the next state values.
– Continue partitioning until two successive partitions
are the same (i.e. PN-1 = PN).
– All states in any one block are equivalent.

Equivalent states can be combined into a single state.

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 State Minimization: Partitioning

Example:

Use partitioning to minimize the number of states in

the following Finite State Machine (FSM).

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 State Minimization: Partitioning
A/ 1

B/1 C/0

State
Diagram
D/1 E/0

G/0 F/0

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 State Minimization: Partitioning

Present Next state Output

state w= 0 w= 1 z

A B C 1
B D F 1
C F E 0
D B G 1
E F C 0
F E D 0
G F G 0

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 State Minimization: Partitioning

Initial Partition:

P1 = (ABCDEFG)

The initial partition contains all states in the state diagram / table.

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 State Minimization: Partitioning

Separate states based on output value.
− P2 = (ABD)(CEFG)

Present Next state Output

state w= 0 w= 1 z

A B C 1
B D F 1
C F E 0
D B G 1
E F C 0
F E D 0
G F G 0

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 State Minimization: Partitioning

Separate states based on next state values.

ABD CEFG
0 1 0 1

BDB CFG FFEF ECDG

− P3 = (ABD)(CEG)(F)

unique state

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 State Minimization: Partitioning

Separate states based on next state values.

ABD CEG
0 1 0 1

BDB CFG FFF ECG

− P4 = (AD)(CEG)(F)(B)

unique states

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 State Minimization: Partitioning

Separate states based on next state values.

AD CEG
0 1 0 1

BB CG FFF ECG

− P5 = (AD)(CEG)(F)(B)

same as previous partition (P4)

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 State Minimization: Partitioning

Since P4 = P5, state minimization is complete.

The equivalent states are:
− A=D
− C=E=G
− B
− F

Thus, the FSM can be realized with just 4 states.

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 FSM: State Minimization

Present Next state Output

state w= 0 w= 1 z

A B C 1
B A F 1
C F C 0
F C A 0

Minimized State Table

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 FSM: State Minimization

Minimized
State Diagram

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 Memory

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 Memory

Memory is required to store:

1. data
2. application programs
3. operating system

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 Memory

Can be broadly classified as:

Random Access Memory (RAM)

or
Read Only Memory (ROM)

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 Random Access Memory (RAM)

Can be written to or read from.
− Read/Write memory

Reading from RAM is non-destructive.

Access time to read from any memory
location is the same.
− As compared to serial access memory.

Volatile
− Information is lost when power is
removed.
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 Random Access Memory (RAM)

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 Random Access Memory (RAM)

Static Random Access Memory (SRAM)
− Based on the Flip-Flop
− Requires a large number of transistors
− Fast

Dynamic Random Access Memory (DRAM)
− Uses a single transistor to store charge
− Requires very few transistors
− Must be periodically refreshed
− Slow(er)
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 Random Access Memory (RAM)

What is typically stored in RAM?

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 Read Only Memory (ROM)

Can only be read from.

Memory is written (or “programmed”) once

Reading from ROM is non-destructive.

Access time to read from any memory
location is the same.
− As compared to serial access memory.

Non-Volatile
− Information is retained even after power
is removed.
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 Read Only Memory (ROM)

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 Read Only Memory (ROM)

Programmable Read Only Memory (PROM)
− Can be “programmed”

Erasable PROM (EPROM)
− Can be “programmed” and erased

Electrically Erasable PROM (EEPROM)
− Can be erased using an electrical signal

UV Erasable PROM (UVEPROM)
− Can be erased using Ultraviolet light
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 Read Only Memory (ROM)

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 Read Only Memory (ROM)

What is typically stored in ROM?

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 Memory

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 Memory

Random Access Memory

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 Random Access Memory

Address
− Location in memory of the binary information
− Must be decoded to select the appropriate
location and read/write the associated data
− k-bit address → 2k memory locations

Data
− Binary information of interest
− Stored in a specific location in the memory
− Typically organized into words
− Each word has n bits
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 Random Access Memory

address data

10-bit address
1024 locations

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 Random Access Memory

Read
− Indicates that the memory is to be read

Write
− Indicates that the memory is to be written

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 Random Access Memory

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 Random Access Memory

Rather than use the Read and Write
signals, most commercially available RAM
chips use Enable and Read/Write'

Enable
− Used to enable the selected RAM chip
− Aka. “chip select”

Read/Write'
− RAM is read when Read/Write' = 1
− RAM is written when Read/Write' = 0
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 Random Access Memory

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 Random Access Memory

Write Cycle

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 Random Access Memory

Read Cycle

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 Random Access Memory

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 Random Access Memory

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