Exceptions

Dr. E. Papanasam AP-III

SoC
 Exceptions and Interrupts
• Control is the most challenging aspect of processor design:
• One of the hardest parts of control is implementing exceptions
and interrupts
– Events other than branches or jumps that change the
normal flow of instruction execution
• They were initially created to handle unexpected events from
within the processor, like arithmetic overflow
• Exception - any unexpected change in control flow without
distinguishing whether the cause is internal or external;
• Term interrupt used only when the event is externally caused
 Handling of Exception in MIPS
Architecture

• The basic action that the processor must perform when an

exception occurs is
– To save the address of the offending instruction in the
exception program counter (EPC) and
– Transfer control to the operating system at some specified
address
 Handling of Exception in MIPS
Architecture (2)
• Operating system can then take the appropriate action, which
may involve
– Providing some service to the user program,
– Taking some predefined action in response to an overflow,
or
– Stopping the execution of the program and reporting an
error

• After performing the required action, the operating system can

– Terminate the program or
– Continue its execution, using the EPC to determine where
to restart the execution of the program
 Handling of Exception in MIPS
Architecture (3)
• To handle the exception, the operating system must also know
the reason for the exception
• Methods used to communicate the reason for an exception
– Include a status register called the cause register (method
used in the MIPS architecture)
– Field of cause register indicates the reason for the
exception
– use vectored interrupts
– In a vectored interrupt, the address to which control is
transferred is determined by the cause of the exception
 Handling of Exception in MIPS
Architecture (4)
• The operating system knows the reason for the exception by
the address at which it is initiated

• Processing required for exceptions can be performed by

• Adding a few extra registers and control signals to our basic
implementation and by slightly extending control
 Handling of Exception in MIPS
Architecture (5)
• Two additional registers to be added to the MIPS implementation:
• EPC: A 32-bit register used to hold the address of the affected
instruction
• Cause:
– A register used to record the cause of the exception
– In the MIPS architecture, this register is 32 bits, although some
bits are currently unused
– Assume there is a five-bit field that encodes the two possible
exception sources
– 10 representing an undefined instruction and
– 12 representing arithmetic overflow
 Exceptions in a Pipelined
Implementation
• A pipelined implementation treats exceptions as another form of
control hazard
• Suppose there is an arithmetic overflow in an add instruction
– Flush the instructions that follow the add instruction from the
pipeline and
– Begin fetching instructions from the new address (Just as we
did for the taken branch)
• Same mechanism as we used for taken branches
• But the exception causes the deasserting of control lines
• To flush the instruction in the IF stage turn it into a nop
• To flush instructions in the ID stage, we use the multiplexor
already in the ID stage that zeros control signals for stalls
 Exceptions in a Pipelined
Implementation (2)
• A new control signal, called ID.Flush, is ORed with the stall
signal from the hazard detection unit to flush during ID
• To flush the instruction in the EX phase, we use a new signal
called EX.Flush to cause new multiplexors to zero the control
lines
• To start fetching instructions from location 8000 0180hex (MIPS
exception address), simply add an additional input to the PC
multiplexor that sends 8000 0180hex to the PC
• The overflow exception is detected during the EX stage
• Use the EX.Flush signal to prevent the instruction in the EX
stage from writing its result in the WB stage
 Exceptions in a Pipelined
Implementation (3)
• The final step is to save the address of the offending
instruction in the exception program counter (EPC)
• In reality, we save the address + 4, so the exception handling
routine must first subtract 4 from the saved value
Datapath with controls to handle
Exceptions
 Exception in a Pipelined Computer
• Given this instruction sequence,
• 40 sub $11, $2, $4
• 44 and $12, $2, $5
• 48 or $13, $2, $6
• 4C add $1, $2, $1
• 50 slt $15, $6, $7
• 54 lw $16, 50($7)
• ...
• assume the instructions to be invoked on an exception begin like
this:
• 80000180 sw $26, 1000($0)
• 80000184 sw $27, 1004($0)
• Show what happens in the pipeline if an overflow exception occurs
in the add instruction
The result of an exception due to arithmetic
overflow in the add instruction
The result of an exception due to arithmetic
overflow in the add instruction (2)
The result of an exception due to arithmetic
overflow in the add instruction (3)
• The overflow is detected during the EX stage of clock 6, saving the
address following the add in the EPC register (4C + 4 = 50hex)
• Overflow causes all the Flush signals to be set near the end of this
clock cycle, deasserting control values for the add

• Clock cycle 7 shows the instructions converted to bubbles in the

pipeline plus the fetching of the first instruction of the exception
routine—sw $25,1000($0)—from instruction location 8000
0180hex
• Note that the AND and OR instructions, which are prior to the
add, still complete
• ALU overflow signal is an input to the control unit (Not shown)
• Imprecise interrupt
– Also called imprecise exception
– Interrupts or exceptions in pipelined computers not
associated with the exact instruction that was the cause of
the interrupt or exception

• Precise interrupt
– Also called precise exception
– An interrupt or exception that is always associated with
the correct instruction in pipelined computers