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WWW - Manaresults.co - In: Linear Ic Applications

This document appears to be an exam for a course on linear integrated circuits applications. It contains: 1) Six questions in Part A asking about silicon planar technology processes, ideal op-amp equivalent circuit, instrumentation amplifier features, calculating Q value from bandwidth and resonant frequency, FSK generator using 555 timers, and basic DAC technologies. 2) Part B contains 7 questions, including describing an integrator circuit and advantages of ICs over discrete components, explaining input offset voltage with a diagram, describing a voltage to current converter and practical differentiator circuit, deriving expressions for a band reject and low pass filter, and computing lock in range and external component values for a PLL. 3) Questions also cover counter type

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83 views1 page

WWW - Manaresults.co - In: Linear Ic Applications

This document appears to be an exam for a course on linear integrated circuits applications. It contains: 1) Six questions in Part A asking about silicon planar technology processes, ideal op-amp equivalent circuit, instrumentation amplifier features, calculating Q value from bandwidth and resonant frequency, FSK generator using 555 timers, and basic DAC technologies. 2) Part B contains 7 questions, including describing an integrator circuit and advantages of ICs over discrete components, explaining input offset voltage with a diagram, describing a voltage to current converter and practical differentiator circuit, deriving expressions for a band reject and low pass filter, and computing lock in range and external component values for a PLL. 3) Questions also cover counter type

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t chinna
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Code No: RT31042 R13 SET - 1

III B. Tech I Semester Supplementary Examinations, May - 2019


LINEAR IC APPLICATIONS
(Common to Electronics and Communication Engineering, Electronics and Instrumentation
Engineering, Electronics and Computer Engineering)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answering the question in Part-A is compulsory
3. Answer any THREE Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PART –A
1. a) List the basic processes used in the silicon planer technology. [3M]
b) Draw the equivalent circuit of an ideal OP-AMP. [4M]
c) List the important features of an instrumentation amplifier. [4M]
d) The resonant frequency fo of a band pass filter is 1khz and its bandwidth is 3 kHz. Find [3M]
the value of Q.
e) Discuss the operation of a FSK generator using 555 timers. [4M]
f) Explain about basic DAC technologies with schematic diagram. [4M]
Q. PART -B
2. What is an integrator circuit? Discuss the relative advantages and disadvantages if IC’S [16M]
over discrete assembly. How will you make a monolithic IC explain in detail?

3. a) Explain about input offset voltage with a neat diagram. [8M]


b) Define Slew rate. How it effect the op-amp performance? Explain. [8M]

4. a) With a neat diagram explain about the voltage to current converter in details. [8M]
b) Describe the working of practical differentiator circuit. Derive the expression for output [8M]
voltage.

5. a) With a neat diagram explain the band reject filter. Derive the expression for output [8M]
voltage.
b) Design a first order low pass filter for a high cut-off frequency of 2 kHz and pass band [8M]
gain of 2.

6. The free running frequency of a 565 PLL is 100 kHz, the filter capacitor is 2μF and [16M]
supply voltage is ± 6V. Compute the lock in range, capture range frequency and value of
external components RT and CT.

7. a) With a neat diagram explain about the counter type A/D converter in detail. [8M]
b) Determine the output voltages caused by each bit in a 6-bit ladder if the input levels are [8M]
0=0v and 1=+16v. Determine the resolution and full-scale output of this circuit. Find out
the voltage from the above ladder for a digital input of 101011.

*****

www.manaresults.co.in

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