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Carry Save Adder Verilog Code

The document describes a carry save adder module and test bench implemented in Verilog. It uses full adders and ripple carry adders to perform additions without propagating carries between stages, allowing for faster addition of multiple operands. The module takes in 4 byte operands and outputs their sum along with a carry bit. It first adds pairs of operands using full adders, then adds the results with the fourth operand to produce the final sum.

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MANISHA S
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3K views

Carry Save Adder Verilog Code

The document describes a carry save adder module and test bench implemented in Verilog. It uses full adders and ripple carry adders to perform additions without propagating carries between stages, allowing for faster addition of multiple operands. The module takes in 4 byte operands and outputs their sum along with a carry bit. It first adds pairs of operands using full adders, then adds the results with the fourth operand to produce the final sum.

Uploaded by

MANISHA S
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Carry Save adder:

module Carry_save_adder_8(input [7:0]b,input [7:0]c,

input [7:0]d,input [7:0]e,

output [8:0]sum,output cout);

wire [7:0]s0,c0,c1;

wire [6:0]cw,s1;

full_adder fa0(.sum(s0[0]),.cout(c0[0]),.a(b[0]),.b(c[0]),.cin(d[0]));

full_adder fa1(.sum(s0[1]),.cout(c0[1]),.a(b[1]),.b(c[1]),.cin(d[1]));

full_adder fa2(.sum(s0[2]),.cout(c0[2]),.a(b[2]),.b(c[2]),.cin(d[2]));

full_adder fa3(.sum(s0[3]),.cout(c0[3]),.a(b[3]),.b(c[3]),.cin(d[3]));

full_adder fa4(.sum(s0[4]),.cout(c0[4]),.a(b[4]),.b(c[4]),.cin(d[4]));

full_adder fa5(.sum(s0[5]),.cout(c0[5]),.a(b[5]),.b(c[5]),.cin(d[5]));

full_adder fa6(.sum(s0[6]),.cout(c0[6]),.a(b[6]),.b(c[6]),.cin(d[6]));

full_adder fa7(.sum(s0[7]),.cout(c0[7]),.a(b[7]),.b(c[7]),.cin(d[7]));

full_adder fa8(.sum(sum[0]),.cout(c1[0]),.a(e[0]),.b(s0[0]),.cin(1'b0));

full_adder fa9(.sum(s1[0]),.cout(c1[1]),.a(e[1]),.b(s0[1]),.cin(c0[0]));

full_adder fa10(.sum(s1[1]),.cout(c1[2]),.a(e[2]),.b(s0[2]),.cin(c0[1]));

full_adder fa11(.sum(s1[2]),.cout(c1[3]),.a(e[3]),.b(s0[3]),.cin(c0[2]));

full_adder fa12(.sum(s1[3]),.cout(c1[4]),.a(e[4]),.b(s0[4]),.cin(c0[3]));

full_adder fa13(.sum(s1[4]),.cout(c1[5]),.a(e[5]),.b(s0[5]),.cin(c0[4]));

full_adder fa14(.sum(s1[5]),.cout(c1[6]),.a(e[6]),.b(s0[6]),.cin(c0[5]));

full_adder fa15(.sum(s1[6]),.cout(c1[7]),.a(e[7]),.b(s0[7]),.cin(c0[7]));

ripple_carry_adder_8 rc0(.sum(sum[8:1]),.cout(cout),.a(c1[7:0]),.b({c0[7],s1[6:0]}),.cin(1'b0));

endmodule
module ripple_carry_adder_8(input [7:0] a,

input [7:0] b,

input cin,

output [7:0] sum,

output cout );

wire [6:0]c;

full_adder FA0(.a(a[0]),.b(b[0]),.cin(cin),.sum(sum[0]),.cout(c[0]));

full_adder FA1(.a(a[1]),.b(b[1]),.cin(c[0]),.sum(sum[1]),.cout(c[1]));

full_adder FA2(.a(a[2]),.b(b[2]),.cin(c[1]),.sum(sum[2]),.cout(c[2]));

full_adder FA3(.a(a[3]),.b(b[3]),.cin(c[2]),.sum(sum[3]),.cout(c[3]));

full_adder FA4(.a(a[4]),.b(b[4]),.cin(c[3]),.sum(sum[4]),.cout(c[4]));

full_adder FA5(.a(a[5]),.b(b[5]),.cin(c[4]),.sum(sum[5]),.cout(c[5]));

full_adder FA6(.a(a[6]),.b(b[6]),.cin(c[5]),.sum(sum[6]),.cout(c[6]));

full_adder FA7(.a(a[7]),.b(b[7]),.cin(c[6]),.sum(sum[7]),.cout(cout));

endmodule

module full_adder(a,b,cin,sum, cout);

input a,b,cin;

output sum, cout;

wire x,y,z;

half_adder h1(.a(a), .b(b), .sum(x), .cout(y));

half_adder h2(.a(x), .b(cin), .sum(sum), .cout(z));

assign cout= y|z;

endmodule
module half_adder( a,b, sum, cout );

input a,b;

output sum, cout;

assign sum= a^b;

assign cout= a & b;

endmodule

TEST BENCH:

module Carry_save_adder_8_testbench( );

wire [8:0]sum;

wire cout;

reg [7:0]b,c,d,e;

Carry_save_adder_8 uut(.b(b),.c(c),.d(d),.e(e),.sum(sum),.cout(cout));

initial

begin

$display($time, " << Starting the Simulation >>");

b=0; c=0; d=0; e=0;

#100 b= 8'd255; c=8'd255; d=8'd255; e=8'd40;

#100 b= 8'd10; c=8'd0; d=8'd0; e=8'd0;

#100 b= 8'd10; c=8'd10; d=8'd0; e=8'd0;

#100 b= 8'd4; c=8'd6; d=8'd12; e=8'd0;

#100 b= 8'd11; c=8'd2; d=8'd4; e=8'd7;

#100 b= 8'd20; c=8'd0; d=8'd20; e=8'd0;

#100 b= 8'd12; c=8'd5; d=8'd10; e=8'd10;

#100 b= 8'd7; c=8'd6; d=8'd12; e=8'd8;

#100 b= 8'd15; c=8'd15; d=8'd15; e=8'd15;


end

initial

$monitor("B=%d, C=%d, D=%d,E=%d,Sum= %d, Cout=%d",b,c,d,e,sum,cout);

endmodule

Ripple carry adder verilog code:


module ripplecarryadder(a, b, cin, sum, cout);

input [07:0] a;

input [07:0] b;

input cin;

output [7:0]sum;

output cout;

wire[6:0] c;

fulladd a1(a[0],b[0],cin,sum[0],c[0]);

fulladd a2(a[1],b[1],c[0],sum[1],c[1]);

fulladd a3(a[2],b[2],c[1],sum[2],c[2]);

fulladd a4(a[3],b[3],c[2],sum[3],c[3]);

fulladd a5(a[4],b[4],c[3],sum[4],c[4]);

fulladd a6(a[5],b[5],c[4],sum[5],c[5]);

fulladd a7(a[6],b[6],c[5],sum[6],c[6]);

fulladd a8(a[7],b[7],c[6],sum[7],cout);

endmodule

module fulladd(a, b, cin, sum, cout);

input a;

input b;

input cin;output sum;output cout;


assign sum=(a^b^cin);

assign cout=((a&b)|(b&cin)|(a&cin));

endmodule

TEST BENCH:

module ripple_adder_tb( );

reg [7:0] a;

reg [7:0] b;

reg cin;

wire [7:0] sum;

wire cout;

ripplecarryadder uut (.a(a),.b(b),.cin(cin),.sum(sum),.cout(cout) );

initial

begin

a=8'b00000001;b=8'b00000001;cin=1'b0;

#10 a=8'b00000001;b=8'b00000001;cin=1'b1;

#10 a=8'b00000010;b=8'b00000011;cin=1'b0;

#10 a=8'b10000001;b=8'b10000001;cin=1'b0;

#10 a=8'b00011001;b=8'b00110001;cin=1'b0;

#10 a=8'b00000011;b=8'b00000011;cin=1'b1;

#10 a=8'b11111111;b=8'b00000001;cin=1'b0;

#10 a=8'b11111111;b=8'b00000000;cin=1'b1;

#10 a=8'b11111111;b=8'b11111111;cin=1'b0;

#10 $stop;

end

endmodule

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