Mapping DSP Algorithms

Into FPGAs
Sean Gallagher,Senior DSP Specialist,
Xilinx Inc.
[email protected]
215-990-4616
 Agenda

§ History of Algorithm implementations in FPGAs

§ Why FPGAs for Signal Processing
§ Overview of Xilinx FPGA
§ Interesting Algorithms for FPGA implelentation
– Critically sampled channlizer
– Divide and Conquer DFT
– Winograd FFT
§ The Xilinx DSP tool flow

Page 2
 History FPGAs for Algorithm Implementation

§ Systolic Array processing techniques were established in the

‘70s
– S.Y. Kung, others
§ FPGA technology invented by Xilinx in 1984
– Glue logic integration
– Super Computing Research Center (SRC) built Splash I and II
coprocessing boards in early ’90s
– Board of 32 Xilinx FPGAs slaved to a Sun workstation
– Computation speeds of 6-7 times greater than a Cray II computer

Page 3
 My History With FPGAs

§ Visited SRC in early ‘90s to sell synthesis tools

– Had no clue what they were talking about
§ Pursued MSCE at Villanova focused on algorithms in FPGAs
– They had no idea what I was talking about
– Master’s thesis in ‘95, Implementing Algorithms in FPGAs
§ Came to Xilinx in 2001 as DSP Specialist
– Still learning

Page 4
Emerging Applications Drive Demand for
Next Generation FPGAs

Next Gen Wireless Automotive

Communications Infotainment

Next Gen Wired •Consume

Communications r

Industry’s Highest
Lowest Power Industry’s Best
System Performance
and Cost Price-Performance
and Capacity
• Handheld portable • Wireless LTE infrastructure • 100GE line card
ultrasound • 10G PON OLT line card • 300G bridge
• Digital SLR lens • LED backlit and 3D video • Terabit switch fabric
control module displays • 100G OTN
• Software defined radio • Medical imaging • MUXPONDER
• Avionics imaging • RADAR
• ASIC emulation
• Test & Measurement

•Aerospace Audio Video

•& Defense Broadcast
•Test & Medical
Measurement Imaging
Page 5
Why FPGA for Signal Processing?

1 GHz
= 4 MSPS
256 clock cycles

- How much computational power do you need?

500 MHz
= 500 MSPS
1 clock cycle

Page 6
 Flexibility

- How many MACs (multiply accumulator) do you need?

- For Example, in FIR Filter,
OutputDataRate * NumberOfTaps * NumberOfChannels
Number of MACs required =
InputDataRate * ClockRate

Parallel Semi -Parallel Serial

× +
× + +
× +
+ DQ
+
+ DQ

× +
+
× + × +

× +

Speed Area

FPGAs can meet various throughput requirement

Page 7
“Multi-Channel Friendly”

20MHz LPF ch1 80MHz

Samples Samples
LPF ch2
LPF
LPF ch3
Multi Channel
ch4 Filter
LPF

§ Parallelism enables efficient implementation of multi-channel into a single

FPGA
§ Many low sample rate channels can be multiplexed (e.g. TDM) and
processed in the FPGA, at a higher rate
§ Many of Xilinx IPs takes advantage of multi-channel implementation -
FIRCompiler, FFT

Page 8
FPGA + DSP Processor

§ FPGA enables DSP processor acceleration – mapping speed critical

loop of DSP code to FPGA
§ FPGAs enables consolidation of glue logic, memory, interfaces, ASSP
§ For detail on interface (EMIF,VLYNQ,LinkPort), see
http://www.xilinx.com/esp/wireless.htm

FPGA as pre-processor FPGA as co-processor

500 MHz 500 MHz
100 MHz 100 kHz C6416 100 kHz

C6416

Page 9
6 Series Xilinx FPGAs

•Now Shipping

§ Virtex-6 - Industry leading DSP performance

§ Spartan-6 Industry leading DSP cost / performance

Industries Best Industries Highest

Price/Performance System Performance
Logic Cells 3.8K – 147K 74K – 567K
DSP Slices 8-180 288-2016
Max Transceivers 8 72
Transceiver 3.125 Gbps 6.6 Gbps
Performance 11.18 Gpbs
Memory 4,824 Kbits 38,309 Kbits
Max. SelectIO 576 1200
SelectIO Voltages 1.2v to 3.3v 1v to 2.5v

Page 10
Introducing the 7 Series FPGAs

§ Industry’s Lowest Power and First Unified Architecture

– Spanning Low-Cost to Ultra High-End applications
§ Three new device families with breakthrough innovations in power
efficiency, performance-capacity and price-performance

Page 11
 Bridging the DSP Performance Gap with 7-Series

•DSP Performance

•4752 GMAC

•7-Series

•6-Series
•2000 GMAC

•Virtex-7
•770 GMAC
•Virtex-
•90 GMAC 6 •Kintex-7
•33 GMAC
•Spartan-6
•Time
•Multi-core DSP Architectures
•* Peak performance for symmetric filters
 FPGA Resource

§ Challenge: How do we make the best

use of these resources in most
efficient manner?

DSP48

B 18

25 x 18 48 P
A MULT
25
25

D 25
+/- C =

Virtex-6 Overview 13

BRAM Logic Fabric

CLB,
Switch
IOB,
Matrix
DCM

Page 13Base Platform

Virtex-6 13
 DSP Performance through the DSP48E1 Slice
Virtex-6, Artex-7, Kintex-7, Virtex-7

DSP48E1 Slice

B
25x18 48-Bit Accum
DSP48 Tile +
Pre-Add X P
A -
•Interconnect

DSP48E1
Slice +/-
DSP48E1 D =
Slice
Pattern
C Detector

§ 2 DSP48E1 Slices / Tile

§ Column Structure to avoid routing delay
§ Pre-adder, 25x18 bit multiplier, accumulator
§ Pattern detect, logic operation, convergent/symmetric rounding
§ 638 MHz Fmax
Page 14
 Pre-Adder

§ Hardened Pre-Adder leverages

filter symmetry to reduce Logic,
Power and Routing
§ No restriction to coefficient table
size

•Filter symmetry
exploited to pre-add
tap delay values and
reduce multiplies by
•Coefficients cn 50%
Greater Flexibility with Fully Independent Multipliers

• DSP48 Tile
•Interconnect

DSP48E1
Slice

DSP48E1
Slice

§ Full, independent access to every multiplier

§ One accumulator for each multiplier
§ 5 Interconnects support up to 50 bit multiplies per tile
 25x18 Multiplier

§ Single DSP slice supports up to

25x18 multiplies
– 50% fewer DSP resources required
for high-precision multiplies
– Efficient FFT Implementations
– Efficient single-precision floating-
point implementations
§ Single DSP Tile supports up to
50x36 multiplies
§ Delivers higher performance and
lower power
 Efficient Rounding Modes using Pattern Matching

§ Only FPGA architecture

that supports pattern
detection
– Pattern can be constant (set by
attribute) or C input
§ Efficient implementation of
rounding modes
– Symmetric
– Convergent
– Saturation
 One Accumulator for each Multiplier

§ DSP48E1 slice provides an

accumulator for each
multiplier
– 2X more than competitive
architectures
§ Up to 48-bits accumulation per DSP
slice
– 25x18 multiply
§ Up to 96-bits accumulation per DSP
tile
– 50x36 multiply
 DSP IP Portfolio

Category IP Blocks

§ Comprehensive IP portfolio Math mult, adder, accumulator,

divider, trig, CORDIC
Filters FIR, CIC
§ Constraint Driven Memory RAM, register, FIFO, shift
register
Transforms FFT, IFFT, LTE FFT
§ IP can be imported into RTL,
Processors MicroBlaze
System Generator and
Platform Studio Video Color correction, CFA, pixel
correction, image
characterization, edge
enhancement, noise reduction,
statistics, CSC, VFBC, Scaler,
timing controller,
Wireless DDS, DUC/DDC, MIMO
Decoder/encoder, RACH
preamble det, DPD, CFR,
Floating-Point Add/sub, mult, div, sqrt,
compare, convert, FFT
20
 Constraint Driven IP

Interpolate by 2

30.22 MHz FIR Compiler 61.44 MHz

6.0

11 Tap FIR Filter

Parameter Result 1 Result 2 Result 3 Result 4
Channels 2 2 4 4
Clock Frequency 122.7 245.4 245.4 368.1
DSP Slice Count 3 1 3 1

§ Overclocking automatically used to reduce DSP slice count

§ Quick estimates provided by IP compiler GUI
§ Insures best results for your design requirements

21
 Interesting Algorithms For FPGA
Implementation

§ Critically sampled channelizers

– Polyphase with a DFT bank
§ Divide and conquer DFT
– Calculating a 1D FFT as a 2DFFT
§ Winograd FFT Transform
– Least amount of multiplies

22
Passband Polyphase Filters

S( f ) •channels

f
fc fc fc fc fc
§ In a FDM digital communication system a common
requirement is, for each channel:
– translate the channel to baseband
– shape the channel spectrum
– reduce the sample rate to match the channel bandwidth
§ This is the function of a channelizer
§ When the channel spacing’s are equal a
computationally efficient structure for performing the
above functions is the carrier centered polyphase
transform
Channelization 23
Baseband Polyphase Filter

h0 ( n)
h1 (n )
x ( n)
h2 (n ) y ( Mn)

hM −1 (n )

h0 (n) = h0 hM L hN − M
h1 (n) = h1 hM +1 L hN − M +1
M M M L M
hM −1 (n) = hM −1 h2 M −1 L hN −1

Channelization 24
Passband Polyphase Filters

Express the filter coefficient set in terms of a course and vernier index
r1 and r2 respectively
N
h(n) = h(r1 + Mr2 ) r1 =0,K , M − 1, r2 =0,K , −1
M
•Invoke the modulation theorem to convert a prototype baseband filter
to its equivalent carrier centered, or spectrally shifted version

if h(n) ⇔ H (θ )
then h(n)e jθ 0n ⇔ H (θ − θ 0 )

Channelization 25
Passband Polyphase Filters

The coefficients of the carrier centered filter are

g (n) = h(n)e jθ 0n

| H (θ ) | | G (θ ) |

θ
−π θ0 π
Now perform a polyphase partition on the modulated coefficients
g r1 ( r2 ) = h( r1 + Mr2 )e jθ0 ( r1 + Mr2 )
= h(r1 + Mr2 )e jθ 0 r1 e jθ0 Mr2

Select θ 0 so that a single period of the series e jθ 0 n is harmonically

related to M
Channelization 26
Passband Polyphase Filters

2π
θ0 = k
M
2π
jk Mr2
jθ 0 r1
g r1 ( r2 ) = h( r1 + Mr2 )e e M

2π
jk r1
= h( r1 + Mr2 )e M

•Carrier centered e j1θ k

polyphase filter h0 ( n)
•the one structure e j1θ k
•baseband’s the x ( n) h1 (n)
channel
•shapes the signal y ( Mn, k )
•reduces the e j ( M − 2)θ k
sample rate hM −2 (n )
e j ( M −1)θ k
hM −1 ( n)

Channelization 27
Passband Polyphase Filters

h0 (n)

h1 (n)
y (Mn, 0)

hM −2 (n)

hM −1 (n)
x ( n)
e j1θ k
h0 (n)
e j1θk
h1 (n)
•Recovering 2 channels from y (Mn, k )
FDM spectra
•The two sets of filters e j ( M −2)θk
employ identical coefficients hM − 2 (n)
•Note: the two sets of filters e j ( M −1)θ k
hM −1 (n)
contain the same data

Channelization 28
Passband Polyphase Filters

y (Mn, 0)

h0 (n)

h1 (n)
x ( n)

e j1θ k
hM − 2 (n)
e j1θ k
hM −1 (n)
y (Mn, k )
•Only one filter is required
because the data is the same in e j ( M −2)θk
both filters on the previous slide
e j ( M −1)θk
•Baseband and carrier centered
polyphase filter, heterodyne and
downsample

Channelization 29
Polyphase Transform

Recall that the IDFT of an M -point sequence Y (k ) is

M −1
y (n) = ∑ Y ( k )e j 2π nk / M n = 0,1,K , M − 1
k =0
If the M phase rotators are sequenced over all of the M values of k
we recognize that this is the same as computing an IDFT

h0 ( n) y ( Mn, 0)

x ( n) h1 (n ) y ( Mn,1)

•M-Point
•IDFT
hM −2 (n ) y( Mn, M − 2)

hM −1 ( n) y ( Mn, M − 1)

Channelization 30
 •Passband Polyphase Filters
h0 (n)

h1 (n)

hM −2 (n)

hM −1 (n)

e j1θ k
h0 (n)
•Carrier centered polyphase
e j1θk
filters can also be used for
h1 (n)
constructing frequency
division multiplexed signals
e j ( M −2)θk
•Baseband and carrier
hM − 2 (n) centered polyphase filter,
e j ( M −1)θk heterodyne and upsample
hM −1 (n)

Channelization 31
 •Passband Polyphase Filters

h0 (n)

h1 (n)

e j1θ k

hM −2 (n)
e j1θk

hM −1 (n)

e j ( M −2)θk •Baseband and carrier

centered polyphase common
e j ( M −1)θk
filter, heterodyne and
upsample
Channelization 32
 Divide and Conquer FFT

§ It is possible to compute a one dimensional DFT as a two

dimensional DFT
– Ideal for processing hi rate data that has been demuxed to multiple
paths at a lower rate

M −1 L −1
X ( p, q ) = ∑ ∑
Decompose DFT ( Mp + q )( mL + l )
into two dimensions:
x ( l , m )W N
m=0 l =0

But: WN( Mp + q )( mL +l ) = WNMLmpWNMLqWNMplWNlq

However:
WNNmp = 1, WNmqL = WNmq/ L = WMmq and WNMpl = WNpl/ M = WLpl
 M −1 
{
L −1
X ( p, q ) = ∑ WNlq  ∑ x (l , m)WMmq  }WLlp
l =0  m =0 

Page 33
 Divide and Conquer FFT

These simplifications lead to:

 
{
L −1 M −1
X ( p, q ) = ∑ WNlq  ∑ x(l , m)WMmq  }WLlp
l =0  m=0 

Process Steps:
1. Store signal column-wise
2. Compute the M point DFT for each row
lq
3. Multiply the resulting array by the phase factors WN
4. Compute the L-point DFT of each column
5. Read the resulting array row wise

Page 34
 Winograd FFT

Developed by mathematician Schmuel Winograd in 1976

•Goal was to reduce the number of multiplies required
•Multiplies minimized but at expense of increased complexity
•Memory mappings became very complex too
•Due to complexity, cost of doing an fft did not significantly go down
•Problem with algorithm is that multiplies and accumulates were separated
so execution on DSP processor was not efficient

Page 35