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, M . TECH rS P) I\UD-SEMESTER EXAMINATION, SEPTEMBER 2016

SP-502 Digital System Design

t
<\ne mpt all question s. A ssume any missing data suitably. MAX MARKS: 20

, 1 Construct a 16 x 1 multiplexer with two 8 x 1 and one 2 x 1 multiplexers. Use block diagrams . Implement
VerilogNHOL code for the aforementioned 16 x 1 multiplexer. Also include test bench for verification of the
functionality. (8)

2. Distinguish between synchronous and asynchronous RESET by writing VerilogNHDL code for both
(a) 0-Latch
(b) D Flip-flop (6)

.1 A sequential circuit has an input (X) and an output (Z) . The output is the same as the input was three clock periods
previ ously . For example.
X=OIOI IOlOl lOIOOOI
Z = OOOOJOl 1010110 10
(6)
The first three values of Z are O Find a Mealy state graph and table for the circuit.
---·------·---------- - ------- ---------------- -·- - - - ---
 ~ q •. I i ··- :i' •I , , C' ) -- - •• •'• I'
:-!! • j qi,.;;i \~i ] .l ' ... '-- 111 ~ !.~1.;,

fvH<l .,5em~!)H,'l f fx;::minJtiuH

Si-U04 : Oigitnl Sy5tum Do~1g,i

Q. 1
linplemcr t the following IJoolean function with a 3 x 8 decod1;r (a:;surn o active hieh·out!) Ut}.
Fl (A, B, C) = re M (0, 3, 4, 6) . Also write verilog code for the same using structural style o.f ·
niodo liing . [5]

~ 2. (a ) 0~; ivi:. the ~i:i;:tt! tyLJl i:: .:inJ U1 r: ,:ta~t: J1il grJ1 ! 1 uf U:e ;;i;qu~r,ti i:i l c.irc uit slH)\.Vn in the figq'i·e
below. (3]

/ \
I J
- - ·1 l_J
(l>} f.xµlain th e µrubl c1n of IJ tcl1 in fercncd encu untert:d uuri11t3 Jorie syn U1c: :;is. [1]

(c) Dtffcrcn tiJ te bet 1.vee11 bl ocking Jnd non-blockin(! stJten1 ents. [1]

u. 3 A :J~~'t.1t.:11t1c;11 drcu,l lid) on~ iHµu t {X) a11J one outpu t( /.). Ur,fvVLJ 1\/i~dly stJ ll: (Ov1:. 1;Jp 1Ji r,g}
grdph if the outpu t is Z :: 1 when the total nu 1nbcr of l's re ceived is ciivi:;ibl c by 3. Al;;o v✓ ri tc
Ver dog cod1; for the sJme. ·fs]

· ··•-t • •···,·······················'~·•~~•·~····~••+f ♦ ••7+7••··~~•~·• ~·f 1 4~ ~ ~ ~4 .~~

 l

\ fa x Marb ·20

y _ _ _ _ _ _.....,.
I-

z---------'----4
OR
Q . 1) Gi_ven the Boolean function F== xy'z + x 'y'z + w'xy + wx 'y + wxy
a) Obtam the truth table of the function .
b) ~raw _the gate structure using the original Boolean expression .
c) Simp_hfy the function to a minimum number of literals using Boolean algebra.
d) Obtam the truth table of the function from the simplified expression and show that it is the same as
the one in part (a)
e) Draw the gate structure from the simplified expression and compare the total number of gates with
the diagram of part (b) (2)

Q .2) Give an algorithmically designed Combinational circuit for 4-bit comparator. Also explain the
step involved in designing the algorithm . (3)

Q.3) Complete the design of the BCD-to-seven-segment decoder by performing the following steps.
(a) Plot the seven maps for the outputs ·
(b) Simplify the seven output functions in sum of products form , and determine the total number of
gates that will be needed to implement the decoder.
(c) Verify that the seven output functions give a valid simplification . Compare the number of gates
with that obtained in (b ). (3)

Q.4) Many offices and buildings use combination locks to control entry . As the design engineer of the
Wonderful Door Security Company, you are asked to implement a door security system by using a
card reader. There are four inputs to the card reader: inputs X, Y, and Z are used to validate the
correct door code, and input V is used to check if the card reader is still valid. After the card reader is
being read by the system, there are three outputs to this system : alarm (A), door open (D), and Error
(E). Door (D) will only open when the decimal value of the binary inputs (x, y, z) is odd AND the
card reader is valid. The Error (E) signal goes on when the code on the card is correct (i .e. decimal
value equal to odd) but the card is no longer valid. Finally, the alarm (A) will trigger when the code is
incorrect. Show your final design in canonical product of sum form. (3)

Q.5) Design a PLA as 4X4X2 to implement the following two Boolean functions . Minimize the
number of product terms. Show all your work, including the Kamaugh maps used in the minimization.
FI (A,B,C,D) = I(I , 3, 4, 5, 7, 13 , 15)
F2 (A ,8 ,C,D) = I(O, 2 , 3, 6, 7, 8, 10, 11 , 12, 14) (3 )
. th ..c. nee issues related to static interconnection networks. (3)
Q.6) Explam e penorma

Q 7) Solve any TWO . ( 1 5)

. . Fl 's classification of Computer Architecture. . . ~
a) Explain Y?11 . d t s and disadvantages of slmred -rnemory r. f\d message-passing
b) Provide a li st of the mam a van age. . t l. 5}
paradigm. (1 .5)
c) Write short note on PAL, GAL and FPGA
 ,I

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t < l> I J U1u 1tnl ,ntti m l> c•,.lun t ,fnJ. \ HU I \ •ril u.,:

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, Jl u u1,

\tl \jU«',thtn, r1u 1, t' tflhtl m urk .. . •\ '1'- llrnt· ,uaieuhlt- m i<i'i iO J;t tl11tit , if"" '

lI o ~hl ~I
) itkt<,'1111,lh hL'l\\1,•1.·11 lllt' t l1.d drl.t\ .,nd t1nn , p1111 d <.•l. 1) \\ Ith the heir ii ,lllt.ihk
, ~n,pt~
\ \ flll. .1 \ t H >I 1. t11.ll.' 1,,1 r..l h11 h1II ,\dJ1..·1 us111 g Cu: m:r..ill' ~!tilcment rn '-itrrn.. tural
tl h ,J\.'1111 11 •
I),·" Lu 1..· .11 1 11Het•c.:1 dt11:i t, pr t( 1 c1call..· .1 memor) u t i; l 2 l>vtc, with X n<l<lrc.,., ltnc

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l,UL'P lt.'llt,

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\ \ rHL' J \ 'l 11)1 pwces:> that. Is cq u1 va lcn1 to th e fo ll owing concu rrent stakmt:11'
\ Bl \\ hen C I cl-;c B~ '" hen C 2 else l:D when C 3 el <;c f)
Orn,, ,, a, etom1 Jiagram to ex plain ··wait for Ons·· .
,p1.... 11 , ih " hlo ... k sw tcrnc nt c:-m be used to rcmnvc Jri, er for am '>1µnal

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.... OD J11p-1lop l~ ~lll1! lar to <I l) 11 ir- t1or. L'XCL'pt !hat the ll1p-tl op t:J.n ch.mg...: :H,tt .:
1; ;)1 t,n hoth the ri si ng l'dge :i nd fal ling ed g.c of the cl0ck mrut l he 1l1p-tlr1r h..1"
J1rc~• fl''- l' I 111ptll R. •md R ·o· l\.'S Ct S the 111 r -fiop :( 1 l ) () tndl?N'nden. (1 t tt1 l'
,t'~" \ 1mJidrl :,. ,: has .1 J 1rl'L'.l set input. S. th~lt se ts; tile l11i~ t •1i' h · n.L.:; :n-.1 ..:::
the clock Write ~1 VI IDL descripti on of a DD ll ip-!lop.
1r tht lo ll<w.ing \ HD! (ode .. \ IL (.'&. I) :1 fl' htt st~n.,b th ,1t .m: (l ,lt ttm l' ..i11-., ,t
..:hang<:!- to I ell ll!Til' Sn~. ma.k l" a tahk shm\'111g th1..· \ ,d11l· ~ ( 1 1 \ . n. I...° 1.\ i) J., ..1
luncuon ot tllnc unt i l um c = l 8ns ( Include .\ dclt:1 ). lnd il'atL' th'-· times ,.It\\ h1,,:h c.t.. : L
;,rocc~~ heµ111~ cxec utmµ
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 .',1/Jl \ ,>. of Puges: :! Roll No ..... .. .. .. .... .. .. ....
VII SEMESTER B.E. (ECE/CoE/ICE) I

«~ MlD SEMESTER EXAMINATION, September2012

F. C/CoE- 402: Digital Circuits & Systems-II ; IC-402: Digital

r, ml'. 1-1 .l hrs

Integrated Circuits-II
Max. Marks: 20

I
/ :'10 TE : Assume and mention any missing data
I Attempt any four questions.

Q I. Design a sequence detector. which allows overlapping of data I

sey uence. to detect ' 1100110 ' . (5 marks]

\
Q.2. Design a FSM with two inputs X and Y and an output Z as per
the fo ll owi ng conditions :
If Xt = I , then Z = Yt * Yt - i Figure 1
Else if Xt= 0, then Z = Yt + Yt-i
Where : * 1.s Boolean AND, + is Boolean OR. Xt and Yt are current Q4. Implement the problem in previous question as a Mealy
inputs and Yt - l is previous input. machine, again using D type flip-flops and a (64x8bits1 ROM only
a) Draw the 5tate diagram and state table. [5 marks]
bJ Jmplement the system using D type flip-flops . [5 marks]
QS . Highlight the significance of finite state machine using a block
Q3. Implement a Moore machine with one input (enb) and five diagram and discuss their capabilities and limitations . Also, prove
outputs apart from the system clock, to implement the state diagram that if a Mealy machine is strongly connected and completely
in Figure l using D type flip flops and a (64x8bits] ROM only. Show specified, the corresponding Moore machine wi\l also be strongly
the state table, -circuit diagram and contents of the ROM in support of connected and completely satisfied. [S marks)
.'- our design . Relevant ROM signals include, address bits, data bits
and chip enable and read enable signals. [5 marks]
 Total No. <?l /1agt·(sJ. Rn /I No
FIFTH SEMEST~:r~ B.E. (ICE)
B.E . MID SEM. EXAMINATl()N, SEPT.-2017
IC 303:- DIGITAL INTEGRATED CIRClHTS · I
rime: I :Jtl I frs. Max . Mark s: 20

Note: Attempt ALL question s.

1.(a) Represent (-57) n in 8-bit 2's complement form . [lj

lb) Conve11 BCD number ( 10000 IO 10 I) to binary. [ l]
(c) Use T s complement method lo perform the operation (54 5)8 - ( 17)g. [2]
(d) Represc>nt XO R ga te usin g four NANO gates only. [2]

' Reduce F (Fig. l) using laws of Boolean Al gehra and implement the reduceq
expression usin g NANO gates only. [2+2]
C

A--D
A
F
8 - -,, _ . #

B~
C

Fig. I

3. Derive the expression of F for the circuit of Fig 2. [3]

2 Xl
::-.rux 2XI
".\fL"X
y s
0 F

✓r
X
z
Fig2

4. Simpli fy F = .l:(0,1,2,3,7,13) + d( 6,15) using Tabulation method. l31

5. A complementer circuit is one which gives the complement of the input at the
output. Oesign a 1-bit BCD nine ' s complementer l'ircu it using 4-bit h inan;
adder. - 14.l
-----x--- --
-

Mid-Term Examination
M. Tech (ESV), First Semester 2017
Digital System Design using HDLs
Paper Code: ESD07

Duration : 1 Hour 30 Minutes Maximum Marks : 15

Att empt all questions. Assume any missing data suitably.

1. A Mealy sequential circuit has two inputs and one output rf the total number of O's received is 2: 4 and at least
three pairs of inputs have occurred, then the output should be I coincident with the last input pair in the sequence.
Whenever a 1 output occurs, the circuit resets. Derive a state graph and state table . 5 Marks

2 . Desigr, the controJler in Fig. 1 using T flip-flops and logic gates where x and y are the inputs. Also draw the
. I ,
equ1va ent ASM chart for the same. 5 Marks
-x~ 0

Fig . 1

3. (a) Differentiate between the following two verilog statements 5 Marks

#5 a= b;
a= #5 b;

(b) Differentiate between assign and deassign statements in verilog.

(c) Differentiate between blocking and non-blocking assignment statements.
(d} Write ve rilog code for a 4-to-2 bit priority encoder.
 \
\
M. rech {ESV) 1•t Serner»tf1r
\
MidftSemefiter Examination \
l:SDO'l : Oi~ it31 System De sign u sing HOLs \
"1 e. 1 Hour JO
· M,m
' utes

.:.
~e r-npt ail q u :->sfo
1 A
<:.: • ns. ssu rne ariy mi ss ing diJ ta suitably .
( '

- 1 . irn p lem d n't t he foll ow ing Boo lea n r·unc\lv n with a 4 X 1 rnullipl ex~ ( and extur~ii\ gat~s.

Fl (A, 8 , C, D) ;:) ~rn (1, 3, 4 , 11, 1-2, l3 , l4, 15 ). CCJ nnect inputs A and B t o the se.l ect l1ne::s .
. _.4. lso w _ri tc Ve rllog cude for the smn~ u~i!,g structural style of rnodc. lUng, l51

8(t + l) ~" ~A+ xlf

I
I .
'?, ?- A
I , .
r· t , • J• ~t t: . ' '
''.} 1,.h~W tna J., I
lGJt C Yi d 5TJ.iil o r tr1 ~ c;rCUL ,
· t:,). Ust l the stjtcl table fo r the se qu enti,d circwit.
r) Dra\-y \he correspond inc~state diagram .

~ ·. .

l,_

.
J. 3. Jnip.lernen t a _rv1oore FSM (r\Jon•overlapping) for detecting a sequence 10001 . .1.
~. nd.also_
" -- ' ,vrite. .

\;' )rilog code fc r the sanie . \ · . t3+ :~ 1

.... ,.. - · -~ ~ .. .... - -~ ~ ~ ... ... .., .., * ... ,;,, * ,., '" * * * 1k "'*"' * ~ * * * * * * * * * * * * * * * * * * ** *** "* ~ * * *,.; ~ * * * * * * ~ * * $ ** * *
>l; • ' I• •
 \....r • r-1·/ 1 6).
\\
l,o.l
l I P
, . ,,
i ;, ,: v,,. (... f A)\',J
-.• . l
'II
~
I
711 B.l~. (l~CE)
' "' SEMESTER
l\ltd S1.·mcstt.~1· .Exnm inntiuu, St·ptcml> cr 201H
! l tn C' I I ~ llt ;\
lllGITAL Cl RC lJJ l :, ANH S H,'l J:I\Hi • H tLC.tOll

1. .i) l:::,..phun how prupuyaticm dul<Jy of tut i11w rtc1 1.:uu bo wt ificd cxpe,1ihu.. htJ!ly. <1 J
b) Rl.!illi'l.c f(A,B,O) })u(O,1,2,5,6,7) using u h11z.u.r<l 1icc logic m.ttw.ark.
:,ct (iJ

l . Com·ert th(; Moure titUlt.1 dingnun l~ shown in lhi.; fi gu1i.: 1.,clow to u 1cuuc~-J \k~• l; .Adle
diugrum. Also drow tlu, state trwu,itlon tnblc for a DFF impk:mcnt,1tiun. (:S j

iJ

J. Llrnw the st.ate diagram for a sequen~c detector with output puttcrn ~s follu'.'. ~:
Input• 0 l OI 1 0 0 0 1 1 1 1 0 0 l OO1
0 1tput- 0 0 0·0 1 0 1 1 0 1 .1 1 0 1 0 0 1 0 (_5 )

D::~ign the digi4U circuH Ui.iiflg D•flip•fl op.

-1. H.~Juce the fo llo wing ~tat~ table using purtition technique i:uul draw thi: reJu.;~1.i st,::.; di..:.~r:..in
(})

PS NS.Z
X=cO ---f X;.:; l ____
- -- ---- --- - - ·---
A B,l l l.l
I3 F,l D,1
C --D,O_ ~- 1.(!1-
_!?_.~ _c,L _____ y,t
E j J.1__ ____ C. l
F _.__ C,l ~'.1
U r·,l l) 1
I1,- - l c·.u -- A,1
 ~

8 .C. (COE)
(~
l\'11 D tH~M .I.LST.GH l,1;XAJv1lNNi11.0 N, /·k pL01nbot :w l r.,
CO!!: ·102: Dig-Hul (;ircuHv mal 8y1:J tcuw IJ
lintr' Ot ·;, u H uu n.1

-umitions. AHti um u 1rnitn6J o u1i1rnin, datu, if 011 .

QI. \VrjtL: I ' )L '

VJJ1L . . .
ior Dt:cm1ul tu UL' U i.!ll<.:O ut.!r.
i 1;0Ji.i (4 )
,- . ,,.,. ~x , .
1) 1 1
' ') le . ..
1 •
' ~y,u111 th1: d1ih;r~nt (ypi.:s uf!foti.lrds (2)
(o) hid th!.! H1;t:ta1d in llw Circuit (2)
P~iy + p ·•,fr,t
~,,..,

( )3 F·,r th~ ~r0 11 owwg

· M~1chin~ dqw.
,~ · \.!. • (4 l

I. Me.rger Orµph
2. Compatibility Graph
fi nd- 111e n11n1mal
· · mac.:hine nnd show lhe state table

PS NS,i

II T?
l- 13 14
A Ell
B c,o A, l D,O
C c,o D,l A,0
E,l B,~
B,O C, ~

Q~-- (a) Find the eqi.+ivulepce partitio11 and corresponding reduced machine in the st.:mdarJ
fonri. (4)
~~~ ~ i

PS .,
NS z II
X:::: 0 X:.::: 1
A F,O G,1
ll G,O A,1
.. - .. ··~·~. ~fi··
C 0,0 C11
D c,o ... ..
~
B,l..
.. - .,,_.

I.: D,O t-\1

F E.1 1:,1
G E,1 G,1
~ ;;. .... ~,.......,..... __.........

:1':-J\~ that cqL-JivHh:nc(;p/.lrtition is Uniqt!~

-: ~ J :s:.;n an overlapping 1v1oore Sequl'ncc detector \'. hidi dct~c,s tLL·se c:p.1~nc'--: l !OU ! 1. (:~)

' ' \
•

JO. (I( .. )

\UO "fi ~K\ ·t t'k f Uft'OM V f ~AftUNA llO,-.., -..,,f,.mt,.-.-. 201M

H .ttU n•1U•t { ff"t Uft.t 11ut $\y-.,tm._ tt
f 1\ H I IU flt -.
"1H. M trio . 20

,' I t'\ft"'.• 't·mn '-"'tunt mtrtli.-.i

"'' 1n·\ ' ' 11 t·' hi ,· nH ~"lllf dntn. it ,, ,., .
\• l l r,t th
t' ~t.,h.' tnhl r nf Ch<." mnchtnl" ,riv(:.n below. find the An•Prole.-"'-e n- ttatio-n uid a
')""'f'<'rn' --,~ ~
. L, Ulf! n:ducrd mnchmr 1n ~,andnnt fonn . Abo daign the dig.jwl cu cw• re~, rnfuc~d
"'•\'
PS 1 N"i/
XO X· l
A B.1 II . I
B F. I D.l
(s -~ DJ) - E,t
j_Q__ I C,t F,1
E J_D, I- LC.1
F I C, l t C.!_

G l C, l D,1
I E 1C.Q l A 1_J
· \ ,.,n~ ..equence of pulse.-~ enters a 2-input 2-outpu _syncLmoous ~qLcnri.J cucu.r \Anlch h
x qrn red 10 prod ucc an output z= L wheneverthe sequence l 11 I 0<,·r m s. 0 lo"~ t,1J: pmg sequcncC"5
are accepted. For example, if the input is 0101111 1, th~ required output 1s ()(\){x)c,. 1 uesign th .:
"' ircuj t.

() -: Write tht. VHDL code

JI ro obtain 2 clock cycle delay

~) 3-bit synchronous counter
() 4 (a ) Define synchronous sequential machine. Write the capabilities and limitat10ns l' ~· tir- :: .;
.\" tale machine.
, h) C...onvcrt following Moore machine to its equivalent Mday machir,c Al~o ,.ksi p \.\: tj
·r~uH ror CC'l nvcrted model
 Roll no .. . . .. .
Total no of pages: 1
B.E . (ECE/CoE/ICE)
VII Semester
MID SEMESTER EXAMINATION, September 2017

EC/CoE 402: Digital Circuits and Systems -,-II; IC-402: Digital Integrated Circuits-II
Max. Marks: 20
Time: 1-1/2 hrs

Note: Assume and mention any missing data. Attempt any four questions.

Ql : Modify a DFF to include an enable signal E. IfE is' I' then transfer the input I on the rising
edge of the clock signal to the output Q. IfE is '0' then retain the last value of Q. Use Moore
model of FSM to design the system. Ensure that the implementation does not have any static
~ &. ~

Q2: Obtain merger graph and find the set of maximal compatibles for the incompletely specified
machine given below. [5]

PS NS, Z
11 12
A E, 0 B,O
B F, O A, -
C E - C, 0
'
D F, 1 D, 0 .
E C, I C -
'
F D, - B, 0

Q3 : Find equivalence partition and a corresponding reduced machine in standard form . [5] ·

PS NS, Z
11 12
A E, O D, I
B F, O D, O
C E, O B, I
D F, O B, 0
E C, 0 F, 1
F B, 0 C, 0

Q4: Design and implement even parity generator using finite state mac h.me paradigm.
. · [5]
Q5 : Design a 4-bit binary to seven se~ment decoder to display the 4-bit n . .
number on two seven segment displays. Use a suitable PROM t . umber as 2-d1g1t octal
) ( _ _ _ _ __. o implement the design . [5]
 f 11 laJ No P.a i~c(s)
11 f Roll No ...•....... .. ..

B.E. (ll)

ll. E. Mll.>-SRMF.STER f:XAMINATION , Sl( JYff,MBER 2016

11'-202 Dl11ltal CircuilJI & Systems

A1teni p1 all questions. Assume 11ny missing data suitably. MAX MARKS: 20

(a) Given F'(A. 8, C, D) .. }:m(0, I, 2, 6, 7, 13, 15).

(i) Find the mintenn expansion for F
(ii) Find the maxterm expansion for F (2)

(b) Perform the decimal subtraction in BCD by the 9's complement method (667.3),o - (882.5),o (2)

2. Minimize the following function in POS form using 5-variable K-Map

F= Lfll (0, l , 4, 5, 6, 13, 14, 15, 22, 24, 25, 28, 29, 30, 31). (4)

3 · A lawn sprinkling system is controlled automatically by certain combinations of the following variables.

Season (S = 1, if swnmer; 0, otherwise)

Mofature content of soiJ (M=l, if high; 0, if low)
Outside temperanu-e (T=l, if high; 0, if low)
Outside Humidity (H=J , if high; 0, if low)

The sprinkler is turned on under any of the following circumstances

i) The moisture content is low in winter.

ii) The temperature is high and the moisture content is low in summer
iii) The temperature is high and humidity is high in summer
iv) The temperature is low and the moisture content is low in summer
v) The temperature is high and the humidity is low

Design a combinationaJ circu.it to tum on the sprinkler system. (4)

4. Implement the following Boolean function with 4 x J multiplexer and external gates.

F = Dn (1 , 3, 4, J J, 12, 13, 14, 15) (4)

5. Using a decoder of suitable size and external gates, design the combinational circuit defined by the following
three Boolean functions: - (4)"'

(a) F = x'yz' + xz
(b) P = y'z' + x'y + yz'
 .Hu.t- 1 t~rn1 t<.xa1111nat1011
\1. Tt\ch (SP), First Sen1ester 201 7
Digital S~·ste n1 Desi~n
Paper Code: SPD04

Du.r ation ; 1 Hour 30 \tinutes Maximum Marks: 15

\ rt t'mpt J: qut"'s n n ns .-\ssuml' :ln \

..
m i.:-s ing- data suitabh.. ·.
.

' l~lr lt'm~nr J u.nn·ersa l shift reg.ist.?r with the following function table using 4x 1 multiplexers and D flip-flops .
\\ nr~ d ve;--dog code fL"'f the implementation.

\
"tode control
so
I
S1 I Reeister operation
0 i 0 No change
0 l 1 Shift right
1 i 0 Shift left
1 I 1 Parallel load
'
7 Marks

.2 . Draw L1e state graphs for both Mealy and Moore sequence detectors in order to detect the sequence 10001
(o verlapp ing). Also implement the Mealy based sequence detector using D flip-flop and logic gates.
6 Marks

3 . Differentiate between ASM and ASMD chart with example. 2 Marks

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