02/09/17

Lecture 12: VERILOG DESCRIPTION STYLES

PROF. INDRANIL SENGUPTA

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

Descrip(on Styles in Verilog

•  Two different styles of descrip>on:
1.  Data Flow
Using assignment statements.
•  Con>nuous assignment

2.  Behavioral
•  Procedural assignment Using procedural statements
–  Blocking similar to a program in high-level
language.
–  Non-blocking

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Data Flow Style: Con(nuous Assignment

•  Iden>fied by the keyword “assign”. assign a = b + c;!
assign sign = Z[15];!
•  Forms a sta>c binding between:
–  The “net” being assigned on the leR-hand side (LHS).
–  The expression on the right-hand side (RHS), which may consist of both
“net” and “register” type variables.
•  The assignment is con>nuously ac>ve:
–  Almost exclusively used to model combina>onal circuits.
–  We shall also see some examples of modeling sequen>al circuit elements.

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•  Some points to note:

–  A Verilog module can contain any number of “assign” statements.
–  Typically, the “assign” statements are followed by procedural descrip>ons.
–  The “assign” statements are used to model behavioral descrip>ons.
•  We shall illustrate various usages of “assign” statements for
modeling combina>onal and also some sequen>al logic blocks.

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module generate_MUX (data, select, out);!

input [15:0] data;!
input [3:0] select;!
output out;!
assign out = data[select];!
endmodule!
Non-constant index in
expression on RHS
generates a MUX

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•  Point to note:
–  Whenever there is an array reference on the RHS with a variable index, a
MUX is generated by the synthesis tool.
–  If the index is a constant, just a wire will be generated.
Example: assign out = data[2];!

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module generate_set_of_MUX (a, b, f, sel);!

input [0:3] a, b;!
input sel;!
output [0:3] f;!
assign f = sel ? a : b;!
endmodule!

Condi>onal operator
generates a MUX

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•  Point to note:
–  Whenever a condi>onal is encountered in the RHS of an expression, a 2-
to-1 MUX is generated.
–  In the previous example, since the variables “a”, “b” and “f” are vectors, an
array of 2-to-1 MUX-es are generated.
–  What hardware will be generated by the following?
assign f = (a==0) ? (c+d) : (c–d); !

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module generate_decoder (out, in, select);!

input in;!
input [0:1] select;!
output [0:3] out;!
assign out[select] = in;!
endmodule!

Non-constant index in
expression on LHS
generates a decoder

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•  Point to note:
–  A constant index in the expression on the LHS will not generate a decoder.
–  Example: assign out[5] = in;!
This will simply generate a wire connec>on.
–  As a rule of thumb, whenever the synthesis tool detects a variable index in
the LHS, a decoder is generated.

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En D Qn
module level_sensitive_latch (D, Q, En);!
0 x Qn-1
input D, En;!
1 0 0
output Q;!
1 1 1
assign Q = En ? D : Q;!
Generates a D-type latch
endmodule!

Here is an example to
describe a sequen>al
logic element using
“assign” statement.

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•  Modeling a simple S-R latch:

R S R Qn
Q
1 1 Qn-1
0 1 0
1 0 1
S Qbar 0 0 ?

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module sr_latch (Q, Qbar, S, R);!

input S, R;! module latchtest;!
output Q, Qbar;! reg S, R; wire Q, Qbar;!
sr_latch LAT (Q, Qbar, S, R);!
assign Q = ~(R & Qbar);!
initial!
assign Qbar = ~(S & Q);!begin!
endmodule! $monitor ($time, “S=%b R=%b, Q=%b, Qbar=%b”, !
S, R, Q, Qbar);!
S = 1’b0; R = 1’b1;!
#5 S = 1’b1; R = 1’b1;!
#5 S = 1’b1; R = 1’b0;!
#5 S = 1’b1; R = 1’b1;!
#5 S = 1’b0; R = 1’b0;!
#5 S = 1’b1; R = 1’b1;!
end!
endmodule!

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Simula>on Output
0 S=0, R=1, Q=0, Qbar=1!
5 S=1, R=1, Q=0, Qbar=1!
10 S=1, R=0, Q=1, Qbar=0!
15 S=1, R=1, Q=1, Qbar=0!
20 S=0, R=0, Q=1, Qbar=1!
and then the simulator hangs!

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END OF LECTURE 12

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Lecture 13: PROCEDURAL ASSIGNMENT

PROF. INDRANIL SENGUPTA

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

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Behavioral Style: Procedural Assignment

•  Two kinds of procedural blocks are supported in Verilog:
–  The “ini>al” block
•  Executed once at the beginning of simula>on.
•  Used only in test benches; cannot be used in synthesis.
–  The “always” block
•  A con>nuous loop that never terminates
•  The procedural block defines:
–  A region of code containing sequen7al statements.
–  The statements execute in the order they are wrijen.

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The “ini(al” Block

•  All statements inside an “ini>al” statement cons>tute an “ini>al block”.
–  Grouped inside a “begin … end” structure for mul>ple statements.
–  The statements starts at >me 0, and execute only once.
–  If there are mul>ple “ini>al” blocks, all the blocks will start to execute concurrently
at >me 0.
•  The “ini>al” block is typically used to write test benches for simula>on:
–  Specifies the s>mulus to be applied to the design-under-test (DUT).
–  Specifies how the DUT outputs are to be displayed / handled.
–  Specifies the file where the waveform informa>on is to be dumped.

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module testbench_example;!
reg a, b, cin, sum, cout;!
initial!
cin = 1’b0;!
initial!
•  The three “ini>al” blocks execute
begin! concurrently.
#5 a = 1’b1; b=1’b1;! •  The first block executes at >me 0.
#5 b = 1’b0;!
•  The third block terminates
end!
simula>on at >me 25 units.
initial!
#25 $finish;!

endmodule!

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Some Short Cuts in Declara(ons

•  “output” and “reg” can be declared together in the same statement.
output reg [7:0] data; !
instead of output [7:0] data; reg [7:0] data;!

•  A variable can be ini>alized when it is declared:

reg clock = 0;!
instead of reg clock; initial clock = 0; !

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The “always” Block

•  All behavioral statements inside an “always” statement cons>tute an “always
block”.
–  Mul>ple statements are grouped using “begin … end”.
•  An “always” statement starts at >me 0 and executes the statements inside the
block repeatedly, and never stops.
–  Used to model a block of ac>vity that is repeated indefinitely in a digital circuit.
–  For example, a clock signal that is generated con>nuously.
–  We can specify delays for simula>on; however, for real circuits, the clock generator
will be ac>ve as long as there is power supply.

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module generating_clock;!
output reg clk;! •  “ini>al” and “always
blocks can coexist within
initial!
clk = 1’b0; // initialized to 0 at time 0! the same Verilog module.
•  They all execute
always!
concurrently; “ini>al”
#5 clk = ~clk; // Toggle after time 5 units!
only once and “always”
initial! repeatedly.
#500 $finish;!
endmodule!

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•  A module can contain any number of

Basic syntax of “always” block:
“always” blocks, all of which execute
concurrently. always @(event_expression)!
•  The @(event_expression) part is begin!
required for both combina>onal and sequential_statement_1;!
sequen>al circuit descrip>ons. sequential_statement_2;!
…!
sequential_statement_n;!
end!

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•  Only “reg” type variable can be assigned within an “ini>al” or ‘always” block.
•  Basic reason:
–  The sequen>al “always” block executes only when the event expression triggers.
–  At other >mes the block is doing nothing.
–  An object being assigned to must therefore remember the last value assigned (not
con>nuously driven).
–  So, only “reg” type variables can be assigned within the “always” block.
–  Of course, any kind of variable may appear in the event expression (reg, wire, etc.).

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Sequen(al Statements in Verilog

•  In Verilog, one of more sequen>al statements can be present
inside an “ini>al” or “always” block.
–  The statements are executed sequen>ally.
–  Mul>ple assignment statements inside a “begin … end” block may either
execute sequen>ally or concurrently depending upon on the type of
assignment.
•  Two types of assignment statements: blocking (a = b + c;) or non-blocking
(a <= b + c;).
•  The sequen>al statements are explained next.

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(a) begin … end

begin! •  A number of sequen>al

sequential_statement_1;! statements can be grouped
sequential_statement_2;! together using “begin .. end”.
…!
•  If n=1, “begin … end” is not
sequential_statement_n;!
required.
end!

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(b) if … else if (<expression1>)!

sequential_statement;!
if (<expression>)! else if (<expression2>)!
sequential_statement;! sequential_statement;!
else if (<expression3>)!
if (<expression>)!
sequential_statement;!
sequential_statement;!
else default_statement;!
else!
sequential_statement;!
•  Each sequen>al_statement can be
a single statement or a group of
statements within “begin … end”.

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(c) case
case (<expression>)! •  Each sequen>al_statement can be
expr1: sequential_statement;! a single statement or a group of
expr2: sequential_statement;! statements within “begin … end”.
...! •  Can replace a complex “if … else”
statement for mul>way branching.
exprn: sequential_statement;!
•  The expression is compared to the
default: default_statement;!
alterna>ves (expr1, expr2, etc.) in
endcase!
the order they are wrijen.
•  If none of the alterna>ves matches,
the default statement is executed.

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•  Two varia>ons: “casez” and “casex”.

–  The “casez” statement treats all “z” values in the case alterna>ves or the
case expression as don’t cares.
–  The “casex” statement treats all “x” and “z” values in the case item as
don’t cares.
reg [3:0] state; integer next_state;!
casex (state)!
If state is “4’b01zx”, the 4’b1xxx : next_state = 0;!
second expression will 4’bx1xx : next_state = 1;!
give match, and 4’bxx1x : next_state = 2;!
next_state will be 1. 4’bxxx1 : next_state = 3;!
default : next_state = 0;!
endcase!

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END OF LECTURE 13

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Lecture 14: PROCEDURAL ASSIGNMENT (CONTD.)

PROF. INDRANIL SENGUPTA

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

(d) “while” loop

while (<expression>)! Example:

sequential_statement;!
integer mycount;!
•  The “while” loop executes un>l the initial!
expression is not true. begin!
while (mycount <= 255)!
•  The sequen>al_statement can be a begin!
single statement or a group of $display (“My count:%d”, mycount);!
statements within “begin … end”. mycount = mycount + 1;!
end!
end!

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(e) “for” loop

•  The “for” loop consists of three parts:
for (expr1; expr2; expr3)!
a)  An ini>al condi>on (expr1).
sequential_statement;!
b)  A check to see if the termina>ng condi>on
•  The “for” loop executes as long as is true (expr2).
the expression expr2 is true. c)  A procedural assignment to change the
•  The sequen>al_statement can be value of the control variable (expr3).
a single statement or a group of •  The “for” loop can be conveniently used to
statements within “begin … end”. ini>alize an array or memory.

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Example:

integer mycount;!
reg [100:1] data;!
integer i;!
initial!
for (mycount=0; mycount<=255; mycount=mycount+1)!
$display (“My count:%d”, mycount);!
initial!
for (i=1; i<=100; i=i+1)!
data[i] = 1’b0;!

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(f) “repeat” loop

repeat (<expression>)! •  The expression in the “repeat” construct can

be a constant, a variable or a signal value.
sequential_statement;!
•  If it is a variable or a signal value, it is
evaluated only when the loop starts and
•  The “repeat” construct executes the not during execu>on of the loop.
loop a fixed number of >mes.
•  The sequen>al_statement can be a single
•  It cannot be used to loop on a general statement or a group of statements within
logical expression like “while”. “begin … end”.

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Example:

reg clock;! Exactly 100 clock pulses
initial! are generated.
begin!
clock = 1’b0;!
repeat (100)!
#5 clock = ~clock;!
end!

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(g) “forever” loop

forever!
sequential_statement;! •  The “forever” construct does not use any
expression and executes forever un>l $finish is
•  The “forever” loop is typically used encountered in the test bench.
along with >ming specifier. •  Equivalent to a “while” loop for which the
•  If delay is not specified, the expression is always true.
simulator would execute this •  The sequen>al_statement can be a single
statement indefinitely without statement or a group of statements within
advancing $>me. “begin … end”.
•  Rest of design will never be
executed.

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// Clock generation using “forever” construct!

reg clk;!
initial!
begin!
clk = 1’b0;!
forever #5 clk = ~clk; // Clock period of 10 units!
end!

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Other Constructs Available

# (time_value)! •  Makes a block suspend for “>me_value” units of

>me.
•  The >me unit can be specified using the `>mescale
command.

@ (event_expression)! •  Makes a block suspend un>l “event_expression”

triggers.
•  Various keywords associated with “event_expression”
shall be discussed with examples..

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@ (event_expression)
•  The event expression specifies the event that is required to resume execu>on
of the procedural block.
•  The event can be any one of the following:
a)  Change of a signal value.
b)  Posi>ve or nega>ve edge occurring on signal (posedge or negedge).
c)  List of above-men>oned events, separated by “or” or comma.
•  A “posedge” is any transi>on from {0, x, z} to 1, and from 0 to {z, x}.
•  A “negedge” is any transi>on from {1, x, z} to 0, and from 1 to {z, x}.

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•  Examples:
–  @ (in) // “in” changes
–  @ (a or b or c) // any of “a”, “b”, “c” changes
–  @ (a, b, c) // -- do --
–  @ (posedge clk) // posi>ve edge of “clk”
–  @ (posedge clk or negedge reset) // posi>ve edge of “clk” or nega>ve
edge of “reset”
–  @ (*) // any variable changes

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// D flip-flop with synchronous set and reset !

module dff (q, qbar, d, set, reset, clk);!
input d, set, reset, clk;!
output reg q; output qbar;!
assign qbar = ~q;!
always @ (posedge clk)!
begin!
if (reset == 0) q <= 0;!
else if (set == 0) q <= 1;!
else q <= d;!
end!
endmodule!

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// D flip-flop with asynchronous set and reset !

module dff (q, qbar, d, set, reset, clk);!
input d, set, reset, clk;!
output reg q; output qbar;!
assign qbar = ~q;!
always @ (posedge clk or negedge set or negedge reset)!
begin!
if (reset == 0) q <= 0;!
else if (set == 0) q <= 1;!
else q <= d;!
end!
endmodule!

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// Transparent latch with enable!

module latch (q, qbar, din, enable);!
input din, enable;!
output reg q; output qbar;!
assign qbar = ~q;!
always @ (din or enable)!
begin!
if (enable) q = din;!
end!
endmodule!

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END OF LECTURE 14

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Lecture 15: PROCEDURAL ASSIGNMENT (EXAMPLES)

PROF. INDRANIL SENGUPTA

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

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// A combinational logic example!

module mux21 (in1, in0, s, f);! •  The event expression in the
input in1, in0, s;! “always” block triggers whenever at
output reg f;! least one of “in1”, “in0” or “s”
! changes.
always @(in1 or in0 or s)! •  The “or” keyword specifies the
if (s)! condi>on.
f = in1;!
else!
f = in0;!
endmodule!

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// A combinational logic example!

module mux21 (in1, in0, s, f);! •  An alternate way to specify the
input in1, in0, s;! event condi>on by using comma
output reg f;! instead of “or”.
! •  Supported in later versions of
always @(in1, in0, s)! Verilog.
if (s)!
f = in1;!
else!
f = in0;!
endmodule!

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// A combinational logic example!

module mux21 (in1, in0, s, f);! •  An alternate way to specify the
input in1, in0, s;! event condi>on by using a “*”
output reg f;! instead of naming the variables.
! •  “*” is ac>vated whenever any of
always @(*)! the variables change.
if (s)!
f = in1;!
else!
f = in0;!
endmodule!

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// A sequential logic example!

!
module dff_negedge (D, clock, Q, Qbar);!
•  The keyword “negedge”
input D, clock;! means at the nega>ve going
output reg Q, Qbar;! edge of the specified signal.
always @(negedge clock)! •  Similarly, we can use
begin! “posedge”.
Q = D;! •  We can combine various
Qbar = ~D;! triggering condi>ons by
end! separa>ng them by commas
endmodule! or “or”.

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// 4-bit counter with asynchronous

reset!
module counter (clk, rst, count);!
input clk, rst;! The event condi>on triggers
output reg [3:0] count;! when either a posi>ve edge of
“clk” comes, or a posi>ve edge
always @(posedge clk or posedge rst) ! of “rst”.
begin!
if (rst) !
count <= 0;!
else!
count <= count + 1;!
end!
endmodule!

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// Another sequential logic example!

!
module incomp_state_spec (curr_state, flag);!
input [0:1] curr_state;!
output reg [0:1] flag;!
!
always @(curr_state)!
case (curr_state)! The variable “flag” is not
0,1 : flag = 2;! assigned a value in all the
3 : flag = 0;! branches of the “case”
endcase! statement.
endmodule! •  A latch (2-bit) will be
generated for “flag”.

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// A small modification!
!
module incomp_state_spec (curr_state, flag);!
input [0:1] curr_state;!
output reg [0:1] flag;!
!
always @(curr_state)!
begin! Here the variable “flag” is
flag = 0;! defined for all the possible
case (curr_state)! values of “curr_state”.
0,1 : flag = 2;! •  A pure combina>onal circuit
3 : flag = 0;! will be generated.
endcase! •  The latch is avoided.
end!
endmodule!

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•  When a “case” statement is incompletely decoded, the synthesis

tool will infer the need for a latch to hold the residual output
when the select bits take the unspecified values.
–  It is up to the designer to code the design in such a way that latch can be
avoided where possible.

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// A simple 4-function ALU!

module ALU_4bit (f, a, b, op); !
input [1:0] op; input [7:0] a, b;!
output reg [7:0] f; !
parameter ADD=2’b00, SUB=2’b01, MUL=2’b10, DIV=2’b11;!
always @(*)!
case (op)!
ADD : f = a + b;!
SUB : f = a – b;!
MUL : f = a * b;!
DIV : f = a / b;!
endcase!
endmodule!

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module priority_encoder (in, code);!

input [7:0] in;!
output reg [2:0] code;!
always @(in)!
•  The inputs bits are checked
begin!
sequen>ally one by one (in order of
if (in[0]) code = 3’b000;!
priority).
else if (in[1]) code = 3’b001;!
else if (in[2]) code = 3’b010;! •  “in[0]” has the highest priority.
else if (in[3]) code = 3’b011;! •  For simultaneously ac>ve inputs,
else if (in[4]) code = 3’b100;! the first ac>ve input
else if (in[5]) code = 3’b101;! encountered will be encoded.
else if (in[6]) code = 3’b110;!
else if (in[7]) code = 3’b111;!
else code = 3’bxxx;!
end!
endmodule!

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module bcd_to_7seg (bcd, seg);!

input [3:0] bcd;! a
output reg [6:0] seg;!
always @(bcd)! f b
g
case!
0: seg = 6’b0000001;! e c
1: seg = 6’b1001111;!
2: seg = 6’b0010010;! d
3: seg = 6’b0000110;!
4: seg = 6’b1001100;!
5: seg = 6’b0100100;! Segment bit assignment:
6: seg = 6’b0100000;! (a, b, c, d, e, f, g)
7: seg = 6’b0001111;!
8: seg = 6’b0000000;! A segment glows when the
9: seg = 6’b0000100;! corresponding bit of seg is 0.
default : seg = 6’b1111111;!
endcase!
endmodule!
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// An n-bit comparator!
module compare (A, B, lt, gt, eq);!
parameter word_size = 16;!
input [word_size-1:0] A, B;! For actual synthesis, it is
output reg lt, gt, eq;! common to have a structured
design representa>on of the
always @ (*)!
comparator.
begin!
gt = 0; lt = 0; eq = 0;!
if (A > B) gt = 1;!
else if (A < B) lt = 1;!
else eq = 1!
end!
endmodule!

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// A 2-bit comparator!
module compare (A1, A0, B1, B0, lt, gt, eq);!
input A1, A0, B1, B0;!
output reg lt, gt, eq;!
always @ (A1, A0, B1, B0)!
begin!
lt = ({A1,A0) < {B1,B0});!
gt = ({A1,A0) > {B1,B0});!
eq = ({A1,A0) == {B1,B0});!
end!
endmodule!

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module alu_example (alu_out, A, B, operation, en);!

input [2:0] operation; input [7:0] A, B;!
input en;!
output [7:0] alu_out; reg [7:0] alu_reg;!
!
assign alu_out = (en == 1) ? alu_reg : 4’bz;!
always @ (*)!
case (operation)!
3’b000 : alu_reg = A + B;!
3’b001 : alu_reg = A – B;!
3’b011 : alu_reg = ~ A;!
default : alu_reg = 4’b0;!
endcase!
endmodule!

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END OF LECTURE 15

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