Freescale Semiconductor Document Number: MCIMX35SR2CEC

Data Sheet: Technical Data Rev. 10, 06/2012

IMX35

Package Information
Plastic Package
i.MX35 Applications Case 5284 17 x 17 mm, 0.8 mm Pitch

Processors for
Industrial and Ordering Information
See Table 1 on page 3 for ordering information.

Consumer Products

1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 Introduction 1.1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 3
The i.MX353 and the i.MX357 multimedia applications 1.3. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
processors represent the next generation of ARM11 2 Functional Description and Application Information. . . . . . 4
2.1. Application Processor Domain Overview . . . . . . . . . 5
products with the right performance and integration to 2.2. Shared Domain Overview . . . . . . . . . . . . . . . . . . . . 6
address applications within the industrial and consumer 2.3. Advanced Power Management Overview . . . . . . . . 6
2.4. ARM11 Microprocessor Core. . . . . . . . . . . . . . . . . . 6
markets for applications such as HMI and display 2.5. Module Inventory . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
controllers. Unless otherwise specified, the material in 3. Signal Descriptions: Special Function Related Pins . . . . 12
this data sheet is applicable to both the i.MX353 and 4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1. i.MX35 Chip-Level Conditions . . . . . . . . . . . . . . . . 12
i.MX357 devices and referred to singularly throughout 4.2. Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
this document as i.MX35 or MCIMX35. The i.MX353 4.3. Supply Power-Up/Power-Down Requirements and
Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
devices do not include a graphics processing unit 4.4. Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
(GPU). For information on i.MX35 devices for 4.5. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . 18
automotive applications, please refer to document 4.6. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . 19
4.7. I/O Pin DC Electrical Characteristics . . . . . . . . . . . 20
number, MCIMX35SR2AEC. 4.8. I/O Pin AC Electrical Characteristics . . . . . . . . . . . 23
4.9. Module-Level AC Electrical Specifications . . . . . . . 29
The i.MX35 processor takes advantage of the 5. Package Information and Pinout . . . . . . . . . . . . . . . . . . 130
ARM1136JF-S™ core running at 532 MHz that is 5.1. MAPBGA Production Package 1568-01, 17 × 17 mm,
0.8 Pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
boosted by a multi-level cache system and integrated 5.2. MAPBGA Signal Assignments . . . . . . . . . . . . . . . 132
features such as LCD controller, Ethernet, and graphics 6. Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . 144
acceleration for creating rich user interfaces. 7. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

The i.MX35 supports connections to various types of

external memories, such as SDRAM, mobile DDR, and
DDR2, SLC and MCL NAND Flash, NOR Flash and

© Freescale Semiconductor, Inc., 2010. All rights reserved.

SRAM. The devices can be connected to a variety of external devices such as USB 2.0 OTG, ATA,
MMC/SDIO, and Compact Flash.

1.1 Features
It provides low-power solutions for applications demanding high-performance multimedia and graphics.
The i.MX35 is based on the ARM1136 platform, which has the following features:
• ARM1136JF-S processor, version r1p3
• 16-Kbyte L1 instruction cache
• 16-Kbyte L1 data cache
• 128-Kbyte L2 cache, version r0p4
• 128 Kbytes of internal SRAM
• Vector floating point unit (VFP11)
To boost multimedia performance, the following hardware accelerators are integrated:
• Image processing unit (IPU)
• OpenVG 1.1 graphics processing unit (GPU) (not available for the MCIMX351)
The MCIMX35 provides the following interfaces to external devices (some of these interfaces are muxed
and not available simultaneously):
• 2 controller area network (CAN) interfaces
• 2 SDIO/MMC interfaces, 1 SDIO/CE-ATA interface (CE-ATA is not available for the MCIMX351)
• 32-bit mobile DDR, DDR2 (4-bank architecture), and SDRAM (up to 133 MHz)
• 2 configurable serial peripheral interfaces (CSPI) (up to 52 Mbps each)
• Enhanced serial audio interface (ESAI)
• 2 synchronous serial interfaces (SSI)
• Ethernet MAC 10/100 Mbps
• 1 USB 2.0 host with ULPI interface or internal full-speed PHY. Up to 480 Mbps if external HS
PHY is used.
• 1 USB 2.0 OTG (up to 480 Mbps) controller with internal high-speed OTG PHY
• Flash controller—MLC/SLC NAND and NOR
• GPIO with interrupt capabilities
• 3 I2C modules (up to 400 Kbytes each)
• JTAG
• Key pin port
• Asynchronous sample rate converter (ASRC)
• 1-Wire
• Parallel camera sensor (4/8/10/16-bit data port for video color models: YCC, YUV, 30 Mpixels/s)
• Parallel display (primary up to 24-bit, 1024 x 1024)
• Parallel ATA (up to 66 Mbytes) (not available for the MCIMX351)

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 • PWM
• SPDIF transceiver
• 3 UART (up to 4.0 Mbps each)

1.2 Ordering Information

Table 1 provides the ordering information for the i.MX35 processors for consumer and industrial
applications.
Table 1. Ordering Information

Operating Signal Ball

Silicon
Description Part Number Package1 Speed Temperature Map Ball Map
Revision
Range (°C) Locations

i.MX353 MCIMX353CVM5B 2.0 5284 532 MHz –40 to 85 Table 94 Table 96

i.MX353 MCIMX353DVM5B 2.0 5284 532 MHz –20 to 70 Table 94 Table 96

i.MX357 MCIMX357CVM5B 2.0 5284 532 MHz –40 to 85 Table 94 Table 96

i.MX357 MCIMX357DVM5B 2.0 5284 532 MHz –20 to 70 Table 94 Table 96

i.MX353 MCIMX353CJQ5C 2.1 5284 532MHz -40 to 85 Table 95 Table 97

i.MX353 MCIMX353DJQ5C 2.1 5284 532MHz -20 to 70 Table 95 Table 97

i.MX357 MCIMX357CJQ5C 2.1 5284 532MHz -40 to 85 Table 95 Table 97

i.MX357 MCIMX357DJQ5C 2.1 5284 532MHz -20 to 70 Table 95 Table 97

1 Case 5284 is RoHS-compliant, lead-free, MSL = 3, 1.

The ball map for silicon revision 2.1 is different than the ballmap for silicon revision 2.0. The layout for
each revision is not compatible, so it is important that the correct ballmap be used to implement the layout.
See Section 5, “Package Information and Pinout.”
Table 2 shows the functional differences between the different parts in the i.MX35 family.
Table 2. Functional Differences in the i.MX35 Parts

Module MCIMX351 MCIMX353 MCIMX355 MCIMX356 MCIMX357

I2C (3) Yes Yes Yes Yes Yes

CSPI (2) Yes Yes Yes Yes Yes

SSI/I2S (2) Yes Yes Yes Yes Yes

ESAI Yes Yes Yes Yes Yes

SPDIF I/O Yes Yes Yes Yes Yes

USB HS Host Yes Yes Yes Yes Yes

USB OTG Yes Yes Yes Yes Yes

FlexCAN (2) Yes Yes Yes Yes Yes

MLB Yes Yes Yes Yes Yes

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 Table 2. Functional Differences in the i.MX35 Parts (continued)

Module MCIMX351 MCIMX353 MCIMX355 MCIMX356 MCIMX357

Ethernet Yes Yes Yes Yes Yes

1-Wire Yes Yes Yes Yes Yes

KPP Yes Yes Yes Yes Yes

SDIO/MMC (2) Yes Yes Yes Yes Yes

SDIO/Memory Stick Yes Yes Yes Yes Yes

External Memory Controller (EMC) Yes Yes Yes Yes Yes

JTAG Yes Yes Yes Yes Yes

PATA — Yes Yes Yes Yes

CE-ATA — Yes Yes Yes Yes

Image Processing Unit (IPU) (inversion — Yes Yes Yes Yes

and rotation, pre- and post-processing,
camera interface, blending, display
controller)

Open VG graphics acceleration (GPU) — Yes — Yes Yes

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1.3 Block Diagram
Figure 1 is the i.MX35 simplified interface block diagram.

DDR2/SDDR NOR NAND Camera LCD Display 1 External Graphics

RAM Flash/ Flash Sensor Accelerator
PSRAM LCD Display 2

External Memory
Interface (EMI)
Image
Processing Unit
(IPU)

Smart
DMA ARM11 ARM1136 Platform Peripherals
Platform
ARM1136JF-S SSI HS USBOTG
SPBA VFP HS USBOTGPHY
AUDMUX
L1 I/D cache HS USBHost
L2 cache I2C(3) FS USBPHY
Peripherals UART(2)
AVIC
MSHC ESAI GPU 2D
MAX CSPI
SPDIF
AIPS (2) eSDHC(3)
SSI
ETM
ASRC CAN(2) ECT
UART
CSPI IOMUX
Internal
ATA Memory IIM GPIO(3)
FEC RTICv3
RNGC EPIT
SCC

Timers
KPP RTC
PWM WDOG
3 FuseBox OWIRE GPT

Audio/Power MMC/SDIO Connectivity

JTAG Bluetooth Keypin Access
Management or WLAN

Figure 1. i.MX35 Simplified Interface Block Diagram

2 Functional Description and Application Information

The i.MX35 consists of the following major subsystems:
• ARM1136 Platform—AP domain
• SDMA Platform and EMI—Shared domain

2.1 Application Processor Domain Overview

The applications processor (AP) and its domain are responsible for running the operating system and
applications software, providing the user interface, and supplying access to integrated and external
peripherals. The AP domain is built around an ARM1136JF-S core with 16-Kbyte instruction and data L1
caches, an MMU, a 128-Kbyte L2 cache, a multiported crossbar switch, and advanced debug and trace
interfaces.

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The i.MX35 core is intended to operate at a maximum frequency of 532 MHz to support the required
multimedia use cases. Furthermore, an image processing unit (IPU) is integrated into the AP domain to
offload the ARM11 core from performing functions such as color space conversion, image rotation and
scaling, graphics overlay, and pre- and post-processing.
The functionality of AP Domain peripherals includes the user interface; the connectivity, display, security,
and memory interfaces; and 128 Kbytes of multipurpose SRAM.

2.2 Shared Domain Overview

The shared domain is composed of the shared peripherals, a smart DMA engine (SDMA) and a number of
miscellaneous modules. For maximum flexibility, some peripherals are directly accessible by the SDMA
engine.
The i.MX35 has a hierarchical memory architecture including L1 caches and a unified L2 cache. This
reduces the bandwidth demands for the external bus and external memory. The external memory
subsystem supports a flexible external memory system, including support for SDRAM (SDR, DDR2 and
mobile DDR) and NAND Flash.

2.3 Advanced Power Management Overview

To address the continuing need to reduce power consumption, the following techniques are incorporated
in the i.MX35:
• Clock gating
• Power gating
• Power-optimized synthesis
• Well biasing
The insertion of gating into the clock paths allows unused portions of the chip to be disabled. Because
static CMOS logic consumes only leakage power, significant power savings can be realized.
“Well biasing” is applying a voltage that is greater than VDD to the nwells, and one that is lower than VSS
to the pwells. The effect of applying this well back bias voltage reduces the subthreshold channel leakage.
For the 90-nm digital process, it is estimated that the subthreshold leakage is reduced by a factor of ten
over the nominal leakage. Additionally, the supply voltage for internal logic can be reduced from 1.4 V to
1.22 V.

2.4 ARM11 Microprocessor Core

The CPU of the i.MX35 is the ARM1136JF-S core, based on the ARM v6 architecture. This core supports
the ARM Thumb® instruction sets, features Jazelle® technology (which enables direct execution of Java
byte codes) and a range of SIMD DSP instructions that operate on 16-bit or 8-bit data values in 32-bit
registers.
The ARM1136JF-S processor core features are as follows:
• Integer unit with integral EmbeddedICE™ logic
• Eight-stage pipeline

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 • Branch prediction with return stack
• Low-interrupt latency
• Instruction and data memory management units (MMUs), managed using micro TLB structures
backed by a unified main TLB
• Instruction and data L1 caches, including a non-blocking data cache with hit-under-miss
• Virtually indexed/physically addressed L1 caches
• 64-bit interface to both L1 caches
• Write buffer (bypassable)
• High-speed Advanced Micro Bus Architecture (AMBA)™ L2 interface
• Vector floating point co-processor (VFP) for 3D graphics and hardware acceleration of other
floating-point applications
• ETM™ and JTAG-based debug support
Table 3 summarizes information about the i.MX35 core.
Table 3. i.MX35 Core

Core Core Integrated Memory

Brief Description
Acronym Name Features

ARM11 or ARM1136 The ARM1136™ platform consists of the ARM1136JF-S core, the ETM • 16-Kbyte
ARM1136 Platform real-time debug modules, a 6 × 5 multi-layer AHB crossbar switch (MAX), and instruction cache
a vector floating processor (VFP). • 16-Kbyte data
The i.MX35 provides a high-performance ARM11 microprocessor core and cache
highly integrated system functions. The ARM Application Processor (AP) and • 128-Kbyte L2
other subsystems address the needs of the personal, wireless, and portable cache
product market with integrated peripherals, advanced processor core, and • 32-Kbyte ROM
power management capabilities. • 128-Kbyte RAM

2.5 Module Inventory

Table 4 shows an alphabetical listing of the modules in the MCIMX35. For extended descriptions of the
modules, see the MCIMX35 reference manual.
Table 4. Digital and Analog Modules

Block
Block Name Domain1 Subsystem Brief Description
Mnemonic

1-WIRE 1-Wire ARM ARM1136 1-Wire provides the communication line to a 1-Kbit add-only
interface platform memory. the interface can send or receive 1 bit at a time.
peripherals
ASRC Asynchronous SDMA Connectivity The ASRC is designed to convert the sampling rate of a signal
sample rate peripherals associated to an input clock into a signal associated to a different
converter output clock. It supports a concurrent sample rate conversion of
about –120 dB THD+N. The sample rate conversion of each
channel is associated to a pair of incoming and outgoing sampling
rates.

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 Table 4. Digital and Analog Modules (continued)

Block
Block Name Domain1 Subsystem Brief Description
Mnemonic

ATA ATA module SDMA Connectivity The ATA block is an AT attachment host interface. Its main use is to
peripherals interface with IDE hard disk drives and ATAPI optical disk drives. It
interfaces with the ATA device over a number of ATA signals.

AUDMUX Digital audio ARM Multimedia The AUDMUX is a programmable interconnect for voice, audio, and
mux peripherals synchronous data routing between host serial interfaces (SSIs) and
peripheral serial interfaces (audio codecs). The AUDMUX has two
sets of interfaces: internal ports to on-chip peripherals and external
ports to off-chip audio devices. Data is routed by configuring the
appropriate internal and external ports.

CAN(2) CAN module ARM Connectivity The CAN protocol is primarily designed to be used as a vehicle
peripherals serial data bus running at 1 Mbps.

CCM Clock control ARM Clocks This block generates all clocks for the peripherals in the SDMA
module platform. The CCM also manages ARM1136 platform low-power
modes (WAIT, STOP), disabling peripheral clocks appropriately for
power conservation, and provides alternate clock sources for the
ARM1136 and SDMA platforms.

CSPI(2) Configurable SDMA, Connectivity This module is a serial interface equipped with data FIFOs; each
serial ARM peripherals master/slave-configurable SPI module is capable of interfacing to
peripheral both serial port interface master and slave devices. The CSPI ready
interface (SPI_RDY) and slave select (SS) control signals enable fast data
communication with fewer software interrupts.

ECT Embedded SDMA, Debug ECT (embedded cross trigger) is an IP for real-time debug
cross trigger ARM purposes. It is a programmable matrix allowing several subsystems
to interact with each other. ECT receives signals required for
debugging purposes (from cores, peripherals, buses, external
inputs, and so on) and propagates them (propagation programmed
through software) to the different debug resources available within
the SoC.

EMI External SDMA External The EMI module provides access to external memory for the ARM
memory memory and other masters. It is composed of the following main
interface interface submodules:
M3IF—provides arbitration between multiple masters requesting
access to the external memory.
SDRAM CTRL—interfaces to mDDR, DDR2 (4-bank architecture
type), and SDR interfaces.
NANDFC—provides an interface to NAND Flash memories.
WEIM—interfaces to NOR Flash and PSRAM.

EPIT(2) Enhanced ARM Timer Each EPIT is a 32-bit “set-and-forget” timer that starts counting after
periodic peripherals the EPIT is enabled by software. It is capable of providing precise
interrupt timer interrupts at regular intervals with minimal processor intervention. It
has a 12-bit prescaler to adjust the input clock frequency to the
required time setting for the interrupts, and the counter value can be
programmed on the fly.

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 Table 4. Digital and Analog Modules (continued)

Block
Block Name Domain1 Subsystem Brief Description
Mnemonic

ESAI Enhanced SDMA Connectivity The enhanced serial audio interface (ESAI) provides a full-duplex
serial audio peripherals serial port for serial communication with a variety of serial devices,
interface including industry-standard codecs, SPDIF transceivers, and other
DSPs. The ESAI consists of independent transmitter and receiver
sections, each section with its own clock generator.

eSDHCv2 Enhanced ARM Connectivity The eSDHCv2 consists of four main modules: CE-ATA, MMC, SD
(3) secure digital peripherals and SDIO. CE-ATA is a hard drive interface that is optimized for
host controller embedded applications of storage. The MultiMediaCard (MMC) is a
universal, low-cost, data storage and communication media to
applications such as electronic toys, organizers, PDAs, and smart
phones. The secure digital (SD) card is an evolution of MMC and is
specifically designed to meet the security, capacity, performance,
and environment requirements inherent in emerging audio and
video consumer electronic devices. SD cards are categorized into
Memory and I/O. A memory card enables a copyright protection
mechanism that complies with the SDMI security standard. SDIO
cards provide high-speed data I/O (such as wireless LAN via SDIO
interface) with low power consumption.
Note: CE-ATA is not available for the MCIMX351.

FEC Ethernet SDMA Connectivity The Ethernet media access controller (MAC) is designed to support
peripherals both 10 and 100 Mbps Ethernet/IEEE 802.3 networks. An external
transceiver interface and transceiver function are required to
complete the interface to the media

GPIO(3) General ARM Pins Used for general purpose input/output to external ICs. Each GPIO
purpose I/O module supports 32 bits of I/O.
modules

GPT General ARM Timer Each GPT is a 32-bit free-running or set-and-forget mode timer with
purpose timers peripherals a programmable prescaler and compare and capture registers. A
timer counter value can be captured using an external event and can
be configured to trigger a capture event on either the leading or
trailing edges of an input pulse. When the timer is configured to
operate in set-and-forget mode, it is capable of providing precise
interrupts at regular intervals with minimal processor intervention.
The counter has output compare logic to provide the status and
interrupt at comparison. This timer can be configured to run either
on an external clock or on an internal clock.

GPU2D Graphics ARM Multimedia This module accelerates OpenVG and GDI graphics.
processing unit peripherals Note: Not available for the MCIMX351.
2Dv1

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 Table 4. Digital and Analog Modules (continued)

Block
Block Name Domain1 Subsystem Brief Description
Mnemonic

I2C(3) I2C module ARM ARM1136 Inter-integrated circuit (I2C) is an industry-standard, bidirectional
platform serial bus that provides a simple, efficient method of data exchange,
peripherals minimizing the interconnection between devices. I2C is suitable for
applications requiring occasional communications over a short
distance among many devices. The interface operates at up to
100 kbps with maximum bus loading and timing. The I2C system is
a true multiple-master bus, with arbitration and collision detection
that prevent data corruption if multiple devices attempt to control the
bus simultaneously. This feature supports complex applications with
multiprocessor control and can be used for rapid testing and
alignment of end products through external connections to an
assembly-line computer.

IIM IC ARM Security The IIM provides the primary user-visible mechanism for interfacing
identification modules with on-chip fuse elements. Among the uses for the fuses are
module unique chip identifiers, mask revision numbers, cryptographic keys,
and various control signals requiring a fixed value.

IOMUX External ARM Pins Each I/O multiplexer provides a flexible, scalable multiplexing
signals and pin solution with the following features:
multiplexing • Up to eight output sources multiplexed per pin
• Up to four destinations for each input pin
• Unselected input paths held at constant levels for reduced power
consumption

IPUv1 Image ARM Multimedia The IPU supports video and graphics processing functions. It also
processing unit peripherals provides the interface for image sensors and displays. The IPU
performs the following main functions:
• Preprocessing of data from the sensor or from the external
system memory
• Postprocessing of data from the external system memory
• Post-filtering of data from the system memory with support of the
MPEG-4 (both deblocking and deringing) and H.264 post-filtering
algorithms
• Displaying video and graphics on a synchronous (dumb or
memory-less) display
• Displaying video and graphics on an asynchronous (smart)
display
• Transferring data between IPU sub-modules and to/from the
system memory with flexible pixel reformatting

KPP Keypin port ARM Connectivity Can be used for either keypin matrix scanning or general purpose
peripherals I/O.

OSCAUD OSC audio Analog Clock The OSCAUDIO oscillator provides a stable frequency reference for
reference the PLLs. This oscillator is designed to work in conjunction with an
oscillator external 24.576-MHz crystal.

OSC24M OSC24M Analog Clock The signal from the external 24-MHz crystal is the source of the
24-MHz CLK24M signal fed into USB PHY as the reference clock and to the
reference real time clock (RTC).
oscillator

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 Table 4. Digital and Analog Modules (continued)

Block
Block Name Domain1 Subsystem Brief Description
Mnemonic

MPLL Digital SDMA Clocks DPLLs are used to generate the clocks:
PPLL phase-locked MCU PLL (MPLL)—programmable
loops Peripheral PLL (PPLL)—programmable

PWM Pulse-width ARM ARM1136 The pulse-width modulator (PWM) is optimized to generate sound
modulator platform from stored sample audio images; it can also generate tones.
peripherals

RTC Real-time ARM Clocks Provides the ARM1136 platform with a clock function (days, hours,
clock minutes, seconds) and includes alarm, sampling timer, and minute
stopwatch capabilities.

SDMA Smart DMA SDMA System The SDMA provides DMA capabilities inside the processor. It is a
engine controls shared module that implements 32 DMA channels and has an
interface to connect to the ARM1136 platform subsystem, EMI
interface, and the peripherals.

SJC Secure JTAG ARM Pins The secure JTAG controller (SJC) provides debug and test control
controller with maximum security.

SPBA SDMA SDMA System The SPBA controls access to the SDMA peripherals. It supports
peripheral bus controls shared peripheral ownership and access rights to an owned
arbiter peripheral.

S/PDIF Serial audio SDMA Connectivity Sony/Philips digital transceiver interface

interface peripherals

SSI(2) Synchronous SDMA, Connectivity The SSI is a full-duplex serial port that allows the processor
serial interface ARM(2) peripherals connected to it to communicate with a variety of serial protocols,
including the Freescale Semiconductor SPI standard and the I2C
sound (I2S) bus standard. The SSIs interface to the AUDMUX for
flexible audio routing.

UART(3) Universal ARM Connectivity Each UART provides serial communication capability with external
asynchronous (UART1,2) peripherals devices through an RS-232 cable using the standard RS-232
receiver/trans SDMA non-return-to-zero (NRZ) encoding format. Each module transmits
mitters (UART3) and receives characters containing either 7 or 8 bits
(program-selectable). Each UART can also provide low-speed IrDA
compatibility through the use of external circuitry that converts
infrared signals to electrical signals (for reception) or transforms
electrical signals to signals that drive an infrared LED (for
transmission).

USBOH High-speed SDMA Connectivity The USB module provides high performance USB on-the-go (OTG)
USB on-the-go peripherals functionality (up to 480 Mbps), compliant with the USB 2.0
specification, the OTG supplement, and the ULPI 1.0 low pin count
specification. The module has DMA capabilities handling data
transfer between internal buffers and system memory.

WDOG Watchdog ARM Timer Each module protects against system failures by providing a method
modules peripherals of escaping from unexpected events or programming errors. Once
activated, the timer must be serviced by software on a periodic
basis. If servicing does not take place, the watchdog times out and
then either asserts a system reset signal or an interrupt request
signal, depending on the software configuration.

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1
ARM = ARM1136 platform, SDMA = SDMA platform

3 Signal Descriptions: Special Function Related Pins

Some special functional requirements are supported in the device. The details about these special functions
and the corresponding pin names are listed in Table 5.
Table 5. Special Function Related Pins

Function Name Pin Name Mux Mode Detailed Description

External ARM Clock EXT_ARMCLK ALT0 External clock input for ARM clock.

External Peripheral Clock I2C1_CLK ALT6 External peripheral clock source.

External 32-kHz Clock CAPTURE ALT4 External clock input of 32 kHz, used when the internal
24M Oscillator is powered off, which could be
CSPI1_SS1 ALT2 configured either from CAPTURE or CSPI1_SS1.

Clock Out CLKO ALT0 Clock-out pin from CCM, clock source is controllable
and can also be used for debug.

Power Ready GPIO1_0 ALT1 PMIC power-ready signal, which can be configured
either from GPIO1_0 or TX1.
TX1 ALT1

Tamper Detect GPIO1_1 ALT6 Tamper-detect logic is used to issue a security

violation. This logic is activated if the tamper-detect
input is asserted. Tamper-detect logic is enabled by the
bit of IOMUXC_GPRA[2]. After enabling the logic, it is
impossible to disable it until the next reset.

4 Electrical Characteristics
The following sections provide the device-level and module-level electrical characteristics for the i.MX35
processor.

4.1 i.MX35 Chip-Level Conditions

This section provides the device-level electrical characteristics for the IC. See Table 6 for a quick reference
to the individual tables and sections.
Table 6. i.MX35 Chip-Level Conditions

Characteristics Table/Location

Absolute Maximum Ratings Table 7 on page 13

i.MX35 Operating Ranges Table 8 on page 13

Interface Frequency Table 9 on page 14

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 CAUTION
Stresses beyond those listed in Table 7 may cause permanent damage to the
device. These are stress ratings only. Functional operation of the device at
these or any other conditions beyond those indicated in Table 8 is not
implied. Exposure to absolute-maximum-rated conditions for extended
periods may affect device reliability.
Table 7. Absolute Maximum Ratings

Parameter Symbol Min. Max. Units

Supply voltage (core) VDDmax1 –0.5 1.47 V

Supply voltage (I/O) NVCCmax –0.5 3.6 V
Input voltage range VImax –0.5 3.6 V
oC
Storage temperature Tstorage –40 125
ESD damage immunity: Vesd V
2
Human Body Model (HBM) — 2000
Charge Device Model (CDM) — 5003
1
VDD is also known as QVCC.
2
HBM ESD classification level according to the AEC-Q100-002 standard
3
Corner pins max. 750 V

4.1.1 i.MX35 Operating Ranges

Table 8 provides the recommended operating ranges. The term NVCC in this section refers to the
associated supply rail of an input or output.
Table 8. i.MX35 Operating Ranges

Parameter Symbol Min. Typical Max. Units

Core Operating Voltage VDD 1.22 — 1.47 V

0 < fARM < 400 MHz
Core Operating Voltage 1.33 — 1.47 V
0 < fARM < 532 MHz
State Retention Voltage 1 — — V
EMI1 NVCC_EMI1,2,3 1.7 — 3.6 V
WTDG, Timer, CCM, CSPI1 NVCC_CRM 1.75 — 3.6 V
NANDF NVCC_NANDF 1.75 — 3.6 V
ATA, USB generic NVCC_ATA 1.75 — 3.6 V
eSDHC1 NVCC_SDIO 1.75 — 3.6 V
CSI, SDIO2 NVCC_CSI 1.75 — 3.6 V
JTAG NVCC_JTAG 1.75 — 3.6 V
LCDC, TTM, I2C1 NVCC_LCDC 1.75 — 3.6 V

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 Table 8. i.MX35 Operating Ranges (continued)

Parameter Symbol Min. Typical Max. Units

I2Sx2,ESAI, I2C2, UART2, UART1, FEC NVCC_MISC 1.75 — 3.6 V

2
MLB NVCC_MLB 1.75 — 3.6 V
USB OTG PHY PHY1_VDDA 3.17 3.3 3.43 V
USB OTG PHY USBPHY1_VDDA_BIAS 3.17 3.3 3.43 V
USB OTG PHY USBPHY1_UPLLVDD 3.17 3.3 3.43 V
USB HOST PHY PHY2_VDD 3.0 3.3 3.6 V
OSC24M OSC24M_VDD 3.0 3.3 3.6 V
OSC_AUDIO OSC_AUDIO_VDD 3.0 3.3 3.6 V
MPLL MVDD 1.4 — 1.65 V
PPLL PVDD 1.4 — 1.65 V
Fusebox program supply voltage FUSE_VDD3 3.0 3.6 3.6 V
Operating Ambient Temperature Range TA –20 — 70 oC

oC
Operating Ambient Temperature Range TA –40 — 85
1
EMI I/O interface power supply should be set up according to external memory. For example, if using SDRAM then
NVCC_EMI1,2,3 should all be set at 3.3 V (typ.). If using MDDR or DDR2, NVC_EMI1,2,3 must be set at 1.8 V (typ.).
2 MLB Interface I/O pins can be programmed to function as GPIO for the consumer and industrial parts by setting NVCC_MLB

to 1.8 or 3.3 V. NVCC_MLB can be left floating.

3 The Fusebox read supply is connected to supply of the full speed USB PHY. FUSE_VDD is only used for programming. It is

recommended that FUSE_VDD be connected to ground when not being used for programming. FUSE_VDD should be
supplied by following the power up sequence given in Section 4.3.1, “Powering Up.”

4.1.2 Interface Frequency Limits

Table 9 provides information on interface frequency limits.
Table 9. Interface Frequency

ID Parameter Symbol Min. Typ. Max. Units

1 JTAG TCK Frequency fJTAG DC 5 10 MHz

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4.2 Power Modes
Table 10 provides descriptions of the power modes of the i.MX35 processor.
Table 10. i.MX35 Power Modes

QVCC (ARM/L2 OSC24M_VDD

MVDD/PVDD
Power Peripheral) OSC_AUDO_VDD
Description
Mode
Typ. Max. Typ. Max. Typ. Max.

Wait VDD1,2,3,4 = 1.1 V (min.)

ARM is in wait for interrupt mode.
MAX is active.
L2 cache is kept powered.
MCU PLL is on (400 MHz)
PER PLL is off (can be configured)
16 mA — 7.2 mA — 1.2 mA —
(default: 300 MHz)
Module clocks are gated off (can be
configured by CGR register).
OSC 24M is ON.
OSC audio is off (can be configured).
RNGC internal osc is off.
Doze VDD1,2,3,4 = 1.1 V (min.)
ARM is in wait for interrupt mode.
MAX is halted.
L2 cache is kept powered.
L2 cache control logic off.
AWB enabled.
MCU PLL is on(400 MHz)
12.4 mA — 7.2 mA — 1.2 mA —
PER PLL is off (can be configured).
(300 Mhz).
Module clocks are gated off (can be
configured by CGR register).
OSC 24M is ON.
OSC audio is off (can be configured)
RNGC internal osc is off
Stop VDD1,2,3,4 = 1.1 V (min.)
ARM is in wait for interrupt mode.
MAX is halted
L2 cache is kept powered.
L2 cache control logic off.
AWB enabled.
1.1 mA — 400 µA — 1.2 mA —
MCU PLL is off.
PER PLL is off.
All clocks are gated off.
OSC 24 MHz is on
OSC audio is off
RNGC internal osc is off

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 Table 10. i.MX35 Power Modes (continued)

QVCC (ARM/L2 OSC24M_VDD

MVDD/PVDD
Power Peripheral) OSC_AUDO_VDD
Description
Mode
Typ. Max. Typ. Max. Typ. Max.

Static VDD1,2,3,4 = 1.1 V (min.)

ARM is in wait for interrupt mode.
MAX is halted
L2 cache is kept powered.
L2 cache control logic off.
AWB enabled.
820 µA — 50 µA — 24 µA —
MCU PLL is off.
PER PLL is off.
All clocks are gated off.
OSC 24MHz is on
OSC audio is off
RNGC internal osc is off
Note: Typical column: TA = 25 °C

4.3 Supply Power-Up/Power-Down Requirements and Restrictions

This section provides power-up and power-down sequence guidelines for the i.MX35 processor.
CAUTION
Any i.MX35 board design must comply with the power-up and power-down
sequence guidelines as described in this section to guarantee reliable
operation of the device. Any deviation from these sequences can result in
irreversible damage to the i.MX35 processor (worst-case scenario).
NOTE
Deviation from these sequences may also result in one or more of the
following:
• Excessive current during power-up phase
• Prevent the device from booting
• Programming of unprogrammed fuses

4.3.1 Powering Up
The power-up sequence should be completed as follows:
1. Assert Power on Reset (POR).
2. Turn on digital logic domain and IO power supply: VDDn, NVCCx
3. Wait until VDDn and NVCCx power supplies are stable + 32 μs.

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 4. Turn on all other power supplies: PHY1_VDDA, USBPHY1_VDDA_BIAS, PHY2_VDD,
USBPHY1_UPLLVDD, OSC24M_VDD, OSC_AUDIO_VDD, MVDD, PVDD, FUSEVDD.
(Always FUSE_VDD should be connected to ground, except when eFuses are to be
programmed.)
5. Wait until PHY1_VDDA, USBPHY1_VDDA_BIAS, PHY2_VDD, USBPHY1_UPLLVDD,
OSC24M_VDD, OSC_AUDIO_VDD, MVDD, PVDD, (FUSEVDD, optional). Power supplies
are stable + 100 μs.
6. Deassert the POR signal.
Figure 2 shows the power-up sequence and timing.

Figure 2. i.MX35 Power-Up Sequence and Timing

4.3.2 Powering Down

The power-up sequence in reverse order is recommended for powering down. However, all power supplies
can be shut down at the same time.

4.4 Reset Timing

There are two ways of resetting the i.MX35 using external pins:
• Power On Reset (using the POR_B pin)

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 • System Reset (using the RESET_IN_B pin)

4.4.1 Power On Reset

POR_B is normally connected to a power management integrated circuit (PMIC). The PMIC asserts
POR_B while the power supplies are turned on and negates POR_B after the power up sequence is
finished. See Figure 2.
Assuming the i.MX35 chip is already fully powered; it is still possible to reset all of the modules to their
default reset by asserting POR_B for at least 4 CKIL cycles and later de-asserting POR_B. This method
of resetting the i.MX35 can also be supported by tying the POR_B and RESET_IN_B pins together.

POR_B
At least 4 CKIL cycles

CKIL

Figure 3. Timing Between POR_B and CKIL for Complete Reset of i.MX35

4.4.2 System Reset

System reset can be achieved by asserting RESET_IN_B for at least 4 CKIL cycles and later negating
RESET_IN_B. The following modules are not reset upon system reset: RTC, PLLs, CCM, and IIM.
POR_B pin must be deasserted all the time.

RESET_IN_B
At least 4 CKIL cycles

CKIL

Figure 4. Timing Between RESET_IN_B and CKIL for i.MX35 System Reboot

4.5 Power Characteristics

The table shows values representing maximum current numbers for the i.MX35 under worst case voltage
and temperature conditions. These values are derived from the i.MX35 with core clock speeds up to

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18 Freescale Semiconductor
532 MHz. Common supplies have been bundled according to the i.MX35 power-up sequence
requirements. Peak numbers are provided for system designers so that the i.MX35 power supply
requirements will be satisfied during startup and transient conditions. Freescale recommends that system
current measurements be taken with customer-specific use-cases to reflect normal operating conditions in
the end system.
Table 11. Power Consumption

Power Supply Voltage (V) Max Current (mA)

QVCC 1.47 400

MVDD, PVDD 1.65 20

NVCC_EMI1, NVCC_EMI2, NVCC_EMI3, NVCC_LCDC, NVCC_NFC 1.9 90

FUSE_VDD1 3.6 62

NVCC_MISC, NVCC_CSI, NVCC_SDIO, NVCC_CRM, NVCC_ATA, NVCC_MLB, 3.6 60

NVCC_JTAG

OSC24M_VDD, OSC_AUDIO_VDD, PHY1_VDDA, PHY2_VDD, 3.6 25

USBPHY1_UPLLVDD, USBPHY1_VDDA_BIAS
1 This rail is connected to ground; it only needs a voltage if eFuses are to be programmed. FUSE_VDD should be supplied by
following the power up sequence given in Section 4.3.1, “Powering Up.”

The method for obtaining max current is as follows:

1. Measure worst case power consumption on individual rails using directed test on i.MX35.
2. Correlate worst case power consumption power measurements with worst case power
consumption simulations.
3. Combine common voltage rails based on power supply sequencing requirements
4. Guard band worst case numbers for temperature and process variation. Guard band is based on
process data and correlated with actual data measured on i.MX35.
5. The sum of individual rails is greater than real world power consumption, as a real system does
not typically maximize power consumption on all peripherals simultaneously.

4.6 Thermal Characteristics

The thermal resistance characteristics for the device are given in Table 12. These values were measured
under the following conditions:
• Two-layer substrate
• Substrate solder mask thickness: 0.025 mm
• Substrate metal thicknesses: 0.016 mm
• Substrate core thickness: 0.200 mm
• Core via I.D: 0.168 mm, Core via plating 0.016 mm.
• Full array map design, but nearly all balls under die are power or ground.
• Die Attach: 0.033 mm non-conductive die attach, k = 0.3 W/m K
• Mold compound: k = 0.9 W/m K

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 Table 12. Thermal Resistance Data

Rating Condition Symbol Value Unit

Junction to ambient1 natural convection Single layer board (1s) ReJA 53 ºC/W

Junction to ambient1 natural convection Four layer board (2s2p) ReJA 30 ºC/W

Junction to ambient1 (at 200 ft/min) Single layer board (1s) ReJMA 44 ºC/W

Junction to ambient1 (at 200 ft/min) Four layer board (2s2p) ReJMA 27 ºC/W

Junction to boards2 — ReJB 19 ºC/W

Junction to case (top)3 — ReJCtop 10 ºC/W

Junction to package top4 Natural convection ΨJT 2 ºC/W

1
Junction-to-ambient thermal resistance determined per JEDC JESD51-3 and JESD51-6. Thermal test board meets JEDEC
specification for this package.
2 Junction-to-board thermal resistance determined per JEDC JESD51-8. Thermal test board meets JEDEC specification for this

package.
3 Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used

for the case temperature. Reported value includes the thermal resistance of the interface layer.
4
Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, this thermal characterization parameter is written
as Psi-JT.

4.7 I/O Pin DC Electrical Characteristics

I/O pins are of two types: GPIO and DDR. DDR pins can be configured in three different drive strength
modes: mobile DDR, SDRAM, and DDR2. The SDRAM and mobile DDR modes can be further
customized at three drive strength levels: normal, high, and max.
Table 13 shows currents for the different DDR pin drive strength modes.
Table 13. DDR Pin Drive Strength Mode Current Levels

Drive Mode Normal High Max.

Mobile DDR (1.8 V) 3.6 mA 7.2 mA 10.8 mA

SDRAM (1.8 V) — — 6.5 mA

SDRAM (3.3 V) 4 mA 8 mA 12 mA

DDR2 (1.8 V) — — 13.4 mA

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Table 14 shows the DC electrical characteristics for GPIO, DDR2, mobile DDR, and SDRAM pins. The
term NVCC refers to the power supply voltage that feeds the I/O of the module in question. For example,
NVCC for the SD/MMC interface refers to NVCC_SDIO.
Table 14. I/O Pin DC Electrical Characteristics

Pin DC Electrical Characteristics Symbol Test Condition Min. Typ. Max. Unit

GPIO High-level output voltage Voh Ioh = –1 mA NVCC – 0.15 — — V

Ioh = specified drive 0.8 × NVCC

Low-level output voltage Vol Iol = 1 mA — — 0.15 V

Iol = specified drive 0.2 × NVCC

High-level output current for Ioh Standard drive –2.0 — — mA

slow mode High drive –4.0
(Voh = 0.8 × NVCC) Max. drive –8.0

High-level output current Ioh Standard drive –4.0 — — mA

for fast mode High drive –6.0
(Voh = 0.8 × NVCC) Max. drive –8.0

Low-level output current Iol Standard drive 2.0 — — mA

for slow mode High drive 4.0
(Voh = 0.2 × NVCC) Max. drive 8.0

Low-level output current Iol Standard drive 4.0 — — mA

for fast mode High drive 6.0
(Voh = 0.2 × NVCC) Max. drive 8.0

High-level DC Input VIH — 0.7 × NVCC — NVCC V

Voltage with 1.8 V,
3.3 V NVCC (for digital
cells in input mode)

Low-level DC Input VIL — –0.3 V — 0.3 × NVCC V

Voltage with 1.8 V,
3.3 V NVCC (for digital
cells in input mode

Input Hysteresis VHYS OVDD = 3.3 V — 410 — mV

OVDD = 1.8 V 330

Schmitt trigger VT+ VT+ — 0.5 × NVCC — V

Schmitt trigger VT– VT– — — — 0.5 × NVCC V

Pull-up resistor Rpu Vi = 0 — 22 — kΩ

(22 kΩ PU)

Pull-up resistor Rpu Vi = 0 — 47 — kΩ

(47 kΩ PU)

Pull-up resistor Rpu Vi = 0 — 100 — kΩ

(100 kΩ PU)

Pull-down resistor (100 kΩ PD) Rpd Vi = NVCC — 100 — kΩ

External resistance to pull Rkpu Ipu > 620 μA — — 4.8 kΩ

keeper up when enabled @ min Vddio = 3.0 V

External resistance to pull Rkpd Ipu > 510 μA — — 5.9 kΩ

keeper down when enabled @min Vddio = 3.0 V

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 Table 14. I/O Pin DC Electrical Characteristics (continued)

Pin DC Electrical Characteristics Symbol Test Condition Min. Typ. Max. Unit

DDR2 High-level output voltage Voh — NVCC – 0.28 — — V

Low-level output voltage Vol — — 0.28 V

Output min. source current Ioh — –13.4 — — mA

Output min. sink current Iol — 13.4 — — mA

DC input logic high VIH(dc) — NVCC ÷ 2 + — NVCC + 0.3 V

0.125

DC input logic low VIL(dc) — –0.3 V — NVCC ÷ 2 – V

0.125

DC input signal voltage Vin(dc) — –0.3 — NVCC + 0.3 V

(for differential signal)

DC differential input voltage Vid(dc) — 0.25 — NVCC + 0.6 V

Termination voltage Vtt — NVCC ÷ 2 – NV NVCC ÷ 2 + V

0.04 CC 0.04
÷2

Input current (no IIN — — — ±1 μA

pull-up/down)

Tri-state I/O supply current Icc – N — — — ±1 μA

VCC

Mobile High-level output voltage — IOH = –1mA NVCC – 0.08 — — V

DDR IOH = specified drive 0.8 × NVCC

Low-level output voltage — IOL = 1mA — — 0.08 V

IOL = specified drive 0.2 × NVCC

High-level output current — Standard drive –3.6 — — mA

(Voh = 0.8 × NVCCV) High drive –7.2
Max. drive –10.8

Low-level output current — Standard Drive 3.6 — — mA

(Vol = 0.2 × NVCCV) High Drive 7.2
Max. Drive 10.8

High-Level DC CMOS VIH — 0.7 × NVCC — NVCC + 0.3 V

input voltage

Low-Level DC CMOS VIL — –0.3 — 0.2 × NVCC V

input voltage

Differential receiver VTH+ VTH+ — — — 100 mV

Differential receiver VTH– VTH– — –100 — mV

Input current (no IIN VI = 0 — — ±1 μA

pull-up/down) VI = NVCC

Tri-state I/O supply current Icc – N VI = NVCC or 0 — — ±1 μA

VCC

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 Table 14. I/O Pin DC Electrical Characteristics (continued)

Pin DC Electrical Characteristics Symbol Test Condition Min. Typ. Max. Unit

SDR High-level output voltage Voh loh = 5.7 mA OVDD – 0.28 — — V

(1.8 V)
Low-level output voltage Vol loh = 5.7 mA — — 0.4 V

High-level output current Ioh Max. drive 5.7 — — mA

Low-level output current Iol Max. drive 7.3 — — mA

High-level DC Input Voltage VIH — 1.4 — 1.98 V

Low-level DC Input Voltage VIL — –0.3 — 0.8 V

Input current (no IIN VI = 0 — — 150 μA

pull-up/down) VI=NVCC 80

Tri-state I/O supply current Icc VI = OVDD or 0 — — 1180 μA

(NVCC)

Tri-state core supply current Icc VI = VDD or 0 — — 1220 μA

(NVCC)

SDR High-level output voltage Voh Ioh=specified drive 2.4 — — V

(3.3 V) (Ioh = –4, –8, –12,
–16 mA)

Low-level output voltage Vol Ioh=specified drive (Ioh = 4, — — 0.4 V

8, 12, 16 mA)

High-level output current Ioh Standard drive –4.0 — — mA

High drive –8.0
Max. drive –12.0

Low-level output current Iol Standard drive 4.0 — — mA

High drive 8.0
Max. drive 12.0

High-level DC Input Voltage VIH — 2.0 — 3.6 V

Low-level DC Input Voltage VIL — –0.3V — 0.8 V

Input current (no IIN VI = 0 — — ±1 μA

pull-up/down)
VI = NVCC

Tri-state I/O supply current Icc VI = NVCC or 0 — — ±1 μA

(NVCC)

4.8 I/O Pin AC Electrical Characteristics

Figure 5 shows the load circuit for output pins.
From Output Test Point
Under Test
CL

CL includes package, probe and jig capacitance

Figure 5. Load Circuit for Output Pin

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Figure 6 shows the output pin transition time waveform.
NVCC
80% 80%

20% 20%
Output (at pin) 0V
PA1 PA1

Figure 6. Output Pin Transition Time Waveform

4.8.1 AC Electrical Test Parameter Definitions

AC electrical characteristics in Table 16 through Table 21 are not applicable for the output open drain
pull-down driver.
The dI/dt parameters are measured with the following methodology:
• The zero voltage source is connected between pin and load capacitance.
• The current (through this source) derivative is calculated during output transitions.
Table 15. AC Requirements of I/O Pins

Parameter Symbol Min. Max. Units

AC input logic high VIH(ac) NVCC ÷ 2 + 0.25 NVCC + 0.3 V

AC input logic low VIL(ac) –0.3 NVCC ÷ 2 – 0.25 V

Table 16. AC Electrical Characteristics of GPIO Pins in Slow Slew Rate Mode
[NVCC = 3.0 V–3.6 V]

Test Min. Max.

Parameter Symbol Typ. Rise/Fall Units
Condition Rise/Fall Rise/Fall

Duty cycle Fduty — 40 — 60 %

Output pin slew rate (max. drive) tps 25 pF 0.79/1.12 1.30/1.77 2.02/2.58 V/ns
50 pF 0.49/0.73 0.84/1.23 1.19/1.58

Output pin slew rate (high drive) tps 25 pF 0.48/0.72 0.76/1.10 1.17/1.56 V/ns
50 pF 0.27/0.42 0.41/0.62 0.63/0.86

Output pin slew rate (standard tps 25 pF 0.25/0.40 0.40/0.59 0.60/0.83 V/ns
drive) 50 pF 0.14/0.21 0.21/0.32 0.32/0.44

Output pin di/dt (max. drive) tdit 25 pF 15 36 76 mA/ns

50 pF 16 38 80

Output pin di/dt (high drive) tdit 25 pF 8 20 45 mA/ns

50 pF 9 21 47

Output pin di/dt (standard tdit 25 pF 4 10 22 mA/ns

drive) 50 pF 4 10 23

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 Table 17. AC Electrical Characteristics of GPIO Pins in Slow Slew Rate Mode
[NVCC = 1.65 V–1.95 V]

Min. Max.
Parameter Symbol Test Condition Typ. Units
Rise/Fall Rise/Fall

Duty cycle Fduty — 40 — 60 %

Output pin slew rate (max. drive) tps 25 pF 0.30/0.42 0.54/0.73 0.91/1.20 V/ns
50 pF 0.20/0.29 0.35/0.50 0.60/0.80

Output pin slew rate (high drive) tps 25 pF 0.19/0.28 0.34/0.49 0.58/0/79 V/ns
50 pF 0.12/0.18 0.34/0.49 0.36/0.49

Output pin slew rate (standard drive) tps 25 pF 0.12/0.18 0.20/0.30 0.34/0.47 V/ns
50 pF 0.07/0.11 0.11/0.17 0.20/0.27

Output pin di/dt (max. drive) tdit 25 pF 7 21 56 mA/ns

50 pF 7 22 58

Output pin di/dt (high drive) tdit 25 pF 5 14 38 mA/ns

50 pF 5 15 40

Output pin di/dt (standard tdit 25 pF 2 7 18 mA/ns

drive) 50 pF 2 7 19

Table 18. AC Electrical Characteristics of GPIO Pins in Fast Slew Rate Mode for
[NVCC = 3.0 V–3.6 V]

Min. Max.
Parameter Symbol Test Condition Typ. Units
rise/fall Rise/Fall

Duty cycle Fduty — 40 — 60 %

Output pin slew rate (max. drive) tps 25 pF 0.96/1.40 1.54/2.10 2.30/3.00 V/ns
50 pF 0.54/0.83 0.85/1.24 1.26/1.70

Output pin slew rate (high drive) tps 25 pF 0.76/1.10 1.19/1.71 1.78/2.39 V/ns
50 pF 0.41/0.64 0.63/0.95 0.95/1.30

Output pin slew rate (standard drive) tps 25 pF 0.52/0.78 0.80/1.19 1.20/1.60 V/ns
50 pF 0.28/0.44 0.43/0.64 0.63/0.87

Output pin di/dt (max. drive) tdit 25 pF 46 108 250 mA/ns

50 pF 49 113 262

Output pin di/dt (high drive) tdit 25 pF 35 82 197 mA/ns

50 pF 37 86 207

Output pin di/dt (standard tdit 25 pF 22 52 116 mA/ns

drive) 50 pF 23 55 121

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 Table 19. AC Electrical Characteristics, GPIO Pins in Fast Slew Rate Mode
[NVCC = 1.65 V–1.95 V]

Min. Max.
Parameter Symbol Test Condition Typ. Units
Rise/Fall Rise/Fall

Duty cycle Fduty — 40 — 60 %

Output pin slew rate (max. drive) tps 25 pF 0.40/0.57 0.72/0.97 1.2/1.5 V/ns
50 pF 0.25/0.36 0.43/0.61 0.72/0.95

Output pin slew rate (high drive) tps 25 pF 0.38/0.48 0.59/0.81 0.98/1.27 V/ns
50 pF 0.20/0.30 0.34/0.50 0.56/0.72

Output pin slew rate (standard drive) tps 25 pF 0.23/0.32 0.40/0.55 0.66/0.87 V/ns
50 pF 0.13/0.20 0.23/0.34 0.38/0.52

Output pin di/dt (max. drive) tdit 25 pF 7 43 112 mA/ns

50 pF 7 46 118

Output pin di/dt (high drive) tdit 25 pF 11 31 81 mA/ns

50 pF 12 33 85

Output pin di/dt (standard tdit 25 pF 9 27 71 mA/ns

drive) 50 pF 10 28 74

Table 20. AC Electrical Characteristics of GPIO Pins in Slow Slew Rate Mode
[NVCC = 2.25 V–2.75 V]

Min. Max.
Parameter Symbol Test Condition Typ. Units
Rise/Fall Rise/Fall

Duty cycle Fduty — 40 — 60 %

Output pin slew rate (max. drive) tps 25 pF 0.63/0.85 1.10/1.40 1.86/2.20 V/ns
40 pF 0.52/0.67 0.90/1.10 1.53/1.73
50 pF 0.41/0.59 0.73/0.99 1.20/1.50

Output pin slew rate (high drive) tps 25 pF 0.40/0.58 0.71/0.98 1.16/1.40 V/ns
40 pF 0.33/0.43 0.56/0.70 0.93/1.07
50 pF 0.25/0.37 0.43/0.60 0.68/0.90

Output pin slew rate (standard drive) tps 25 pF 0.24/0.36 0.41/0.59 0.66/0.87 V/ns
40 pF 0.19/0.25 0.32/0.35 0.51/0.59
50 pF 0.13/0.21 0.23/0.33 0.36/0.48

Output pin di/dt (max. drive) tdit 25 pF 22 62 148 mA/ns

50 pF 23 65 151

Output pin di/dt (high drive) tdit 25 pF 15 42 102 mA/ns

50 pF 16 44 107

Output pin di/dt (standard tdit 25 pF 7 21 52 mA/ns

drive) 50 pF 8 22 54

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26 Freescale Semiconductor
 Table 21. AC Electrical Characteristics of GPIO Pins in Fast Slew Rate Mode
[NVCC = 2.25 V–2.75 V]

Test Min. Max.

Parameter Symbol Typ. Units Notes
Condition Rise/Fall Rise/Fall

Duty cycle Fduty — 40 — 60 % —

Output pin slew rate (max. drive) tps 25 pF 0.84/1.10 1.45/1.80 2.40/2.80 V/ns 2
40 pF 0.68/0.83 1.14/1.34 1.88/2.06
50 pF 0.58/0.72 0.86/1.10 1.40/1.70

Output pin slew rate (high drive) tps 25 pF 0.69/0.96 1.18/1.50 1.90/2.30 V/ns
40 pF 0.55/0.69 0.92/1.10 1.49/1.67
50 pF 0.40/0.59 0.67/0.95 1.10/1.30

Output pin slew rate (standard drive) tps 25 pF 0.24/0.36 0.80/1.00 1.30/1.60 V/ns
40 pF 0.37/0.47 0.62/0.76 1.00/1.14
50 pF 0.13/0.21 0.45/0.65 0.70/0.95

Output pin di/dt (max. drive) tdit 25 pF 46 124 310 mA/ns 3

50 pF 49 131 324

Output pin di/dt (high drive) tdit 25 pF 33 89 290 mA/ns

50 pF 35 94 304

Output pin di/dt (standard tdit 25 pF 28 75 188 mA/ns

drive) 50 pF 29 79 198

4.8.2 AC Electrical Characteristics for DDR Pins (DDR2, Mobile DDR, and
SDRAM Modes)
Table 22. AC Electrical Characteristics of DDR Type IO Pins in DDR2 Mode

Min. Max.
Parameter Symbol Test Condition Typ. Units
Rise/Fall Rise/Fall

Duty cycle Fduty — 45 50 55 %

Clock frequency f — — 133 — MHz

Output pin slew rate tps 25 pF 0.86/0.98 1.35/1.5 2.15/2.19 V/ns

50 pF 0.46/054 0.72/0.81 1.12/1.16

Output pin di/dt tdit 25 pF 65 157 373 mA/ns

50 pF 70 167 396

Table 23. AC Requirements of DDR2 Pins

Parameter1 Symbol Min. Max. Units

AC input logic high VIH(ac) NVCC ÷ 2 + 0.25 NVCC + 0.3 V

AC input logic low VIL(ac) –0.3 NVCC ÷ 2 – 0.25 V
AC differential cross point voltage for output2 Vox(ac) NVCC ÷ 2 – 0.125 NVCC ÷ 2 + 0.125 V
1 The Jedec SSTL_18 specification (JESD8-15a) for an SSTL interface for class II operation supersedes any specification in this
document.

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2
The typical value of Vox(ac) is expected to be about 0.5 × NVCC and Vox(ac) is expected to track variation in NVCC. Vox(ac)
indicates the voltage at which the differential output signal must cross. Cload = 25 pF.

Table 24. AC Electrical Characteristics of DDR Type IO Pins in mDDR Mode

Min. Max.
Parameter Symbol Test Condition Typ. Units
Rise/Fall Rise/Fall

Duty cycle Fduty — 45 50 55 %

Clock frequency f — — 133 — MHz

Output pin slew rate (max. drive) tps 25 pF 0.80/0.92 1.35/1.50 2.23/2.27 V/ns
50 pF 0.43/0.50 0.72/0.81 1.66/1.68

Output pin slew rate (high drive) tps 25 pF 0.37/0.43 0.62/0.70 1.03/1.05 V/ns
50 pF 0.19/0.23 0.33/0.37 0.75/0.77

Output pin slew rate (standard drive) tps 25 pF 0.18/0.22 0.31/0.35 0.51/0.53 V/ns
50 pF 0.10/0.12 0.16/0.18 0.38/0.39

Output pin di/dt (max. drive) tdit 25 pF 64 171 407 mA/ns

50 pF 69 183 432

Output pin di/dt (high drive) tdit 25 pF 37 100 232 mA/ns

50 pF 39 106 246

Output pin di/dt (standard drive) tdit 25 pF 18 50 116 mA/ns

50 pF 20 52 123

Table 25. AC Electrical Characteristics of DDR Type IO Pins in SDRAM Mode

Min. Min. Clock Max.

Parameter Symbol Test Condition Units
Rise/Fall Frequency Rise/Fall

Clock frequency f — — 125 — MHz

Output pin slew rate (max. drive) tps 25 pF 1.11/1.20 1.74/1.75 2.42/2.46 V/ns
50 pF 0.97/0.65 0.92/0.94 1.39/1.30

Output pin slew rate (high drive) tps 25 pF 0.76/0.80 1.16/1.19 1.76/1.66 V/ns
50 pF 0.40/0.43 0.61/0.63 0.93/0.87

Output pin slew rate (standard drive) tps 25 pF 0.38/0.41 0.59/0.60 0.89/0.82 V/ns
50 pF 0.20/0.22 0.31/0.32 0.47/0.43

Output pin di/dt (max. drive) tdit 25 pF 89 198 398 mA/ns

50 pF 94 209 421

Output pin di/dt (high drive) tdit 25 pF 59 132 265 mA/ns

50 pF 62 139 279

Output pin di/dt (standard drive) tdit 25 pF 29 65 132 mA/ns

50 pF 31 69 139

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28 Freescale Semiconductor
 Table 26. AC Electrical Characteristics of DDR Type IO Pins in SDRAM Mode Max Drive (1.8 V)

Min. Max.
Parameter Symbol Test Condition Typ. Units
Rise/Fall Rise/Fall

Clock frequency f — 125 — — MHz

1
Output pin slew rate (max. drive) tps 25 pF 2.83/2.68 1.84/1.85 1.21/1.40 V/ns
50 pF 1.59/1.49 1.03/1.05 0.70/0.75

Output pin di/dt (max. drive)2 didt 25 pF 89 202 435 mA/ns

50 pF 95 213 456

Input pin transition times3 trfi 1.0 pF 0.07/0.08 0.11/0.12 0.16/0.20 ns

Input pin propagation delay, 50%–50% tpi 1.0 pF 0.35/1.17 0.63/1.53 1.16/2.04 ns

Input pin propagation delay, 40%–60% tpi 1.0 pF 1.18/1.99 1.45/2.35 1.97/2.85 ns
1
Min. condition for tps: wcs model, 1.1 V, IO 1.65 V, and 105 °C. tps is measured between VIL to VIH for rising edge and between
VIH to VIL for falling edge.
2 Max. condition for tdit: bcs model, 1.3 V, IO 1.95 V, and –40 °C.
3 Max. condition for tpi and trfi: wcs model, 1.1 V, IO 1.65 V and 105 °C. Min. condition for tpi and trfi: bcs model, 1.3 V, IO 1.95 V

and –40 °C. Input transition time from pad is 5 ns (20%–80%).

4.9 Module-Level AC Electrical Specifications

This section contains the AC electrical information (including timing specifications) for the modules of
the i.MX35. The modules are listed in alphabetical order.

4.9.1 AUDMUX Electrical Specifications

The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between
internal serial interfaces (SSI) and external serial interfaces (audio and voice codecs). The AC timing of
AUDMUX external pins is hence governed by the SSI module. See the electrical specification for SSI.

4.9.2 CSPI AC Electrical Specifications

The i.MX35 provides two CSPI modules. CSPI ports are multiplexed in the i.MX35 with other pins. See
the “External Signals and Multiplexing” chapter of the reference manual for more details.

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Freescale Semiconductor 29
Figure 7 and Figure 8 depict the master mode and slave mode timings of the CSPI, and Table 27 lists the
timing parameters.

SPI_RDY
CS11

SSn[3:0] CS2 CS6

CS1 CS3 CS5
CS3
CS4
SCLK
CS2
CS7 CS8

MOSI

CS9 CS10
MISO

Figure 7. CSPI Master Mode Timing Diagram

SSn[3:0]
CS1 CS3 CS2 CS6 CS5
CS4
SCLK
CS3 CS2
CS9 CS10
MISO

CS7 CS8
MOSI

Figure 8. CSPI Slave Mode Timing Diagram

Table 27. CSPI Interface Timing Parameters

ID Parameter Symbol Min. Max. Units

CS1 SCLK cycle time tclk 60 — ns

CS2 SCLK high or low time tSW 30 — ns
CS3 SCLK rise or fall tRISE/FALL — 7.6 ns
CS4 SSn[3:0] pulse width tCSLH 30 — ns
CS5 SSn[3:0] lead time (CS setup time) tSCS 30 — ns
CS6 SSn[3:0] lag time (CS hold time) tHCS 30 — ns
CS7 MOSI setup time tSmosi 5 — ns
CS8 MOSI hold time tHmosi 5 — ns
CS9 MISO setup time tSmiso 5 — ns

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 Table 27. CSPI Interface Timing Parameters (continued)

ID Parameter Symbol Min. Max. Units

CS10 MISO hold time tHmiso 5 — ns

CS11 SPI_RDY setup time tSDRY 5 — ns

4.9.3 DPLL Electrical Specifications

There are three PLLs inside the i.MX35, all based on the same PLL design. The reference clock for these
PLLs is normally generated from an external 24-MHz crystal connected to an internal oscillator via
EXTAL24M and XTAL24 pins. It is also possible to connect an external 24-MHz clock directly to
EXTAL24M, bypassing the internal oscillator.
DPLL specifications are listed in Table 28.
Table 28. DPLL Specifications

Parameter Min. Typ. Max. Unit Comments

Reference clock frequency 10 24 100 MHz

Max. allowed reference clock phase noise — — 0.03 2 Tdck1 Fmodulation < 50 kHz
0.01 50 kHz < Fmodulation 300 Hz
0.15 Fmodulation > 300 KHz

Frequency lock time (FOL mode or non-integer MF) — — 80 μs —

Phase lock time — — 100 μs —

Max. allowed PL voltage ripple — — 150 mV Fmodulation < 50 kHz

100 50 kHz < Fmodulation 300 Hz
150 Fmodulation > 300 KHz
1
There are two PLL are used in the i.MX35, MPLL and PPLL. Both are based on same DPLL design.

If crystals are used instead of external oscillators, they should meed the following specifications:

Table 29. Clock Input Tolerance

Parameters OSC24M OSC_AUDIO

Normal Frequency 24 MHz 25.576 MHz

Frequency Tolerance 30 ppm 20 ppm (high quality)

ESR <80 Ω <80 Ω

Load Capacitance 8 pF-12 pF 8 pF-12 pF

Shunt capacitance <7 pF <7 pF

Level of drive >150 μW >150 μW

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4.9.4 Embedded Trace Macrocell (ETM) Electrical Specifications
ETM is an ARM protocol. The timing specifications in this section are given as a guide for a test point
access (TPA) that supports TRACECLK frequencies up to 133 MHz.
Figure 9 depicts the TRACECLK timings of ETM, and Table 30 lists the timing parameters.

Figure 9. ETM TRACECLK Timing Diagram

Table 30. ETM TRACECLK Timing Parameters

ID Parameter Min. Max. Unit

Tcyc Clock period Frequency dependent — ns

Twl Low pulse width 2 — ns

Twh High pulse width 2 — ns

Tr Clock and data rise time — 3 ns

Tf Clock and data fall time — 3 ns

Figure 10 depicts the setup and hold requirements of the trace data pins with respect to TRACECLK, and
Table 31 lists the timing parameters.

Figure 10. Trace Data Timing Diagram

Table 31. ETM Trace Data Timing Parameters

ID Parameter Min. Max. Unit

Ts Data setup 2 — ns

Th Data hold 1 — ns

4.9.4.1 Half-Rate Clocking Mode

When half-rate clocking is used, the trace data signals are sampled by the TPA on both the rising and falling
edges of TRACECLK, where TRACECLK is half the frequency of the clock shown in Figure 10. The same
Ts and Th parameters from Table 31 still apply with respect to the falling edge of the TRACECLK signal.

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32 Freescale Semiconductor
4.9.5 EMI Electrical Specifications
This section provides electrical parametrics and timing for the EMI module.

4.9.5.1 NAND Flash Controller Interface (NFC)

The i.MX35 NFC supports normal timing mode, using two flash clock cycles for one access of RE and
WE. AC timings are provided as multiplications of the clock cycle and fixed delay. Figure 11, Figure 12,
Figure 13, and Figure 14 depict the relative timing requirements among different signals of the NFC at
module level for normal mode. Table 32 lists the timing parameters.

NFCLE
NF1 NF2

NF3 NF4

NFCE

NF5

NFWE

NF6 NF7

NFALE

NF8
NF9

NFIO[7:0] Command

Figure 11. Command Latch Cycle Timing DIagram

NFCLE
NF1

NF3 NF4

NFCE

NF10
NF11
NF5

NFWE
NF6 NF7

NFALE

NF8
NF9

NFIO[7:0] Address

Figure 12. Address Latch Cycle Timing DIagram

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Freescale Semiconductor 33
 NFCLE
NF1

NF3

NFCE

NF10
NF11
NF5

NFWE

NF6 NF7

NFALE

NF8
NF9

NFIO[15:0] Data to NF

Figure 13. Write Data Latch Cycle Timing DIagram

NFCLE

NFCE

NF14
NF15
NF13

NFRE

NF16 NF17

NFRB

NF12

NFIO[15:0] Data from NF

Figure 14. Read Data Latch Cycle Timing DIagram

Table 32. NFC Timing Parameters1

Example Timing for

NFC Clock ≈ 33 MHz
Timing
T = NFC Clock Cycle2
ID Parameter Symbol T = 30 ns Unit

Min. Max. Min. Max.

NF1 NFCLE setup time tCLS T – 4.0 ns — 26 — ns

NF2 NFCLE hold time tCLH T – 5.0 ns — 25 — ns
NF3 NFCE setup time tCS T – 2.0 ns — 28 — ns
NF4 NFCE hold time tCH T – 1.0 ns — 29 — ns

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 Table 32. NFC Timing Parameters1 (continued)

Example Timing for

NFC Clock ≈ 33 MHz
Timing
T = NFC Clock Cycle2
ID Parameter Symbol T = 30 ns Unit

Min. Max. Min. Max.

NF5 NF_WP pulse width tWP T – 1.0 ns 29 ns

NF6 NFALE setup time tALS T – 4.0 ns — 26 — ns
NF7 NFALE hold time tALH T – 4.5 ns — 25.5 — ns
NF8 Data setup time tDS T – 2.0 ns — 28 — ns
NF9 Data hold time tDH T – 5.0 ns — 25 — ns
NF10 Write cycle time tWC 2T – 3.0 ns 57 ns
NF11 NFWE hold time tWH T – 5.0 ns 25 ns
NF12 Ready to NFRE low tRR 6T — 180 — ns
NF13 NFRE pulse width tRP 1.5T – 1.0 ns — 44 — ns
NF14 READ cycle time tRC 2T – 5.5 ns — 54.5 — ns
NF15 NFRE high hold time tREH 0.5T – 4.0 ns 11 — ns
NF16 Data setup on READ tDSR N/A 9 — ns
NF17 Data hold on READ tDHR N/A 0 — ns
1 The flash clock maximum frequency is 50 MHz.
2
Subject to DPLL jitter specification listed in Table 28, "DPLL Specifications," on page 31.

NOTE
High is defined as 80% of signal value and low is defined as 20% of signal
value.
Timing for HCLK is 133 MHz and internal NFC clock (flash clock) is
approximately 33 MHz (30 ns). All timings are listed according to this NFC
clock frequency (multiples of NFC clock phases), except NF16 and NF17,
which are not NFC clock related.

4.9.5.2 Wireless External Interface Module (WEIM)

All WEIM output control signals may be asserted and deasserted by internal clocks related to the BCLK
rising edge or falling edge according to the corresponding assertion or negation control fields. The address
always begins related to BCLK falling edge but may be ended both on rising and falling edge in muxed
mode according to control register configuration. Output data begins related to BCLK rising edge except
in muxed mode where both rising and falling edge may be used according to control register configuration.

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Freescale Semiconductor 35
Input data, ECB and DTACK all captured according to BCLK rising edge time. Figure 15 depicts the
timing of the WEIM module, and Table 33 lists the timing parameters.
WEIM Output Timing
WE1 WE2 WE3
BCLK ...
WE4 WE5
Address
WE6 WE7
CSx_B

WE8 WE9
RW_B

OE_B WE10 WE11

WE12 WE13
EBy_B

LBA_B WE14 WE15

WE16 WE17
Output Data

WEIM Input Timing

BCLK
WE18
Input Data
WE20
WE22
ECB_B
WE24
WE26
DTACK_B
WE27

Figure 15. WEIM Bus Timing Diagram

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36 Freescale Semiconductor
 Table 33. WEIM Bus Timing Parameters1

ID Parameter Min. Max. Unit

WE1 BCLK cycle time2 14.5 — ns

WE2 BCLK low-level width2 7 — ns

WE3 BCLK high-level width2 7 — ns

WE4 Address valid to Clock rise/fall 15 21 ns

WE5 Clock rise/fall to address invalid 22 25 ns

WE6 Clock rise/fall to CSx_B valid 15 19 ns

WE7 Clock rise/fall to CSx_B invalid 3.6 5 ns

WE8 Clock rise/fall to RW_B valid 8 12 ns

WE9 Clock rise/fall to RW_B invalid 3 8 ns

WE10 Clock rise/fall to OE_B valid 7 12 ns

WE11 Clock rise/fall to OE_B invalid 3.8 5.5 ns

WE12 Clock rise/fall to EBy_B valid 6 11.5 ns

WE13 Clock rise/fall to EBy_B invalid 6 10 ns

WE14 Clock rise/fall to LBA_B valid 17.5 20 ns

WE15 Clock rise/fall to LBA_B invalid 0 1 ns

WE16 Clock rise/fall to Output Data valid 5 10 ns

WE17 Clock rise to Output Data invalid 0 2.5 ns

WE18 Input Data Valid to Clock rise3 1 — ns

WE19 Input Data Valid to Clock rise, FCE=0 (in the case there is ECB_B asserted (BCLK/2) — ns
during access) + 3.01

WE19 Input Data Valid to Clock rise, FCE=0 (in the case there is NO ECB_B 6.9 — ns
asserted during access)

WE20 Clock rise to Input Data invalid3 1 — ns

WE22 ECB_B setup time3 5 — ns

WE24 ECB_B hold time3 0 — ns

WE26 DTACK_B setup time 5.4 — ns

WE27 DTACK_B hold time –3.2 — ns

1
“High” is defined as 80% of signal value, and “low” is defined as 20% of signal value.
2 BCLK parameters are measured from the 50% point. For example, “high” is defined as 50% of signal value and “low” is defined
as 50% of signal value.
3 Parameters W18, W20, W22, and W24 are tested when FCE=1. i.MX35 does not support FCE=0.

NOTE
Test conditions: load capacitance, 25 pF. Recommended drive strength for
all controls, address, and BCLK is set to maximum drive.

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Freescale Semiconductor 37
 Recommended drive strength for all controls, address and BCLK is set to
maximum drive.
Figure 16 through Figure 21 depict some examples of basic WEIM accesses to external memory devices
with the timing parameters mentioned in Table 33 for specific control parameter settings.

BCLK
WE4 WE5
ADDR Last Valid Address V1 Next Address
WE6 WE7
CS[x]

RW

WE14 WE15
LBA

WE10 WE11
OE

WE12 WE13
EB[y]

WE20, WE21
DATA V1

WE18, WE 19

Figure 16. Synchronous Memory Timing Diagram for Read Access—WSC = 1

BCLK
WE4 WE5
ADDR Last Valid Address V1 Next Address
WE6 WE7
CS[x]

WE8 WE9
RW

WE14 WE15
LBA

OE

WE12 WE13
EB[y]

WE17
DATA V1
WE16

Figure 17. Synchronous Memory Timing Diagram for Write Access—

WSC = 1, EBWA = 1, EBWN = 1, LBN = 1

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 BCLK
WE4 WE5
ADDR Last Valid Addr Address V1 Address V2
WE6 WE7
CS[x]

RW

WE14 WE15
LBA

WE10 WE11
OE

WE12 WE13
EB[y]

WE24, WE25 WE24, WE25

ECB
WE22, WE23
WE22, WE23
WE20, WE21 WE20, WE21
V1 V1+2 V2 V2+2
DATA Halfword Halfword Halfword Halfword
WE18, WE19
WE18, WE19
Figure 18. Synchronous Memory Timing Diagram for Two Non-Sequential Read Accesses—
WSC = 2, SYNC = 1, DOL = 0

BCLK
WE4 WE5
ADDR Last Valid Addr Address V1
WE6 WE7
CS[x]

WE8 WE9
RW

WE14 WE15
LBA

OE

WE12 WE13
EB[y]

WE24, WE25
ECB
WE22, WE23
WE17
WE17

DATA V1 V1+4 V1+8 V1+12

WE16 WE16

Figure 19. Synchronous Memory TIming Diagram for Burst Write Access—
BCS = 1, WSC = 4, SYNC = 1, DOL = 0, PSR = 1

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 BCLK
WE4 WE5 WE17
ADDR/
M_DATA Last Valid Addr Address V1 Write Data
WE6 WE16 WE7
CS[x]

WE8 WE9
RW
Write
WE14 WE15
LBA

OE

WE12 WE13
EB[y]

Figure 20. Muxed A/D Mode Timing Diagram for Synchronous Write Access—
WSC = 7, LBA = 1, LBN = 1, LAH = 1

BCLK
WE4 WE5 WE20, WE21
ADDR/
Last Valid Addr Address V1 Read Data
M_DATA
WE6 WE18, WE19
CS[x]

WE7
RW
WE14
WE15
LBA

WE10 WE11
OE

WE12 WE13
EB[y]

Figure 21. Muxed A/D Mode Timing Diagram for Synchronous Read Access—
WSC = 7, LBA = 1, LBN = 1, LAH = 1, OEA = 7

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40 Freescale Semiconductor
Figure 22 through Figure 26, and Table 34 help to determine timing parameters relative chip select (CS)
state for asynchronous and DTACK WEIM accesses with corresponding WEIM bit fields and the timing
parameters mentioned above.

CS [x]
WE31 WE32
ADDR Last Valid Address Address V1 Next Address

RW
WE39 WE40
LBA
WE35 WE36
OE
WE37 WE38
EB[y] WE44

DATA V1
WE43

Figure 22. Asynchronous Memory Read Access

CS[x]
WE31 MAXDI
ADDR/ Addr. V1 D(V1)
M_DATA WE32A
WE44

WE
WE40
WE39
LBA

WE35A WE36
OE
WE37 WE38
BE[y]
MAXCO

Figure 23. Asynchronous A/D muxed Read Access (RWSC = 5)

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 CS[x]
WE31 WE32
ADDR Last Valid Address Address V1 Next Address
WE33 WE34
RW
WE39 WE40
LBA

OE
WE45 WE46
BE[y]
WE42
DATA D(V1)
WE41

Figure 24. Asynchronous Memory Write Access

CS[x]

WE31 WE41

ADDR/ Addr. V1 D(V1)

M_DATA WE32A
WE42
WE33 WE34
RW
WE40A
WE39
LBA

OE
WE45 WE46
BE[y]
WE42

Figure 25. Asynchronous A/D Mux Write Access

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42 Freescale Semiconductor
 CS [x]
WE31 WE32
ADDR Last Valid Address Address V1 Next Address

RW
WE39 WE40
LBA
WE35 WE36
OE
WE37 WE38
EB[y] WE44

DATA V1
WE43
WE48

DATA
WE47

Figure 26. DTACK Read Access

Table 34. WEIM Asynchronous Timing Parameters Relative Chip Select Table

Determination By Max
Ref No. Parameter Synchronous Measured Min (If 133 MHz is Unit
Parameters1 supported by SoC)

WE31 CS[x] valid to Address valid WE4 – WE6 – CSA2 — 3 – CSA ns

WE32 Address invalid to CS[x] invalid WE7 – WE5 – CSN3 — 3 – CSN ns

WE32A( CS[x] valid to address invalid WE4 – WE7 + (LBN + LBA + 1 –3 + (LBN + LBA + — ns
muxed – CSA2) 1 – CSA)
A/D

WE33 CS[x] valid to WE valid WE8 – WE6 + (WEA – CSA) — 3 + (WEA – CSA) ns

WE34 WE invalid to CS[x] invalid WE7 – WE9 + (WEN – CSN) — 3 – (WEN_CSN) ns

WE35 CS[x] valid to OE valid WE10 – WE6 + (OEA – CSA) — 3 + (OEA – CSA) ns

WE35A CS[x] valid to OE valid WE10 – WE6 + (OEA + RLBN –3 + (OEA + 3 + (OEA + RLBN + ns
(muxed + RLBA + ADH + 1 – CSA) RLBN + RLBA + RLBA + ADH + 1 –
A/D) ADH + 1 – CSA) CSA)

WE36 OE invalid to CS[x] invalid WE7 – WE11 + (OEN – CSN) — 3 – (OEN – CSN) ns

WE37 CS[x] valid to BE[y] valid (read WE12 – WE6 + (RBEA – CSA) — 3 + (RBEA4 – CSA) ns
access)

WE38 BE[y] invalid to CS[x] invalid WE7 – WE13 + (RBEN – CSN) — 3 – (RBEN5 – CSN) ns
(read access)

WE39 CS[x] valid to LBA valid WE14 – WE6 + (LBA – CSA) — 3 + (LBA – CSA) ns

WE40 LBA invalid to CS[x] invalid WE7 – WE15 – CSN — 3 – CSN ns

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 Table 34. WEIM Asynchronous Timing Parameters Relative Chip Select Table (continued)

Determination By Max
Ref No. Parameter Synchronous Measured Min (If 133 MHz is Unit
Parameters1 supported by SoC)

WE40A CS[x] valid to LBA invalid WE14 – WE6 + (LBN + LBA + 1 –3 + (LBN + LBA + 3 + (LBN + LBA + 1 – ns
(muxed – CSA) 1 – CSA) CSA)
A/D)
WE41 CS[x] valid to Output Data valid WE16 – WE6 – WCSA — 3 – WCSA ns
WE41A CS[x] valid to Output Data valid WE16 – WE6 + (WLBN + — 3 + (WLBN + WLBA + ns
(muxed WLBA + ADH + 1 – WCSA) ADH + 1 – WCSA)
A/D)
WE42 Output Data invalid to CS[x] WE17 – WE7 – CSN — 3 – CSN ns
Invalid
WE43 Input Data valid to CS[x] invalid MAXCO – MAXCSO + MAXDI MAXCO6 – — ns
MAXCSO7 +
MAXDI8
WE44 CS[x] invalid to Input Data 0 0 — ns
invalid
WE45 CS[x] valid to BE[y] valid (write WE12 – WE6 + (WBEA – CSA) — 3 + (WBEA – CSA) ns
access)
WE46 BE[y] invalid to CS[x] invalid WE7 – WE13 + (WBEN – CSN) — –3 + (WBEN – CSN) ns
(write access)
WE47 DTACK valid to CS[x] invalid MAXCO – MAXCSO + MAXDTI MAXCO6 – — ns
MAXCSO7 +
MAXDTI9
WE48 CS[x] Invalid to DTACK invalid 0 0 — ns
1
For the value of parameters WE4–WE21, see column BCD = 0 in Table 33.
2 CS Assertion. This bit field determines when the CS signal is asserted during read/write cycles.
3 CS Negation. This bit field determines when the CS signal is negated during read/write cycles.
4 BE Assertion. This bit field determines when the BE signal is asserted during read cycles.
5 BE Negation. This bit field determines when the BE signal is negated during read cycles.
6
Output maximum delay from internal driving ADDR/control FFs to chip outputs.
7 Output maximum delay from CS[x] internal driving FFs to CS[x] out.
8 DATA maximum delay from chip input data to its internal FF.
9 DTACK maximum delay from chip dtack input to its internal FF.

Note: All configuration parameters (CSA, CSN, WBEA, WBEN, LBA, LBN, OEN, OEA, RBEA, and RBEN) are in cycle units.

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4.9.5.3 ESDCTL Electrical Specifications
Figure 27 through Figure 35 depict the timings pertaining to the ESDCTL module, which interfaces with
mobile DDR or SDR SDRAM. Table 35 through Table 45 list the timing parameters.
SD1
SDCLK
SDCLK
SD2
SD4 SD3
CS

SD5
SD4
RAS

SD5
SD4
CAS

SD4 SD5

SD5
WE

SD6
SD7
ADDR ROW/BA COL/BA
SD8
SD10 SD9
DQ Data

SD4
DQM

Note: CKE is high during the read/write cycle.

SD5
Figure 27. SDRAM Read Cycle Timing Diagram

Table 35. DDR/SDR SDRAM Read Cycle Timing Parameters

ID Parameter Symbol Min. Max. Unit

SD1 SDRAM clock high-level width tCH 3.4 4.1 ns

SD2 SDRAM clock low-level width tCL 3.4 4.1 ns
SD3 SDRAM clock cycle time tCK 7.0 — ns
SD4 CS, RAS, CAS, WE, DQM, CKE setup time tCMS 2.0 — ns
SD5 CS, RAS, CAS, WE, DQM, CKE hold time tCMH 1.8 — ns
SD6 Address setup time tAS 2.0 — ns

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 Table 35. DDR/SDR SDRAM Read Cycle Timing Parameters (continued)

ID Parameter Symbol Min. Max. Unit

SD7 Address hold time tAH 1.8 — ns

SD8 SDRAM access time tAC — 6.47 ns
1
SD9 Data out hold time tOH 1.2 — ns
SD10 Active to read/write command period tRC 10 — clock

1
Timing parameters are relevant only to SDR SDRAM. For the specific DDR SDRAM data related timing parameters, see
Table 44 and Table 45.

NOTE
SDR SDRAM CLK parameters are measured from the 50% point—that is,
high is defined as 50% of signal value and low is defined as 50% of signal
value. SD1 + SD2 does not exceed 7.5 ns for 133 MHz.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is, Table 35 indicates SDRAM requirements. All output signals
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.

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 SD1
SDCLK
SDCLK
SD2
SD3
SD4

CS

SD5

RAS

SD4

CAS

SD5

SD4 SD4

WE
SD5 SD5

SD7
SD6
ADDR
BA ROW / BA COL/BA

SD13 SD14
DQ
DATA

DQM

Figure 28. SDR SDRAM Write Cycle Timing Diagram

Table 36. SDR SDRAM Write Timing Parameters

ID Parameter Symbol Min. Max. Unit

SD1 SDRAM clock high-level width tCH 0.45 0.55 ns

SD2 SDRAM clock low-level width tCL 0.45 0.55 ns
SD3 SDRAM clock cycle time tCK 7.0 — ns
SD4 CS, RAS, CAS, WE, DQM, CKE setup time tCMS 2.4 — ns
SD5 CS, RAS, CAS, WE, DQM, CKE hold time tCMH 1.4 — ns
SD6 Address setup time tAS 2.4 — ns
SD7 Address hold time tAH 1.4 — ns
SD13 Data setup time tDS 2.4 — ns
SD14 Data hold time tDH 1.4 — ns

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 NOTE
Test conditions are: pin voltage 1.7 V–1.95 V, capacitance 15 pF for all pins
(both DDR and non-DDR pins), drive strength is high (7.2 mA). “High” is
defined as 80% of signal value and “low” is defined as 20% of signal value.
SDR SDRAM CLK parameters are measured from the 50% point—that is,
“high” is defined as 50% of signal value, and “low” is defined as 50% of
signal value. tCH + tCL will not exceed 7.5 ns for 133 MHz. DDR SDRAM
CLK parameters are measured at the crossing point of SDCLK and SDCLK
(inverted clock).
The timing parameters are similar to the ones used in SDRAM data sheets.
Table 36 indicates SDRAM requirements. All output signals are driven by
the ESDCTL at the negative edge of SDCLK, and the parameters are
measured at maximum memory frequency.

SD1
SDCLK
SDCLK
SD2
SD3
CS

RAS

SD11

CAS

SD10 SD10

WE

SD7
SD6

ADDR BA ROW/BA

Figure 29. SDRAM Refresh Timing Diagram

Table 37. SDRAM Refresh Timing Parameters

ID Parameter Symbol Min. Max. Unit

SD1 SDRAM clock high-level width tCH 3.4 4.1 ns

SD2 SDRAM clock low-level width tCL 3.4 4.1 ns
SD3 SDRAM clock cycle time tCK 7.5 — ns
SD6 Address setup time tAS 1.8 — ns

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 Table 37. SDRAM Refresh Timing Parameters (continued)

ID Parameter Symbol Min. Max. Unit

SD7 Address hold time tAH 1.8 — ns

SD10 Precharge cycle period1 tRP 1 4 clock
1
SD11 Auto precharge command period tRC 2 20 clock

1
SD10 and SD11 are determined by SDRAM controller register settings.

NOTE
SDR SDRAM CLK parameters are measured from the 50% point—that is,
“high” is defined as 50% of signal value and “low” is defined as 50% of
signal value.
The timing parameters are similar to the ones used in SDRAM data sheets.
Table 37 indicates SDRAM requirements. All output signals are driven by
the ESDCTL at the negative edge of SDCLK, and the parameters are
measured at maximum memory frequency.

SDCLK

CS

RAS

CAS

WE

ADDR BA

SD16 SD16
CKE

Don’t care

Figure 30. SDRAM Self-Refresh Cycle Timing Diagram

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 NOTE
The clock will continue to run unless both CKEs are low. Then the clock will
be stopped in low state.
Table 38. SDRAM Self-Refresh Cycle Timing Parameters

ID Parameter Symbol Min. Max. Unit

SD16 CKE output delay time tCKS 1.8 — ns

DDR1
SDCLK
SDCLK
DDR2
DDR4 DDR3
CS

DDR4 DDR5
RAS

DDR5
DDR4
CAS

DDR4
DDR5 DDR5

WE

CKE

DDR6 DDR4
DDR7
ADDR ROW/BA COL/BA

Figure 31. DDR2 SDRAM Basic Timing Parameters

Table 39. DDR2 SDRAM Timing Parameter Table

DDR2-400
ID PARAMETER Symbol Unit
Min Max

DDR1 SDRAM clock high-level width tCH 0.45 0.55 tCK

DDR2 SDRAM clock low-level width tCL 0.45 0.55 tCK
DDR3 SDRAM clock cycle time tCK 7.0 8.0 ns
DDR4 CS, RAS, CAS, CKE, WE setup time tIS1 1.5 — ns

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 Table 39. DDR2 SDRAM Timing Parameter Table

DDR2-400
ID PARAMETER Symbol Unit
Min Max

DDR5 CS, RAS, CAS, CKE, WE hold time tIH1 1.25 — ns

1
DDR6 Address output setup time tIS 1.5 — ns
DDR7 Address output hold time tIH1 1.5 — ns

NOTE
These values are for command/address slew rate of 1 V/ns and SDCLK,
SDCLK_B differential slew rate of 2 V/ns. For different values, use the
derating table.
Table 40. Derating Values for DDR2–400, DDR2–533

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 SDCLK

SDCLK_B
DDR21 DDR22 DDR20
DDR23 DDR19
DQS (output)
DDR18
DDR17 DDR17 DDR18
DQ (output) Data Data Data Data Data Data Data Data

DQM (output) DM DM DM DM DM DM DM DM

DDR17 DDR17
DDR18 DDR18

Figure 32. DDR2 SDRAM Write Cycle Timing Diagram

Table 41. DDR2 SDRAM Write Cycle Parameters

DDR2-400
ID PARAMETER Symbol Unit
Min Max

DDR17 DQ and DQM setup time to DQS (single-ended strobe) tDS1(base) 0.5 — ns
DDR18 DQ and DQM hold time to DQS (single-ended strobe) tDH1(base) 0.5 — ns
DDR19 Write cycle DQS falling edge to SDCLK output setup time. tDSS 0.2 — tCK
DDR20 Write cycle DQS falling edge to SDCLK output hold time. tDSH 0.2 — tCK
DDR21 DQS latching rising transitions to associated clock edges tDQSS –0.25 0.25 tCK
DDR22 DQS high level width tDQSH 0.35 — tCK
DDR23 DQS low level width tDQSL 0.35 — tCK

NOTE
These values are for DQ/DM slew rate of 1 V/ns and DQS slew rate of
1 V/ns. For different values use the derating table.

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 Table 42. DDR Single-ended Slew Rate

NOTE
SDR SDRAM CLK parameters are measured from the 50% point—that is,
“high” is defined as 50% of signal value and “low” is defined as 50% of
signal value. DDR SDRAM CLK parameters are measured at the crossing
point of SDCLK and SDCLK (inverted clock).
Test conditions are: Capacitance 15 pF for DDR PADS. Recommended
drive strength is Medium for SDCLK and High for Address and controls.

SDCLK

SDCLK_B
DDR26
DQS (input)
DDR25
DDR24

DQ (input) DATA DATA DATA DATA DATA DATA DATA DATA

Figure 33. DDR2 SDRAM DQ vs. DQS and SDCLK READ Cycle Timing Diagram

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 Table 43. DDR2 SDRAM Read Cycle Parameter Table

DDR2-400
ID PARAMETER Symbol Unit
Min Max

DDR24 DQS – DQ Skew (defines the Data valid window in tDQSQ — 0.35 ns
read cycles related to DQS).
DDR25 DQS DQ in HOLD time from DQS1 tQH 2.925 — ns
DDR26 DQS output access time from SDCLK posedge tDQSCK –0.5 0.5 ns
1
The value was calculated for an SDCLK frequency of 133 MHz by the formula tQH = tHP – tQHS = min (tCL,tCH) – tQHS =
0.45 × tCK – tQHS = 0.45 × 7.5 – 0.45 = 2.925 ns.

NOTE
SDRAM CLK and DQS-related parameters are measured from the 50%
point—that is, “high” is defined as 50% of signal value and “low” is defined
as 50% of signal value. DDR SDRAM CLK parameters are measured at the
crossing point of SDCLK and SDCLK (inverted clock).
Test conditions are: Capacitance 15 pF for DDR PADS. Recommended
drive strength is Medium for SDCLK and High for Address and controls.

SDCLK
SDCLK

SD19 SD20

DQS (output)
SD18 SD17
SD17 SD18
DQ (output) Data Data Data Data Data Data Data Data

DQM (output) DM DM DM DM DM DM DM DM

SD17 SD17
SD18 SD18

Figure 34. Mobile DDR SDRAM Write Cycle Timing Diagram

Table 44. Mobile DDR SDRAM Write Cycle Timing Parameters1

ID Parameter Symbol Min. Max. Unit

SD17 DQ and DQM setup time to DQS tDS 0.95 — ns

SD18 DQ and DQM hold time to DQS tDH 0.95 — ns
SD19 Write cycle DQS falling edge to SDCLK output delay time. tDSS 1.8 — ns
SD20 Write cycle DQS falling edge to SDCLK output hold time. tDSH 1.8 — ns

1 Test condition: Measured using delay line 5 programmed as follows: ESDCDLY5[15:0] = 0x0703.

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 NOTE
SDRAM CLK and DQS-related parameters are measured from the 50%
point—that is, “high” is defined as 50% of signal value and “low” is defined
as 50% of signal value.
The timing parameters are similar to the ones used in SDRAM data sheets.
Table 44 indicates SDRAM requirements. All output signals are driven by
the ESDCTL at the negative edge of SDCLK, and the parameters are
measured at maximum memory frequency.

SDCLK
SDCLK

SD23

DQS (input)
SD22
SD21
DQ (input) Data Data Data Data Data Data Data Data

Figure 35. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram

Table 45. Mobile DDR SDRAM Read Cycle Timing Parameters

ID Parameter Symbol Min. Max. Unit

SD21 DQS – DQ Skew (defines the Data valid window in read cycles related to DQS). tDQSQ — 0.85 ns
SD22 DQS DQ HOLD time from DQS tQH 2.3 — ns
SD23 DQS output access time from SDCLK posedge tDQSCK — 6.7 ns

NOTE
SDRAM CLK and DQS-related parameters are measured from the 50%
point—that is, “high” is defined as 50% of signal value, and “low” is defined
as 50% of signal value.
The timing parameters are similar to the ones used in SDRAM data sheets.
Table 45 indicates SDRAM requirements. All output signals are driven by
the ESDCTL at the negative edge of SDCLK, and the parameters are
measured at maximum memory frequency.

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4.9.6 Enhanced Serial Audio Interface (ESAI) Timing Specifications
The ESAI consists of independent transmitter and receiver sections, each section with its own clock
generator. Table 46 shows the interface timing values. The number field in the table refers to timing signals
found in Figure 36 and Figure 37.
Table 46. Enhanced Serial Audio Interface Timing

No. Characteristics1,2 Symbol Expression2 Min. Max. Condition3 Unit

62 Clock cycle4 tSSICC 4 × Tc 30.0 — i ck ns

4 × Tc 30.0 — i ck
63 Clock high period ns
• For internal clock — 2 × Tc − 9.0 6 — —

• For external clock — 2 × Tc 15 — —

64 Clock low period ns
• For internal clock — 2 × Tc − 9.0 6 — —

• For external clock — 2 × Tc 15 — —

65 SCKR rising edge to FSR out (bl) high — — — 17.0 x ck ns
— — — 7.0 i ck a
66 SCKR rising edge to FSR out (bl) low — — — 17.0 x ck ns
— — — 7.0 i ck a
67 SCKR rising edge to FSR out (wr) high5 — — — 19.0 x ck ns
— — — 9.0 i ck a
68 SCKR rising edge to FSR out (wr) low5 — — — 19.0 x ck ns
— — — 9.0 i ck a
69 SCKR rising edge to FSR out (wl) high — — — 16.0 x ck ns
— — — 6.0 i ck a
70 SCKR rising edge to FSR out (wl) low — — — 17.0 x ck ns
— — — 7.0 i ck a
71 Data in setup time before SCKR (SCK in synchronous — — 12.0 — x ck ns
mode) falling edge — — 19.0 — i ck
72 Data in hold time after SCKR falling edge — — 3.5 — x ck ns
— — 9.0 — i ck
73 FSR input (bl, wr) high before SCKR falling edge5 — — 2.0 — x ck ns
— — 12.0 — i ck a
74 FSR input (wl) high before SCKR falling edge — — 2.0 — x ck ns
— — 12.0 — i ck a
75 FSR input hold time after SCKR falling edge — — 2.5 — x ck ns
— — 8.5 — i ck a
78 SCKT rising edge to FST out (bl) high — — — 18.0 x ck ns
— — — 8.0 i ck
79 SCKT rising edge to FST out (bl) low — — — 20.0 x ck ns
— — — 10.0 i ck

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 Table 46. Enhanced Serial Audio Interface Timing (continued)

No. Characteristics1,2 Symbol Expression2 Min. Max. Condition3 Unit

80 SCKT rising edge to FST out (wr) high5 — — — 20.0 x ck ns

— — — 10.0 i ck
81 SCKT rising edge to FST out (wr) low5 — — — 22.0 x ck ns
— — — 12.0 i ck
82 SCKT rising edge to FST out (wl) high — — — 19.0 x ck ns
— — — 9.0 i ck
83 SCKT rising edge to FST out (wl) low — — — 20.0 x ck ns
— — — 10.0 i ck
84 SCKT rising edge to data out enable from high — — — 22.0 x ck ns
impedance — — — 17.0 i ck
86 SCKT rising edge to data out valid — — — 18.0 x ck ns
— — — 13.0 i ck
87 SCKT rising edge to data out high impedance 67 — — — 21.0 x ck ns
— — — 16.0 i ck
89 FST input (bl, wr) setup time before SCKT falling edge5 — — 2.0 — x ck ns
— — 18.0 — i ck
90 FST input (wl) setup time before SCKT falling edge — — 2.0 — x ck ns
— — 18.0 — i ck
91 FST input hold time after SCKT falling edge — — 4.0 — x ck ns
— — 5.0 — i ck
1 i ck = internal clock
x ck = external clock
i ck a = internal clock, asynchronous mode
(asynchronous implies that SCKT and SCKR are two different clocks)
i ck s = internal clock, synchronous mode
(synchronous implies that SCKT and SCKR are the same clock)
2
bl = bit length
wl = word length
wr = word length relative
3
SCKT(SCKT pin) = transmit clock
SCKR(SCKR pin) = receive clock
FST(FST pin) = transmit frame sync
FSR(FSR pin) = receive frame sync
HCKT(HCKT pin) = transmit high frequency clock
HCKR(HCKR pin) = receive high frequency clock
4 For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.
5
The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync
signal waveform, but it spreads from one serial clock before the first bit clock (like the bit length frame sync signal), until the
second-to-last bit clock of the first word in the frame.
6 Periodically sampled and not 100% tested.

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Freescale Semiconductor 57
 62
63 64
SCKT
(Input/Output)

78 79

FST (Bit)
Out
82 83

FST (Word)
Out
86 86

84 87

First Bit Last Bit

Data Out

89

91

FST (Bit) In

90 91

FST (Word) In

Figure 36. ESAI Transmitter Timing

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 62

63

SCKR 64
(Input/Output)

65 66
FSR (Bit)
Out

69 70
FSR (Word)
Out

72
71
Data In
First Bit Last Bit

73 75
FSR (Bit)
In
74 75
FSR (Word)
In

Figure 37. ESAI Receiver Timing

4.9.7 eSDHCv2 AC Electrical Specifications

Figure 38 depicts the timing of eSDHCv2, and Table 47 lists the eSDHCv2 timing characteristics. The
following definitions apply to values and signals described in Table 47:
• LS: low-speed mode. Low-speed card can tolerate a clock up to 400 kHz.
• FS: full-speed mode. For a full-speed MMC card, the card clock can reach 20 MHz; a full-speed
SD/SDIO card can reach 25 MHz.
• HS: high-speed mode. For a high-speed MMC card, the card clock can reach 52 MHz; SD/SDIO
can reach 50 MHz.

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 SD4

SD2
SD1
SD5

SDHCx_CLK
SD3
SDHCx_CMD SD6
SDHCx_DAT_0
output from eSDHCv2 to card SDHCx_DAT_1
SDHCx_DAT_7
SD7 SD8

SDHCx_CMD
SDHCx_DAT_0
output from card to eSDHCv2 SDHCx_DAT_1
SDHCx_DAT_7
Figure 38. eSDHCv2 Timing

Table 47. eSDHCv2 Interface Timing Specification

ID Parameter Symbols Min. Max. Unit

Card Input Clock

SD1 Clock frequency (Low Speed) fPP1 0 400 kHz

Clock frequency (SD/SDIO Full Speed/High Speed) fPP2 0 25/50 MHz
Clock frequency (MMC Full Speed/High Speed) fPP3 0 20/52 MHz
Clock frequency (Identification Mode) fOD 100 400 kHz
SD2 Clock Low time tWL 7 — ns
SD3 Clock high time tWH 7 — ns
SD4 Clock rise time tTLH — 3 ns
SD5 Clock fall time tTHL — 3 ns
eSDHC Output/Card Inputs CMD, DAT (Reference to CLK)

SD6 eSDHC output delay tOD –3 3 ns

eSDHC Input/Card Outputs CMD, DAT (Reference to CLK)

SD7 eSDHC input setup time tISU 5 — ns

SD8 eSDHC input hold time tIH4 2.5 — ns
1 In low-speed mode, the card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
2 In normal-speed mode for the SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,
clock frequency can be any value between 0–50 MHz.
3
In normal-speed mode for MMC card, clock frequency can be any value between 0 and 20 MHz. In high-speed mode, clock
frequency can be any value between 0–52 MHz.
4
To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.

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4.9.8 Fast Ethernet Controller (FEC) AC Electrical Specifications
This section describes the electrical information of the FEC module. The FEC is designed to support both
10- and 100-Mbps Ethernet networks. An external transceiver interface and transceiver function are
required to complete the interface to the media. The FEC supports the 10/100 Mbps Media Independent
Interface (MII) using a total of 18 pins. The 10-Mbps 7-wire interface that is restricted to a 10-Mbps data
rate uses seven of the MII pins for connection to an external Ethernet transceiver.

4.9.8.1 FEC AC Timing

This section describes the AC timing specifications of the FEC. The MII signals are compatible with
transceivers operating at a voltage of 3.3 V.

4.9.8.2 MII Receive Signal Timing

The MII receive timing signals consist of FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and
FEC_RX_CLK. The receiver functions correctly up to a FEC_RX_CLK maximum frequency of
25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency
must exceed twice the FEC_RX_CLK frequency. Table 48 lists MII receive channel timings.
Table 48. MII Receive Signal Timing

Num. Characteristic1 Min. Max. Unit

M1 FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup 5 — ns

M2 FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold 5 — ns
M3 FEC_RX_CLK pulse width high 35% 65% FEC_RX_CLK period
M4 FEC_RX_CLK pulse width low 35% 65% FEC_RX_CLK period

1 FEC_RX_DV,
FEC_RX_CLK, and FEC_RXD0 have the same timing when in 10 Mbps 7-wire interface mode.

Figure 39 shows the MII receive signal timings listed in Table 48.

M3

FEC_RX_CLK (input)

M4
FEC_RXD[3:0] (inputs)
FEC_RX_DV
FEC_RX_ER

M1 M2

Figure 39. MII Receive Signal Timing Diagram

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4.9.8.3 MII Transmit Signal Timing
The transmitter timing signals consist of FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and
FEC_TX_CLK. The transmitter functions correctly up to a FEC_TX_CLK maximum frequency of
25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency
must exceed twice the FEC_TX_CLK frequency. Table 49 lists MII transmit channel timings.
Table 49. MII Transmit Signal Timing

Num Characteristic1 Min. Max. Unit

M5 FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER 5 — ns

invalid
M6 FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER — 20 ns
valid
M7 FEC_TX_CLK pulse width high 35% 65% FEC_TX_CLK period
M8 FEC_TX_CLK pulse width low 35% 65% FEC_TX_CLK period

1 FEC_TX_EN,
FEC_TX_CLK, and FEC_TXD0 have the same timing when in 10 Mbps 7-wire interface mode.

Figure 40 shows the MII transmit signal timings listed in Table 49.

M7

FEC_TX_CLK (input)

M5
M8
FEC_TXD[3:0] (outputs)
FEC_TX_EN
FEC_TX_ER

M6

Figure 40. MII Transmit Signal Timing Diagram

4.9.8.4 MII Asynchronous Inputs Signal Timing

The MII asynchronous timing signals are FEC_CRS and FEC_COL. Table 50 lists MII asynchronous
inputs signal timing.
Table 50. MII Asynch Inputs Signal Timing

Num Characteristic Min. Max. Unit

M91 FEC_CRS to FEC_COL minimum pulse width 1.5 — FEC_TX_CLK period

1
FEC_COL has the same timing in 10 Mbit 7-wire interface mode.

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Figure 41 shows MII asynchronous input timings listed in Table 50.

FEC_CRS, FEC_COL

M9

Figure 41. MII Asynch Inputs Timing Diagram

4.9.8.5 MII Serial Management Channel Timing

Serial management channel timing is accomplished using FEC_MDIO and FEC_MDC. The FEC
functions correctly with a maximum MDC frequency of 2.5 MHz. Table 51 lists MII serial management
channel timings.
The MDC frequency should be equal to or less than 2.5 MHz to be compliant with the IEEE 802.3 MII
specification. However the FEC can function correctly with a maximum MDC frequency of 15 MHz.
Table 51. MII Transmit Signal Timing

Num Characteristic Min. Max. Units

M10 FEC_MDC falling edge to FEC_MDIO output invalid (minimum 0 — ns

propagation delay)
M11 FEC_MDC falling edge to FEC_MDIO output valid (max. — 5 ns
propagation delay)
M12 FEC_MDIO (input) to FEC_MDC rising edge setup 18 — ns
M13 FEC_MDIO (input) to FEC_MDC rising edge hold 0 — ns
M14 FEC_MDC pulse width high 40% 60% FEC_MDC period
M15 FEC_MDC pulse width low 40% 60% FEC_MDC period

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Figure 42 shows MII serial management channel timings listed in Table 51.

M14

M15
FEC_MDC (output)

M10

FEC_MDIO (output)

M11

FEC_MDIO (input)

M12 M13

Figure 42. MII Serial Management Channel Timing Diagram

4.9.9 FIR Electrical Specifications

FIR implements asynchronous infrared protocols (FIR, MIR) defined by IrDA® (Infrared Data
Association). Refer to the IrDA® website for details on FIR and MIR protocols.

4.9.10 FlexCAN Module AC Electrical Specifications

The electrical characteristics are related to the CAN transceiver outside the chip. The i.MX35 has two
CAN modules available for systems design. Tx and Rx ports for both modules are multiplexed with other
I/O pins. Refer to the IOMUX chapter of the MCIMX35 Multimedia Applications Processor Reference
Manual to see which pins expose Tx and Rx pins; these ports are named TXCAN and RXCAN,
respectively.

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4.9.11 I2C AC Electrical Specifications
This section describes the electrical characteristics of the I2C module.

4.9.11.1 I2C Module Timing

Figure 43 depicts the timing of the I2C module. Table 52 lists the I2C module timing parameters.

IC10 IC11 IC9

I2DAT

IC2 IC8 IC4 IC7 IC3

I2CLK

START IC10 IC11 START STOP START

IC6 IC5
IC1

Figure 43. I2C Bus Timing Diagram

Table 52. I2C Module Timing Parameters

Standard Mode Fast Mode

ID Parameter Unit
Min. Max. Min. Max.

IC1 I2CLK cycle time 10 — 2.5 — μs

IC2 Hold time (repeated) START condition 4.0 — 0.6 — μs
IC3 Set-up time for STOP condition 4.0 — 0.6 — μs
IC4 Data hold time 01 3.452 01 0.92 μs
IC5 HIGH Period of I2CLK Clock 4.0 — 0.6 — μs
IC6 LOW Period of the I2CLK Clock 4.7 — 1.3 — μs
IC7 Set-up time for a repeated START condition 4.7 — 0.6 — μs
IC8 Data set-up time 250 — 1003 — ns
IC9 Bus free time between a STOP and START condition 4.7 — 1.3 — μs
IC10 Rise time of both I2DAT and I2CLK signals — 1000 — 300 ns
IC11 Fall time of both I2DAT and I2CLK signals — 300 — 300 ns
IC12 Capacitive load for each bus line (Cb) — 400 — 400 pF
1
A device must internally provide a hold time of at least 300 ns for the I2DAT signal in order to bridge the undefined region of
the falling edge of I2CLK.
2 The maximum hold time has to be met only if the device does not stretch the LOW period (ID IC6) of the I2CLK signal.
3 A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement of set-up time (ID IC7) of
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the I2CLK signal.
If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line
max_rise_time (ID No IC10) + data_setup_time (ID No IC8) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus
specification) before the I2CLK line is released.

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4.9.12 IPU—Sensor Interfaces
This section contains a list of supported camera sensors, a functional description, and the electrical
characteristics.

4.9.12.1 Supported Camera Sensors

Table 53 lists the known supported camera sensors at the time of publication.
Table 53. Supported Camera Sensors1

Vendor Model

Conexant CX11646, CX204902, CX204502

Agilant HDCP–2010, ADCS–10212, ADCS–10212
Toshiba TC90A70
ICMedia ICM202A, ICM1022
iMagic IM8801
Transchip TC5600, TC5600J, TC5640, TC5700, TC6000
Fujitsu MB86S02A
Micron MI-SOC–0133
Matsushita MN39980
STMicro W6411, W6500, W65012, W66002, W65522, STV09742
OmniVision OV7620, OV6630, OV2640
Sharp LZ0P3714 (CCD)
Motorola MC30300 (Python)2, SCM200142, SCM201142, SCM221142, SCM200272
National Semiconductor LM96182

1 Freescale Semiconductor does not recommend one supplier over another and in no way suggests that these are the only
camera suppliers.
2 These sensors have not been validated at the time of publication.

4.9.12.2 Functional Description

There are three timing modes supported by the IPU.

4.9.12.2.1 Pseudo BT.656 Video Mode

Smart camera sensors, which typically include image processing capability, support video mode transfer
operations. They use an embedded timing syntax to replace the SENSB_VSYNC and SENSB_HSYNC
signals. The timing syntax is defined by the BT.656 standard.
This operation mode follows the recommendations of the ITU BT.656 specifications. The only control
signal used is SENSB_PIX_CLK. Start-of-frame and active-line signals are embedded in the data stream.
An active line starts with a SAV code and ends with an EAV code. In some cases, digital blanking is

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inserted in between EAV and SAV code. The CSI decodes and filters out the timing coding from the data
stream, thus recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use.

4.9.12.2.2 Gated Clock Mode

The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See
Figure 44.
Active Line
Start of Frame

nth frame n+1th frame

SENSB_VSYNC

SENSB_HSYNC

SENSB_PIX_CLK

SENSB_DATA[9:0] invalid invalid

1st byte 1st byte

Figure 44. Gated Clock Mode Timing Diagram

A frame starts with a rising edge on SENSB_VSYNC (all the timing corresponds to straight polarity of the
corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. The pixel clock
is valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks.
SENSB_HSYNC goes to low at the end of the line. Pixel clocks then become invalid and the CSI stops
receiving data from the stream. For the next line, the SENSB_HSYNC timing repeats. For the next frame,
the SENSB_VSYNC timing repeats.

4.9.12.2.3 Non-Gated Clock Mode

The timing is the same as the gated-clock mode (described in Section 4.9.12.2.2, “Gated Clock Mode”),
except for the SENSB_HSYNC signal, which is not used. See Figure 45. All incoming pixel clocks are
valid and will cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states
low) until valid data is going to be transmitted over the bus.
Start of Frame

nth frame n+1th frame

SENSB_VSYNC

SENSB_PIX_CLK

SENSB_DATA[7:0] invalid invalid

1st byte 1st byte

Figure 45. Non-Gated Clock Mode Timing Diagram

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The timing described in Figure 45 is that of a Motorola sensor. Some other sensors may have slightly
different timing. The CSI can be programmed to support rising/falling-edge triggered SENSB_VSYNC;
active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK.

4.9.12.3 Electrical Characteristics

Figure 46 depicts the sensor interface timing, and Table 54 lists the timing parameters.
1/IP1

SENSB_MCLK
(Sensor Input)

SENSB_PIX_CLK
(Sensor Output)
IP3 IP2 1/IP4

SENSB_DATA,
SENSB_VSYNC,
SENSB_HSYNC

Figure 46. Sensor Interface Timing Diagram

Table 54. Sensor Interface Timing Parameters

ID Parameter Symbol Min. Max. Units

IP1 Sensor input clock frequency Fmck 0.01 133 MHz

IP2 Data and control setup time Tsu 5 — ns
IP3 Data and control holdup time Thd 3 — ns
IP4 Sensor output (pixel) clock frequency Fpck 0.01 133 MHz

4.9.13 IPU—Display Interfaces

This section describes the following types of display interfaces:
• Section 4.9.13.1, “Synchronous Interfaces”
• Section 4.9.13.2, “Interface to Sharp HR-TFT Panels”
• Section 4.9.13.3, “Synchronous Interface to Dual-Port Smart Displays”
• Section 4.9.13.4, “Asynchronous Interfaces”
• Section 4.9.13.5, “Serial Interfaces, Functional Description”

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4.9.13.1 Synchronous Interfaces
This section discusses the interfaces to active matrix TFT LCD panels, Sharp HR-TFT, and dual-port smart
displays.

4.9.13.1.4 Interface to Active Matrix TFT LCD Panels, Functional Description

Figure 47 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure,
signals are shown with negative polarity. The sequence of events for active matrix interface timing is as
follows:
• DISPB_D3_CLK latches data into the panel on its negative edge (when positive polarity is
selected). In active mode, DISPB_D3_CLK runs continuously.
• DISPB_D3_HSYNC causes the panel to start a new line.
• DISPB_D3_VSYNC causes the panel to start a new frame. It always encompasses at least one
HSYNC pulse.
• DISPB_D3_DRDY acts like an output enable signal to the CRT display. This output enables the
data to be shifted to the display. When disabled, the data is invalid and the trace is off.

DISPB_D3_VSYNC

DISPB_D3_HSYNC
LINE 1 LINE 2 LINE 3 LINE 4 LINE n – 1 LINE n

DISPB_D3_HSYNC

DISPB_D3_DRDY

1 2 3 m–1 m
DISPB_D3_CLK

DISPB_D3_DATA

Figure 47. Interface Timing Diagram for TFT (Active Matrix) Panels

4.9.13.1.5 Interface to Active Matrix TFT LCD Panels, Electrical Characteristics

Figure 48 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and
the data. All figure parameters shown are programmable. The timing images correspond to inverse polarity

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of the DISPB_D3_CLK signal and active-low polarity of the DISPB_D3_HSYNC, DISPB_D3_VSYNC
and DISPB_D3_DRDY signals.

IP7

IP9 IP6 IP10

IP8

Start of line IP5

DISPB_D3_CLK

DISPB_D3_HSYNC

DISPB_D3_DRDY

DISPB_D3_DATA

Figure 48. TFT Panels Timing Diagram—Horizontal Sync Pulse

Figure 49 depicts the vertical timing (timing of one frame). All figure parameters shown are
programmable.
Start of frame End of frame
IP13

DISPB_D3_VSYNC

DISPB_D3_HSYNC

DISPB_D3_DRDY

IP11 IP14 IP15

IP12
Figure 49. TFT Panels Timing Diagram—Vertical Sync Pulse

Table 55 shows timing parameters of signals presented in Figure 48 and Figure 49.
Table 55. Synchronous Display Interface Timing Parameters—Pixel Level

ID Parameter Symbol Value Units

IP5 Display interface clock period Tdicp Tdicp1 ns

IP6 Display pixel clock period Tdpcp (DISP3_IF_CLK_CNT_D + 1) × Tdicp ns
IP7 Screen width Tsw (SCREEN_WIDTH + 1) × Tdpcp ns
IP8 HSYNC width Thsw (H_SYNC_WIDTH + 1) × Tdpcp ns

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 Table 55. Synchronous Display Interface Timing Parameters—Pixel Level (continued)

ID Parameter Symbol Value Units

IP9 Horizontal blank interval 1 Thbi1 BGXP × Tdpcp ns

IP10 Horizontal blank interval 2 Thbi2 (SCREEN_WIDTH – BGXP – FW) × Tdpcp ns
IP11 HSYNC delay Thsd H_SYNC_DELAY × Tdpcp ns
IP12 Screen height Tsh (SCREEN_HEIGHT + 1) × Tsw ns
IP13 VSYNC width Tvsw if V_SYNC_WIDTH_L = 0 than ns
(V_SYNC_WIDTH + 1) × Tdpcp
else
(V_SYNC_WIDTH + 1) × Tsw
IP14 Vertical blank interval 1 Tvbi1 BGYP × Tsw ns
IP15 Vertical blank interval 2 Tvbi2 (SCREEN_HEIGHT – BGYP – FH) × Tsw ns
1
Display interface clock period immediate value

Display interface clock period average value.

DISP3_IF_CLK_PER_WR
Tdicp = T HSP_CLK ⋅ ------------------------------------------------------------------
HSP_CLK_PERIOD

Figure 50 depicts the synchronous display interface timing for access level, and Table 56 lists the timing
parameters. The DISP3_IF_CLK_DOWN_WR and DISP3_IF_CLK_UP_WR parameters are set via the
DI_DISP3_TIME_CONF Register.
IP20
DISPB_D3_VSYNC
DISPB_D3_HSYNC
DISPB_D3_DRDY
other controls
DISPB_D3_CLK

IP16 IP17 IP19 IP18

DISPB_DATA

Figure 50. Synchronous Display Interface Timing Diagram—Access Level

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 Table 56. Synchronous Display Interface Timing Parameters—Access Level

ID Parameter Symbol Min. Typ.1 Max. Units

IP16 Display interface clock low time Tckl Tdicd – Tdicu – 1.5 Tdicd2 – Tdicu3 Tdicd – Tdicu + 1.5 ns
IP17 Display interface clock high time Tckh Tdicp – Tdicd + Tdicp – Tdicd + Tdicp – Tdicd + ns
Tdicu – 1.5 Tdicu Tdicu + 1.5
IP18 Data setup time Tdsu Tdicd – 3.5 Tdicu — ns
IP19 Data holdup time Tdhd Tdicp – Tdicd – 3.5 Tdicp – Tdicu — ns
IP20 Control signals setup time to Tcsu Tdicd – 3.5 Tdicu — ns
display interface clock

1
The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.
These conditions may be device specific.
2 Display interface clock down time
1 2 ⋅ DISP3_IF_CLK_DOWN_WR
Tdicd = --- T HSP_CLK ⋅ ceil ---------------------------------------------------------------------------------
2 HSP_CLK_PERIOD
3
Display interface clock up time
1 2 ⋅ DISP3_IF_CLK_UP_WR
Tdicu = --- T HSP_CLK ⋅ ceil ----------------------------------------------------------------------
2 HSP_CLK_PERIOD

where CEIL(X) rounds the elements of X to the nearest integers toward infinity.

4.9.13.2 Interface to Sharp HR-TFT Panels

Figure 51 depicts the Sharp HR-TFT panel interface timing, and Table 57 lists the timing parameters. The
CLS_RISE_DELAY, CLS_FALL_DELAY, PS_FALL_DELAY, PS_RISE_DELAY,
REV_TOGGLE_DELAY parameters are defined in the SDC_SHARP_CONF_1 and
SDC_SHARP_CONF_2 registers. For other Sharp interface timing characteristics, refer to

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Section 4.9.13.1.5, “Interface to Active Matrix TFT LCD Panels, Electrical Characteristics.” The timing
images correspond to straight polarity of the Sharp signals.
Horizontal timing

DISPB_D3_CLK

DISPB_D3_DATA D1 D2 D320

DISPB_D3_SPL
IP21 1 DISPB_D3_CLK period

DISPB_D3_HSYNC

IP23
IP22

DISPB_D3_CLS

IP24
DISPB_D3_PS

IP25

IP26

DISPB_D3_REV

Example is drawn with FW + 1 = 320 pixel/line, FH + 1 = 240 lines.

SPL pulse width is fixed and aligned to the first data of the line.
REV toggles every HSYNC period.
Figure 51. Sharp HR-TFT Panel Interface Timing Diagram—Pixel Level

Table 57. Sharp Synchronous Display Interface Timing Parameters—Pixel Level

ID Parameter Symbol Value Units

IP21 SPL rise time Tsplr (BGXP – 1) × Tdpcp ns

IP22 CLS rise time Tclsr CLS_RISE_DELAY × Tdpcp ns
IP23 CLS fall time Tclsf CLS_FALL_DELAY × Tdpcp ns
IP24 CLS rise and PS fall time Tpsf PS_FALL_DELAY × Tdpcp ns
IP25 PS rise time Tpsr PS_RISE_DELAY × Tdpcp ns
IP26 REV toggle time Trev REV_TOGGLE_DELAY × Tdpcp ns

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4.9.13.3 Synchronous Interface to Dual-Port Smart Displays
Functionality and electrical characteristics of the synchronous interface to dual-port smart displays are
identical to parameters of the synchronous interface. See Section 4.9.13.1.5, “Interface to Active Matrix
TFT LCD Panels, Electrical Characteristics.”

4.9.13.3.6 Interface to a TV Encoder—Functional Description

The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The bits
D7–D0 of the value are mapped to bits LD17–LD10 of the data bus, respectively. Figure 52 depicts the
interface timing.
• The frequency of the clock DISPB_D3_CLK is 27 MHz.
• The DISPB_D3_HSYNC, DISPB_D3_VSYNC and DISPB_D3_DRDY signals are active low.
• The transition to the next row is marked by the negative edge of the DISPB_D3_HSYNC signal. It
remains low for a single clock cycle.
• The transition to the next field/frame is marked by the negative edge of the DISPB_D3_VSYNC
signal. It remains low for at least one clock cycle.
— At a transition to an odd field (of the next frame), the negative edges of DISPB_D3_VSYNC
and DISPB_D3_HSYNC coincide.
— At a transition to an even field (of the same frame), they do not coincide.
• The active intervals—during which data is transferred—are marked by the DISPB_D3_HSYNC
signal being high.

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 DISPB_D3_CLK

DISPB_D3_HSYNC
DISPB_D3_VSYNC
DISPB_D3_DRDY
DISPB_DATA Cb Y Cr Y Cb Y Cr

Pixel Data Timing

523 524 525 1 2 3 4 5 6 10

DISPB_D3_HSYNC

DISPB_D3_DRDY

DISPB_D3_VSYNC

Even Field Odd Field

261 262 263 264 265 266 267 268 269 273
DISPB_D3_HSYNC

DISPB_D3_DRDY

DISPB_D3_VSYNC

Odd Field Even Field

Line and Field Timing - NTSC

621 622 623 624 625 1 2 3 4 23

DISPB_D3_HSYNC

DISPB_D3_DRDY

DISPB_D3_VSYNC

Even Field Odd Field

308 309 310 311 312 313 314 315 316 336
DISPB_D3_HSYNC

DISPB_D3_DRDY

DISPB_D3_VSYNC

Odd Field Even Field

Line and Field Timing - PAL

Figure 52. TV Encoder Interface Timing Diagram

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4.9.13.3.7 Interface to a TV Encoder, Electrical Characteristics
The timing characteristics of the TV encoder interface are identical to the synchronous display
characteristics. See Section 4.9.13.1.5, “Interface to Active Matrix TFT LCD Panels, Electrical
Characteristics.”

4.9.13.4 Asynchronous Interfaces

This section discusses the asynchronous parallel and serial interfaces.

4.9.13.4.8 Parallel Interfaces, Functional Description

The IPU supports the following asynchronous parallel interfaces:
• System 80 interface
— Type 1 (sampling with the chip select signal) with and without byte enable signals.
— Type 2 (sampling with the read and write signals) with and without byte enable signals.
• System 68k interface
— Type 1 (sampling with the chip select signal) with or without byte enable signals.
— Type 2 (sampling with the read and write signals) with or without byte enable signals.
For each of four system interfaces, there are three burst modes:
1. Burst mode without a separate clock—The burst length is defined by the corresponding parameters
of the IDMAC (when data is transferred from the system memory) or by the HBURST signal (when
the MCU directly accesses the display via the slave AHB bus). For system 80 and system 68k type
1 interfaces, data is sampled by the CS signal and other control signals change only when transfer
direction is changed during the burst. For type 2 interfaces, data is sampled by the WR/RD signals
(system 80) or by the ENABLE signal (system 68k), and the CS signal stays active during the
whole burst.
2. Burst mode with the separate clock DISPB_BCLK—In this mode, data is sampled with the
DISPB_BCLK clock. The CS signal stays active during whole burst transfer. Other controls are
changed simultaneously with data when the bus state (read, write or wait) is altered. The CS
signals and other controls move to non-active state after burst has been completed.
3. Single access mode—In this mode, slave AHB and DMA burst are broken to single accesses. The
data is sampled with CS or other controls according to the interface type as described above. All
controls (including CS) become non-active for one display interface clock after each access. This
mode corresponds to the ATI single access mode.
Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 53,
Figure 54, Figure 55, and Figure 56. These timing images correspond to active-low DISPB_Dn_CS,
DISPB_Dn_WR and DISPB_Dn_RD signals.

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Additionally, the IPU allows a programmable pause between two bursts. The pause is defined in the
HSP_CLK cycles. It allows the prevention of timing violation between two sequential bursts or two
accesses to different displays. The range of this pause is from 4 to 19 HSP_CLK cycles.
DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

DISPB_RD

DISPB_DATA

Burst access mode with sampling by CS signal

DISPB_BCLK
DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

DISPB_RD

DISPB_DATA

Burst access mode with sampling by separate burst clock (BCLK)

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

DISPB_RD

DISPB_DATA

Single access mode (all control signals are not active for one display interface clock after each display access)

Figure 53. Asynchronous Parallel System 80 Interface (Type 1) Burst Mode Timing Diagram

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 DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

DISPB_RD

DISPB_DATA

Burst access mode with sampling by WR/RD signals

DISPB_BCLK
DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

DISPB_RD

DISPB_DATA

Burst access mode with sampling by separate burst clock (BCLK)

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

DISPB_RD

DISPB_DATA

Single access mode (all control signals are not active for one display interface clock after each display access)

Figure 54. Asynchronous Parallel System 80 Interface (Type 2) Burst Mode Timing Diagram

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 DISPB_D#_CS

DISPB_PAR_RS
DISPB_WR
(READ/WRITE)
DISPB_RD
(ENABLE)

DISPB_DATA

Burst access mode with sampling by CS signal

DISPB_BCLK
DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR
(READ/WRITE)
DISPB_RD
(ENABLE)

DISPB_DATA

Burst access mode with sampling by separate burst clock (BCLK)

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR
(READ/WRITE)
DISPB_RD
(ENABLE)

DISPB_DATA

Single access mode (all control signals are not active for one display interface clock after each display access)

Figure 55. Asynchronous Parallel System 68k Interface (Type 1) Burst Mode Timing Diagram

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 DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR
(READ/WRITE)
DISPB_RD
(ENABLE)

DISPB_DATA

Burst access mode with sampling by ENABLE signal

DISPB_BCLK
DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR
(READ/WRITE)
DISPB_RD
(ENABLE)

DISPB_DATA

Burst access mode with sampling by separate burst clock (BCLK)

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR
(READ/WRITE)
DISPB_RD
(ENABLE)

DISPB_DATA

Single access mode (all control signals are not active for one display interface clock after each display access)

Figure 56. Asynchronous Parallel System 68k Interface (Type 2) Burst Mode TIming Diagram

Display read operation can be performed with wait states when each read access takes up to 4 display
interface clock cycles according to the DISP0_RD_WAIT_ST parameter in the

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DI_DISPn_TIME_CONF_3 registers (n = 0,1,2). Figure 57 shows the timing of the parallel interface with
read wait states.

WRITE OPERATION READ OPERATION

DISP0_RD_WAIT_ST=00

DISPB_D#_CS
DISPB_RD

DISPB_WR

DISPB_PAR_RS

DISPB_DATA

DISP0_RD_WAIT_ST=01

DISPB_D#_CS
DISPB_RD

DISPB_WR

DISPB_PAR_RS

DISPB_DATA

DISP0_RD_WAIT_ST=10

DISPB_D#_CS
DISPB_RD

DISPB_WR

DISPB_PAR_RS

DISPB_DATA

Figure 57. Parallel Interface Timing Diagram—Read Wait States

4.9.13.4.9 Parallel Interfaces, Electrical Characteristics

Figure 58, Figure 60, Figure 59, and Figure 61 depict timing of asynchronous parallel interfaces based on
the system 80 and system 68k interfaces. Table 58 lists the timing parameters at display access level. All

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timing images are based on active low control signals (signal polarity is controlled via the
DI_DISP_SIG_POL register).

IP28, IP27

DISPB_PAR_RS

DISPB_RD (READ_L)
DISPB_DATA[17]
(READ_H)

IP35, IP33 IP36, IP34

DISPB_D#_CS

DISPB_WR (WRITE_L)
DISPB_DATA[16]
(WRITE_H)
IP31, IP29 IP32, IP30
read point
IP37 IP38
DISPB_DATA
Read Data
(Input)

IP39 IP40
DISPB_DATA
(Output)

IP46,IP44

IP47

IP45, IP43

IP42, IP41

Figure 58. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram

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 IP28, IP27

DISPB_PAR_RS

DISPB_D#_CS

IP35, IP33 IP36, IP34

DISPB_RD (READ_L)
DISPB_DATA[17]
(READ_H)
DISPB_WR (WRITE_L)
DISPB_DATA[16]
(WRITE_H)
IP31, IP29 IP32, IP30
read point
IP37 IP38

DISPB_DATA Read Data

(Input)

IP39 IP40
DISPB_DATA
(Output)

IP46,IP44

IP47

IP45, IP43

IP42, IP41

Figure 59. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram

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 IP28, IP27

DISPB_PAR_RS

DISPB_RD (ENABLE_L)
DISPB_DATA[17]
(ENABLE_H)

IP35,IP33 IP36, IP34

DISPB_D#_CS

DISPB_WR
(READ/WRITE)

IP31, IP29 IP32, IP30

read point
IP38
IP37

DISPB_DATA Read Data

(Input)

IP39 IP40

DISPB_DATA
(Output)

IP46,IP44

IP47

IP45, IP43

IP42, IP41

Figure 60. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram

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 IP28, IP27

DISPB_PAR_RS

DISPB_D#_CS

IP35,IP33 IP36, IP34

DISPB_RD (ENABLE_L)
DISPB_DATA[17]
(ENABLE_H)

DISPB_WR
(READ/WRITE)

IP31, IP29 IP32, IP30

read point
IP37 IP38

DISPB_DATA Read Data

(Input)

IP39 IP40
DISPB_DATA
(Output)

IP46,IP44

IP47

IP45, IP43

IP42, IP41

Figure 61. Asynchronous Parallel System 68k Interface (Type 2) Timing Diagram

Table 58. Asynchronous Parallel Interface Timing Parameters—Access Level

ID Parameter Symbol Min. Typ.1 Max. Units

IP27 Read system cycle time Tcycr Tdicpr – 1.5 Tdicpr2 Tdicpr + 1.5 ns
IP28 Write system cycle time Tcycw Tdicpw – 1.5 Tdicpw3 Tdicpw + 1.5 ns
IP29 Read low pulse width Trl Tdicdr – Tdicur – 1.5 Tdicdr4 – Tdicur5
Tdicdr – Tdicur + 1.5 ns
IP30 Read high pulse width Trh Tdicpr – Tdicdr + Tdicpr – Tdicdr + Tdicpr – Tdicdr + Tdicur ns
Tdicur – 1.5 Tdicur + 1.5
IP31 Write low pulse width Twl Tdicdw – Tdicuw Tdicdw6 – Tdicdw – Tdicuw + 1.5 ns
– 1.5 Tdicuw7
IP32 Write high pulse width Twh Tdicpw – Tdicdw + Tdicpw – Tdicdw Tdicpw – Tdicdw + ns
Tdicuw – 1.5 + Tdicuw Tdicuw + 1.5
IP33 Controls setup time for read Tdcsr Tdicur – 1.5 Tdicur — ns
IP34 Controls hold time for read Tdchr Tdicpr – Tdicdr – 1.5 Tdicpr – Tdicdr — ns

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 Table 58. Asynchronous Parallel Interface Timing Parameters—Access Level (continued)

ID Parameter Symbol Min. Typ.1 Max. Units

IP35 Controls setup time for write Tdcsw Tdicuw – 1.5 Tdicuw — ns
IP36 Controls hold time for write Tdchw Tdicpw – Tdicdw – 1.5 Tdicpw – Tdicdw — ns
IP37 Slave device data delay8 Tracc 0 — Tdrp9 – Tlbd10 – Tdicur – ns
1.5
IP38 Slave device data hold time8 Troh Tdrp – Tlbd – Tdicdr — Tdicpr – Tdicdr – 1.5 ns
+ 1.5
IP39 Write data setup time Tds Tdicdw – 1.5 Tdicdw — ns
IP40 Write data hold time Tdh Tdicpw – Tdicdw – 1.5 Tdicpw – Tdicdw — ns
IP41 Read period2 Tdicpr Tdicpr – 1.5 Tdicpr Tdicpr + 1.5 ns
IP42 Write period3 Tdicpw Tdicpw – 1.5 Tdicpw Tdicpw + 1.5 ns
IP43 Read down time4 Tdicdr Tdicdr – 1.5 Tdicdr Tdicdr + 1.5 ns
5
IP44 Read up time Tdicur Tdicur – 1.5 Tdicur Tdicur + 1.5 ns
IP45 Write down time6 Tdicdw Tdicdw – 1.5 Tdicdw Tdicdw + 1.5 ns
IP46 Write up time7 Tdicuw Tdicuw – 1.5 Tdicuw Tdicuw + 1.5 ns
IP47 Read time point9 Tdrp Tdrp – 1.5 Tdrp Tdrp + 1.5 ns
1The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.
These conditions may be device-specific.
2 Display interface clock period value for read:

DISP#_IF_CLK_PER_RD
Tdicpr = T HSP_CLK ⋅ ceil ----------------------------------------------------------------
HSP_CLK_PERIOD

3
Display interface clock period value for write:
DISP#_IF_CLK_PER_WR
Tdicpw = T HSP_CLK ⋅ ceil ------------------------------------------------------------------
HSP_CLK_PERIOD

4 Display interface clock down time for read:

1 2 ⋅ DISP#_IF_CLK_DOWN_RD
Tdicdr = --- T HSP_CLK ⋅ ceil -------------------------------------------------------------------------------
2 HSP_CLK_PERIOD

5 Display interface clock up time for read:

1 2 ⋅ DISP#_IF_CLK_UP_RD
Tdicur = --- T HSP_CLK ⋅ ceil --------------------------------------------------------------------
2 HSP_CLK_PERIOD

6
Display interface clock down time for write:
1 2 ⋅ DISP#_IF_CLK_DOWN_WR
Tdicdw = --- T ⋅ ceil ---------------------------------------------------------------------------------
2 HSP_CLK HSP_CLK_PERIOD

7 Display interface clock up time for write:

1 2 ⋅ DISP#_IF_CLK_UP_WR
Tdicuw = --- T HSP_CLK ⋅ ceil ----------------------------------------------------------------------
2 HSP_CLK_PERIOD

8
This parameter is a requirement to the display connected to the IPU

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9
Data read point
DISP#_READ_EN
Tdrp = T ⋅ ceil --------------------------------------------------
HSP_CLK HSP_CLK_PERIOD

10
Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a
device – level output delay, board delays, a device – level input delay, an IPU input delay. This value is device specific.

The following parameters are programmed via the DI_DISP#_TIME_CONF_1,

DI_DISP#_TIME_CONF_2, and DI_HSP_CLK_PER registers:
• DISP#_IF_CLK_PER_WR, DISP#_IF_CLK_PER_RD
• HSP_CLK_PERIOD
• DISP#_IF_CLK_DOWN_WR
• DISP#_IF_CLK_UP_WR
• DISP#_IF_CLK_DOWN_RD
• DISP#_IF_CLK_UP_RD
• DISP#_READ_EN

4.9.13.5 Serial Interfaces, Functional Description

The IPU supports the following types of asynchronous serial interfaces:
• 3-wire (with bidirectional data line)
• 4-wire (with separate data input and output lines)
• 5-wire type 1 (with sampling RS by the serial clock)
• 5-wire type 2 (with sampling RS by the chip select signal)
Figure 62 depicts timing of the 3-wire serial interface. The timing images correspond to active-low
DISPB_D#_CS signal and the straight polarity of the DISPB_SD_D_CLK signal.
For this interface, a bidirectional data line is used outside the device. The IPU still uses separate input and
output data lines (IPP_IND_DISPB_SD_D and IPP_DO_DISPB_SD_D). The I/O mux connects the
internal data lines to the bidirectional external line according to the IPP_OBE_DISPB_SD_D signal
provided by the IPU.
Each data transfer can be preceded by an optional preamble with programmable length and contents. The
preamble is followed by read/write (RW) and address (RS) bits. The order of the these bits is
programmable. The RW bit can be disabled. The following data can consist of one word or of a whole
burst. The interface parameters are controlled by the DI_SER_DISPn_CONF registers (n = 1, 2).

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 1 display IF 1 display IF
DISPB_D#_CS
clock cycle clock cycle

DISPB_SD_D_CLK

DISPB_SD_D RW RS D7 D6 D5 D4 D3 D2 D1 D0

Preamble Input or output data

Figure 62. 3-Wire Serial Interface Timing Diagram

Figure 63 depicts timing of the 4-wire serial interface. For this interface, there are separate input and output
data lines both inside and outside the device.
Write

DISPB_D#_CS 1 display IF 1 display IF

clock cycle clock cycle

DISPB_SD_D_CLK
DISPB_SD_D
RW RS D7 D6 D5 D4 D3 D2 D1 D0
(Output)

Preamble Output data

DISPB_SD_D
(Input)

Read
DISPB_D#_CS 1 display IF 1 display IF
clock cycle clock cycle

DISPB_SD_D_CLK
DISPB_SD_D
(Output) RW RS

Preamble
DISPB_SD_D
(Input) D7 D6 D5 D4 D3 D2 D1 D0

Input data
Figure 63. 4-Wire Serial Interface Timing Diagram

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Figure 64 depicts timing of the 5-wire serial interface (Type 1). For this interface, a separate RS line is
added. When a burst is transmitted within a single active chip select interval, the RS can be changed at
boundaries of words.
Write
1 display IF 1 display IF
DISPB_D#_CS
clock cycle clock cycle

DISPB_SD_D_CLK
DISPB_SD_D
RW D7 D6 D5 D4 D3 D2 D1 D0
(Output)

Preamble Output data

DISPB_SD_D
(Input)

DISPB_SER_RS

Read
1 display IF 1 display IF
DISPB_D#_CS clock cycle
clock cycle

DISPB_SD_D_CLK
DISPB_SD_D
RW
(Output)

Preamble

DISPB_SD_D
D7 D6 D5 D4 D3 D2 D1 D0
(Input)

Input data
DISPB_SER_RS

Figure 64. 5-Wire Serial Interface (Type 1) Timing Diagram

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Figure 65 depicts timing of the 5-wire serial interface (Type 2). For this interface, a separate RS line is
added. When a burst is transmitted within a single active chip select interval, the RS can be changed at
boundaries of words.
Write
1 display IF 1 display IF
DISPB_D#_CS
clock cycle clock cycle

DISPB_SD_D_CLK
DISPB_SD_D
(Output) RW D7 D6 D5 D4 D3 D2 D1 D0

Preamble Output data

DISPB_SD_D
(Input)

1 display IF
DISPB_SER_RS
clock cycle

Read

DISPB_D#_CS 1 display IF 1 display IF

clock cycle clock cycle

DISPB_SD_D_CLK
DISPB_SD_D
RW
(Output)

Preamble
DISPB_SD_D
(Input) D7 D6 D5 D4 D3 D2 D1 D0

1 display IF Input data

DISPB_SER_RS
clock cycle

Figure 65. 5-Wire Serial Interface (Type 2) Timing Diagram

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4.9.13.5.10 Serial Interfaces, Electrical Characteristics
Figure 66 depicts timing of the serial interface. Table 59 lists the timing parameters at display access level.
IP49, IP48

DISPB_SER_RS

IP56,IP54 IP57, IP55

DISPB_SD_D_CLK

IP50, IP52 IP51, IP53

read point
IP58 IP59

DISPB_DATA Read Data

(Input)

IP60 IP61
DISPB_DATA
(Output)

IP67,IP65

IP47

IP64, IP66

IP62, IP63

Figure 66. Asynchronous Serial Interface Timing Diagram

Table 59. Asynchronous Serial Interface Timing Parameters—Access Level

ID Parameter Symbol Min. Typ.1 Max. Units

IP48 Read system cycle time Tcycr Tdicpr – 1.5 Tdicpr2 Tdicpr + 1.5 ns
IP49 Write system cycle time Tcycw Tdicpw – 1.5 Tdicpw3 Tdicpw + 1.5 ns
IP50 Read clock low pulse width Trl Tdicdr – Tdicur – 1.5 Tdicdr4 – Tdicur5 Tdicdr – Tdicur + 1.5 ns
IP51 Read clock high pulse width Trh Tdicpr – Tdicdr + Tdicur Tdicpr – Tdicdr + Tdicpr – Tdicdr + Tdicur ns
– 1.5 Tdicur + 1.5
IP52 Write clock low pulse width Twl Tdicdw – Tdicuw – 1.5 Tdicdw6 – Tdicdw – Tdicuw + 1.5 ns
Tdicuw7
IP53 Write clock high pulse width Twh Tdicpw – Tdicdw + Tdicpw – Tdicdw Tdicpw – Tdicdw + ns
Tdicuw – 1.5 + Tdicuw Tdicuw + 1.5
IP54 Controls setup time for read Tdcsr Tdicur – 1.5 Tdicur — ns

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 Table 59. Asynchronous Serial Interface Timing Parameters—Access Level (continued)

ID Parameter Symbol Min. Typ.1 Max. Units

IP55 Controls hold time for read Tdchr Tdicpr – Tdicdr – 1.5 Tdicpr – Tdicdr — ns
IP56 Controls setup time for write Tdcsw Tdicuw – 1.5 Tdicuw — ns
IP57 Controls hold time for write Tdchw Tdicpw – Tdicdw – 1.5 Tdicpw – Tdicdw — ns
IP58 Slave device data delay8 Tracc 0 — 9
Tdrp – Tlbd 10
– Tdicur ns
– 1.5
IP59 Slave device data hold time8 Troh Tdrp – Tlbd – Tdicdr — Tdicpr – Tdicdr – 1.5 ns
+ 1.5
IP60 Write data setup time Tds Tdicdw – 1.5 Tdicdw — ns
IP61 Write data hold time Tdh Tdicpw – Tdicdw – 1.5 Tdicpw – Tdicdw — ns
IP62 Read period2 Tdicpr Tdicpr – 1.5 Tdicpr Tdicpr + 1.5 ns
IP63 Write period3 Tdicpw Tdicpw – 1.5 Tdicpw Tdicpw + 1.5 ns
4
IP64 Read down time Tdicdr Tdicdr – 1.5 Tdicdr Tdicdr + 1.5 ns
IP65 Read up time5 Tdicur Tdicur – 1.5 Tdicur Tdicur + 1.5 ns
IP66 Write down time6 Tdicdw Tdicdw – 1.5 Tdicdw Tdicdw + 1.5 ns
IP67 Write up time7 Tdicuw Tdicuw – 1.5 Tdicuw Tdicuw + 1.5 ns
IP68 Read time point9 Tdrp Tdrp – 1.5 Tdrp Tdrp + 1.5 ns
1
The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.
These conditions may be device specific.
2
Display interface clock period value for read:
DISP#_IF_CLK_PER_RD
Tdicpr = T ⋅ ceil ----------------------------------------------------------------
HSP_CLK HSP_CLK_PERIOD

3
Display interface clock period value for write:
DISP#_IF_CLK_PER_WR
Tdicpw = T ⋅ ceil ------------------------------------------------------------------
HSP_CLK HSP_CLK_PERIOD

4 Display interface clock down time for read:

1 2 ⋅ DISP#_IF_CLK_DOWN_RD
Tdicdr = --- T HSP_CLK ⋅ ceil -------------------------------------------------------------------------------
2 HSP_CLK_PERIOD

5 Display interface clock up time for read:

1 2 ⋅ DISP#_IF_CLK_UP_RD
Tdicur = --- T ⋅ ceil --------------------------------------------------------------------
2 HSP_CLK HSP_CLK_PERIOD

6
Display interface clock down time for write:

1 2 ⋅ DISP#_IF_CLK_DOWN_WR
Tdicdw = --- T HSP_CLK ⋅ ceil ---------------------------------------------------------------------------------
2 HSP_CLK_PERIOD

7
Display interface clock up time for write:

1 2 ⋅ DISP#_IF_CLK_UP_WR
Tdicuw = --- T ⋅ ceil ----------------------------------------------------------------------
2 HSP_CLK HSP_CLK_PERIOD

8 This parameter is a requirement to the display connected to the IPU.

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9
Data read point:

DISP#_READ_EN
Tdrp = T ⋅ ceil --------------------------------------------------
HSP_CLK HSP_CLK_PERIOD
10
Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a
device-level output delay, board delays, a device-level input delay, and an IPU input delay. This value is device specific.

The following parameters are programmed via the DI_DISP#_TIME_CONF_1,

DI_DISP#_TIME_CONF_2, and DI_HSP_CLK_PER registers:
• DISP#_IF_CLK_PER_WR
• DISP#_IF_CLK_PER_RD
• HSP_CLK_PERIOD
• DISP#_IF_CLK_DOWN_WR
• DISP#_IF_CLK_UP_WR
• DISP#_IF_CLK_DOWN_RD
• DISP#_IF_CLK_UP_RD
• DISP#_READ_EN

4.9.14 Memory Stick Host Controller (MSHC)

Figure 67, Figure 68, and Figure 69 depict the MSHC timings, and Table 60 and Table 61 list the timing
parameters.
tSCLKc

tSCLKwh tSCLKwl

MSHC_SCLK

tSCLKr tSCLKf

Figure 67. MSHC_CLK Timing Diagram

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 tSCLKc

MSHC_SCLK

tBSsu tBSh

MSHC_BS

tDsu tDh

MSHC_DATA
(Output)

tDd

MSHC_DATA
(Intput)

Figure 68. Transfer Operation Timing Diagram (Serial)

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 tSCLKc

MSHC_SCLK

tBSsu tBSh

MSHC_BS

tDsu tDh

MSHC_DATA
(Output)

tDd

MSHC_DATA
(Input)

Figure 69. Transfer Operation Timing Diagram (Parallel)

NOTE
The memory stick host controller is designed to meet the timing
requirements per Sony's Memory Stick Pro Format Specifications. Tables in
this section detail the specifications’ requirements for parallel and serial
modes, and not the i.MX35 timing.
Table 60. Serial Interface Timing Parameters1

Standards
Signal Parameter Symbol Unit
Min. Max.

MSHC_SCLK Cycle tSCLKc 50 — ns

H pulse length tSCLKwh 15 — ns
L pulse length tSCLKwl 15 — ns
Rise time tSCLKr — 10 ns
Fall time tSCLKf — 10 ns
MSHC_BS Setup time tBSsu 5 — ns
Hold time tBSh 5 — ns

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 Table 60. Serial Interface Timing Parameters1 (continued)

Standards
Signal Parameter Symbol Unit
Min. Max.

MSHC_DATA Setup time tDsu 5 — ns

Hold time tDh 5 — ns
Output delay time tDd — 15 ns

1
Timing is guaranteed for NVCC from 2.7 V through 3.1 V and up to a maximum overdrive NVCC of 3.3 V. See NVCC
restrictions described in Table 61.

Table 61. Parallel Interface Timing Parameters1

Standards
Signal Parameter Symbol Unit
Min. Max.

MSHC_SCLK Cycle tSCLKc 25 — ns

H pulse length tSCLKwh 5 — ns
L pulse length tSCLKwl 5 — ns
Rise time tSCLKr — 10 ns
Fall time tSCLKf — 10 ns
MSHC_BS Setup time tBSsu 8 — ns
Hold time tBSh 1 — ns
MSHC_DATA Setup time tDsu 8 — ns
Hold time tDh 1 — ns
Output delay time tDd — 15 ns

1
Timing is guaranteed for NVCC from 2.7 V through 3.1 V and up to a maximum overdrive NVCC of 3.3 V. See the NVCC
restrictions described in Table 8.

4.9.15 MediaLB Controller Electrical Specifications

This section describes the electrical information of the MediaLB Controller module.
Table 62. MLB 256/512 Fs Timing Parameters

Parameter Symbol Min Typ Max Units Comment

MLBCLK operating frequency1 fmck 11.264 MHz Min: 256 × Fs at 44.0 kHz
12.288 Typ: 256 × Fs at 48.0 kHz
24.576 Typ: 512 × Fs at 48.0 kHz
24.6272
Max: 512 × Fs at 48.1 kHz
25.600
Max: 512 × Fs PLL unlocked
MLBCLK rise time tmckr — — 3 ns VIL TO VIH

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 Table 62. MLB 256/512 Fs Timing Parameters (continued)

Parameter Symbol Min Typ Max Units Comment

MLB fall time tmckf — — 3 ns VIH TO VIL

MLBCLK cycle time tmckc — 81 — ns 256 × Fs
— 40 — 512 × Fs
MLBCLK low time tmckl 31.5 37 — ns 256 × Fs
30 35.5 — 256 × Fs PLL unlocked
14.5 17 — ns 512 × Fs
14 16.5 — 512 × Fs PLL unlocked
MLBCLK high time tmckh 31.5 38 — ns 256 × Fs
30 36.5 — 256 × Fs PLL unlocked
14.5 17 — ns 512 × Fs
14 16.5 — 512 × Fs PLL unlocked
MLBCLK pulse width variation tmpwv — — 2 ns pp Note2
MLBSIG/MLBDAT input valid to tdsmcf 1 — — ns —
MLBCLK falling
MLBSIG/MLBDAT input hold tdhmcf 0 — — ns —
from MLBCLK low
MLBSIG/MLBDAT output high tmcfdz 0 — tmckl ns —
impedance from MLBCLK low
Bus Hold Time tmdzh 4 — — ns Note3
1
The MLB controller can shut off MLBCLK to place MediaLB in a low-power state.
2 Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other
edge, measured in ns peak-to-peak (pp)
3 The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this
time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.

Ground = 0.0 V; load capacitance = 40 pF; MediaLB speed = 1024 Fs; Fs = 48 kHz; all timing parameters
specified from the valid voltage threshold as listed below unless otherwise noted.
Table 63. MLB Device 1024Fs Timing Parameters

Parameter Symbol Min Typ Max Units Comment

MLBCLK Operating fmck 45.056 MHz Min: 1024 × Fs at 44.0 kHz

Frequency1 49.152 Typ: 1024 × Fs at 48.0 kHz
49.2544 Max: 1024 × Fs at 48.1 kHz
51.200 Max: 1024 × Fs PLL unlocked
MLBCLK rise time tmckr — — 1 ns VIL TO VIH
MLB fall time tmckf — — 1 ns VIH TO VIL
MLBCLK cycle time tmckc — 20.3 — ns —
MLBCLK low time tmckl 6.5 7.7 — ns PLL unlocked
6.1 7.3

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 Table 63. MLB Device 1024Fs Timing Parameters (continued)

Parameter Symbol Min Typ Max Units Comment

MLBCLK high time tmckh 9.7 10.6 — ns PLL unlocked

9.3 10.2 —
MLBCLK pulse width variation tmpwv — — 0.7 ns pp Note2
MLBSIG/MLBDAT input valid tdsmcf 1 — — ns —
to MLBCLK falling
MLBSIG/MLBDAT input hold tdhmcf 0 — — ns —
from MLBCLK low
MLBSIG/MLBDAT output high tmcfdz 0 — tmckl ns —
impedance from MLBCLK low
Bus Hold Time tmdzh 2 — — ns Note3
1
The MLB Controller can shut off MLBCLK to place MediaLB in a low-power state.
2
Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge,
measured in ns peak-to-peak (pp)
3
The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this
time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.

4.9.16 1-Wire Timing Specifications

Figure 70 depicts the RPP timing, and Table 64 lists the RPP timing parameters.

1-WIRE Tx DS2502 Tx
“Reset Pulse” “Presence Pulse”

1-Wire bus OW2

(BATT_LINE)

OW1 OW3
OW4
Figure 70. Reset and Presence Pulses (RPP) Timing Diagram

Table 64. RPP Sequence Delay Comparisons Timing Parameters

ID Parameters Symbol Min. Typ. Max. Units

OW1 Reset time low tRSTL 480 511 — µs

OW2 Presence detect high tPDH 15 — 60 µs
OW3 Presence detect low tPDL 60 — 240 µs
OW4 Reset time high tRSTH 480 512 — µs

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Figure 71 depicts write 0 sequence timing, and Table 65 lists the timing parameters.
OW6
1-Wire bus
(BATT_LINE)

OW5

Figure 71. Write 0 Sequence Timing Diagram

Table 65. WR0 Sequence Timing Parameters

ID Parameter Symbol Min. Typ. Max. Units

OW5 Write 0 low time tWR0_low 60 100 120 µs

OW6 Transmission time slot tSLOT OW5 117 120 µs

Figure 72 shows write 1 sequence timing, and Figure 73 depicts the read sequence timing. Table 66 lists
the timing parameters.
OW8
1-Wire bus
(BATT_LINE)

OW7
Figure 72. Write 1 Sequence Timing Diagram

OW8
1-Wire bus
(BATT_LINE)

OW7
OW9

Figure 73. Read Sequence Timing Diagram

Table 66. WR1/RD Timing Parameters

ID Parameter Symbol Min. Typ. Max. Units

OW7 Write 1/read low time tLOW1 1 5 15 µs

OW8 Transmission time slot tSLOT 60 117 120 µs
OW9 Release time tRELEASE 15 — 45 µs

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4.9.17 Parallel ATA Module AC Electrical Specifications
The parallel ATA module can work on PIO/multiword DMA/ultra-DMA transfer modes (not available for
the MCIMX351). Each transfer mode has a different data transfer rate, Ultra DMA mode 4 data transfer
rate is up to 100 MBps.
The parallel ATA module interface consists of a total of 29 pins. Some pins have different functions in
different transfer modes. There are various requirements for timing relationships among the function pins,
in compliance with the ATA/ATAPI-6 specification, and these requirements are configurable by the ATA
module registers.

4.9.17.1 General Timing Requirements

Table 67 and Figure 74 define the AC characteristics of the interface signals on all data transfer modes.
Table 67. AC Characteristics of All Interface Signals

ID Parameter Symbol Min. Max. Unit

SI1 Rising edge slew rate for any signal on the ATA interface1 Srise1 — 1.25 V/ns
SI2 Falling edge slew rate for any signal on the ATA interface1 Sfall1 — 1.25 V/ns
SI3 Host interface signal capacitance at the host connector Chost — 20 pF
1
SRISE and SFALL meet this requirement when measured at the sender’s connector from 10–90% of full signal amplitude with
all capacitive loads from 15 pF through 40 pF, where all signals have the same capacitive load value.

ATA Interface Signals

SI2 SI1

Figure 74. ATA Interface Signals Timing Diagram

4.9.17.2 ATA Electrical Specifications (ATA Bus, Bus Buffers)

This section discusses ATA parameters. For a detailed description, refer to the ATA-6 specification.
Level shifters are required for 3.3-V or 5.0-V compatibility on the ATA interface.
The use of bus buffers introduces delays on the bus and introduces skew between signal lines. These factors
make it difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. Use of bus
buffers is not recommended if fast UDMA mode is required.
The ATA specification imposes a slew rate limit on the ATA bus. According to this limit, any signal driven
on the bus should have a slew rate between 0.4 and 1.2 V/ns with a 40 pF load. Few vendors of bus buffers
specify the slew rate of the outgoing signals.
When bus buffers are used the ata_data bus buffer is bidirectional, and uses the direction control signal
ata_buffer_en. When ata_buffer_en is asserted, the bus should drive from host to device. When

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ata_buffer_en is negated, the bus drives from device to host. Steering of the signal is such that contention
on the host and device tri-state buses is always avoided.

4.9.17.3 Timing Parameters

Table 68 shows the parameters used in the timing equations. These parameters depend on the
implementation of the ATA interface on silicon, the bus buffer used, the cable delay, and the cable skew.
Table 68. ATA Timing Parameters

Value/
Name Description
Contributing Factor1

T Bus clock period (ipg_clk_ata) Peripheral clock

frequency
ti_ds Set-up time ata_data to ata_iordy edge (UDMA-in only)
UDMA0 15 ns
UDMA1 10 ns
UDMA2, UDMA3 7 ns
UDMA4 5 ns
UDMA5 4 ns

ti_dh Hold time ata_iordy edge to ata_data (UDMA-in only)

UDMA0, UDMA1, UDMA2, UDMA3, UDMA4 5.0 ns
UDMA5 4.6 ns

tco Propagation delay bus clock L-to-H to 12.0 ns

ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data,
ata_buffer_en
tsu Set-up time ata_data to bus clock L-to-H 8.5 ns
tsui Set-up time ata_iordy to bus clock H-to-L 8.5 ns
thi Hold time ata_iordy to bus clock H to L 2.5 ns
tskew1 Maximum difference in propagation delay bus clock L-to-H to any of following signals 7 ns
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data
(write), ata_buffer_en
tskew2 Maximum difference in buffer propagation delay for any of following signals Transceiver
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data
(write), ata_buffer_en
tskew3 Maximum difference in buffer propagation delay for any of following signals ata_iordy, Transceiver
ata_data (read)
tbuf Maximum buffer propagation delay Transceiver
tcable1 Cable propagation delay for ata_data Cable
tcable2 Cable propagation delay for control signals ata_dior, ata_diow, ata_iordy, ata_dmack Cable
tskew4 Maximum difference in cable propagation delay between ata_iordy and ata_data (read) Cable
tskew5 Maximum difference in cable propagation delay between (ata_dior, ata_diow, ata_dmack) Cable
and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write)
tskew6 Maximum difference in cable propagation delay without accounting for ground bounce Cable
1
Values provided where applicable.

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4.9.17.4 PIO Mode Timing
Figure 75 shows timing for PIO read, and Table 69 lists the timing parameters for PIO read.

Figure 75. PIO Read Timing Diagram

Table 69. PIO Read Timing Parameters

ATA Parameter from Controlling

Value
Parameter Figure 75 Variable

t1 t1 t1 (min.) = time_1 × T – (tskew1 + tskew2 + tskew5) time_1

t2 t2r t2 min.) = time_2r × T – (tskew1 + tskew2 + tskew5) time_2r
t9 t9 t9 (min.) = time_9 × T – (tskew1 + tskew2 + tskew6) time_3
t5 t5 t5 (min.) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 If not met, increase
time_2
t6 t6 0 —
tA tA tA (min.) = (1.5 + time_ax) × T – (tco + tsui + tcable2 + tcable2 + 2 × tbuf) time_ax
trd trd1 trd1 (max.) = (–trd) + (tskew3 + tskew4) time_pio_rdx
trd1 (min.) = (time_pio_rdx – 0.5) × T – (tsu + thi)
(time_pio_rdx – 0.5) × T > tsu + thi + tskew3 + tskew4
t0 — t0 (min.) = (time_1 + time_2 + time_9) × T time_1, time_2r, time_9

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Figure 76 shows timing for PIO write, and Table 70 lists the timing parameters for PIO write.

Figure 76. PIO Write Timing Diagram

Table 70. PIO Write Timing Parameters

Parameter
ATA Controlling
from Value
Parameter Variable
Figure 76

t1 t1 t1 (min.) = time_1 × T – (tskew1 + tskew2 + tskew5) time_1

t2 t2w t2 (min.) = time_2w × T – (tskew1 + tskew2 + tskew5) time_2w
t9 t9 t9 (min.) = time_9 × T – (tskew1 + tskew2 + tskew6) time_9
t3 — t3 (min.) = (time_2w – time_on) × T – (tskew1 + tskew2 +tskew5) If not met, increase
time_2w
t4 t4 t4 (min.) = time_4 × T – tskew1 time_4
tA tA tA = (1.5 + time_ax) × T – (tco + tsui + tcable2 + tcable2 + 2*tbuf) time_ax
t0 — t0(min.) = (time_1 + time_2 + time_9) × T time_1, time_2r,
time_9
— — Avoid bus contention when switching buffer on by making ton long enough. —
— — Avoid bus contention when switching buffer off by making toff long enough. —

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Figure 77 shows timing for MDMA read, and Figure 78 shows timing for MDMA write. Table 71 lists the
timing parameters for MDMA read and write.

Figure 77. MDMA Read Timing Diagram

Figure 78. MDMA Write Timing Diagram

Table 71. MDMA Read and Write Timing Parameters

Parameter
ATA from Controlling
Value
Parameter Figure 77, Variable
Figure 78

tm, ti tm tm (min.) = ti (min.) = time_m × T – (tskew1 + tskew2 + tskew5) time_m

td td, td1 td1.(min.) = td (min.) = time_d × T – (tskew1 + tskew2 + tskew6) time_d
tk tk tk.(min.) = time_k × T – (tskew1 + tskew2 + tskew6) time_k
t0 — t0 (min.) = (time_d + time_k) × T time_d, time_k
tg(read) tgr tgr (min. – read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 time_d
tgr.(min. – drive) = td – te(drive)
tf(read) tfr tfr (min. – drive) = 0 —
tg(write) — tg (min. – write) = time_d × T – (tskew1 + tskew2 + tskew5) time_d
tf(write) — tf (min. – write) = time_k × T – (tskew1 + tskew2 + tskew6) time_k
tL — tL (max.) = (time_d + time_k–2) × T – (tsu + tco + 2 × tbuf + 2 × tcable2) time_d, time_k

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 Table 71. MDMA Read and Write Timing Parameters (continued)

Parameter
ATA from Controlling
Value
Parameter Figure 77, Variable
Figure 78

tn, tj tkjn tn = tj = tkjn = (max.(time_k,. time_jn) × T – (tskew1 + tskew2 + tskew6) time_jn

— ton ton = time_on × T – tskew1 —
toff toff = time_off × T – tskew1

4.9.17.5 UDMA-In Timing

Figure 79 shows timing when the UDMA-in transfer starts, Figure 80 shows timing when the UDMA-in
host terminates transfer, Figure 81 shows timing when the UDMA-in device terminates transfer, and
Table 72 lists the timing parameters for the UDMA-in burst.

Figure 79. UDMA-In Transfer Starts Timing Diagram

Figure 80. UDMA-In Host Terminates Transfer Timing Diagram

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Freescale Semiconductor 105
 Figure 81. UDMA-In Device Terminates Transfer Timing Diagram

Table 72. UDMA-In Burst Timing Parameters

Parameters
from
ATA
Figure 79, Description Controlling Variable
Parameter
Figure 80,
Figure 81

tack tack tack (min.) = (time_ack × T) – (tskew1 + tskew2) time_ack

tenv tenv tenv (min.) = (time_env × T) – (tskew1 + tskew2) time_env
tenv (max.) = (time_env × T) + (tskew1 + tskew2)
tds tds1 tds – (tskew3) – ti_ds > 0 tskew3, ti_ds, ti_dh
should be low enough
tdh tdh1 tdh – (tskew3) – ti_dh > 0
tcyc tc1 (tcyc – tskew > T T big enough
trp trp trp (min.) = time_rp × T – (tskew1 + tskew2 + tskew6) time_rp
— tx1 1 (time_rp × T) – (tco + tsu + 3T + 2 × tbuf + 2 × tcable2) > trfs (drive) time_rp
tmli tmli1 tmli1 (min.) = (time_mlix + 0.4) × T time_mlix
tzah tzah tzah (min.) = (time_zah + 0.4) × T time_zah
tdzfs tdzfs tdzfs = (time_dzfs × T) – (tskew1 + tskew2) time_dzfs
tcvh tcvh tcvh = (time_cvh × T) – (tskew1 + tskew2) time_cvh
— ton ton = time_on × T – tskew1 —
toff toff = time_off × T – tskew1

1
There is a special timing requirement in the ATA host that requires the internal DIOW to go high three clocks after the last active
edge on the DSTROBE signal. The equation given on this line tries to capture this constraint.
2. Make ton and toff large enough to avoid bus contention.

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4.9.17.6 UDMA-Out Timing
Figure 82 shows timing when the UDMA-out transfer starts, Figure 83 shows timing when the UDMA-out
host terminates transfer, Figure 84 shows timing when the UDMA-out device terminates transfer, and
Table 73 lists the timing parameters for the UDMA-out burst.

Figure 82. UDMA-Out Transfer Starts Timing Diagram

Figure 83. UDMA-Out Host Terminates Transfer Timing Diagram

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 Figure 84. UDMA-Out Device Terminates Transfer Timing Diagram

Table 73. UDMA-Out Burst Timing Parameters

Parameter
from
ATA Controlling
Figure 82, Value
Parameter Variable
Figure 83,
Figure 84

tack tack tack (min.) = (time_ack × T) – (tskew1 + tskew2) time_ack

tenv tenv tenv (min.) = (time_env × T) – (tskew1 + tskew2) time_env
tenv (max.) = (time_env × T) + (tskew1 + tskew2)
tdvs tdvs tdvs = (time_dvs ×T) – (tskew1 + tskew2) time_dvs
tdvh tdvh tdvs = (time_dvh × T) – (tskew1 + tskew2) time_dvh
tcyc tcyc tcyc = time_cyc × T – (tskew1 + tskew2) time_cyc
t2cyc — t2cyc = time_cyc × 2 × T time_cyc
trfs1 trfs trfs = 1.6 × T + tsui + tco + tbuf + tbuf —
— tdzfs tdzfs = time_dzfs × T – (tskew1) time_dzfs
tss tss tss = time_ss × T – (tskew1 + tskew2) time_ss
tmli tdzfs_mli tdzfs_mli = max. (time_dzfs, time_mli) × T – (tskew1 + tskew2) —
tli tli1 tli1 > 0 —
tli tli2 tli2 > 0 —
tli tli3 tli3 > 0 —
tcvh tcvh tcvh = (time_cvh × T) – (tskew1 + tskew2) time_cvh
— ton ton = time_on × T – tskew1 —
toff toff = time_off × T – tskew1

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4.9.18 Parallel Interface (ULPI) Timing
Electrical and timing specifications of the parallel interface are presented in the subsequent sections.
Table 74. Signal Definitions—Parallel Interface

Name Direction Signal Description

USB_Clk In Interface clock. All interface signals are synchronous to the clock.

USB_Data[7:0] I/O Bidirectional data bus, driven low by the link during idle. Bus ownership is determined by Dir.

USB_Dir In Direction. Control the direction of the data bus.

USB_Stp Out Stop. The link asserts this signal for 1 clock cycle to stop the data stream currently on the bus.

USB_Nxt In Next. The PHY asserts this signal to throttle the data.

USB_Clk

US15 US16
USB_Stp

US15 US16

USB_Data
US17 US17

USB_Dir/Nxt

Figure 85. USB Transmit/Receive Waveform in Parallel Mode

Table 75. USB Timing Specification in VP_VM Unidirectional Mode

Conditions /
ID Parameter Min. Max. Unit
Reference Signal

US15 USB_TXOE_B — 6.0 ns 10 pF

US16 USB_DAT_VP — 0.0 ns 10 pF

US17 USB_SE0_VM — 9.0 ns 10 pF

4.9.19 PWM Electrical Specifications

This section describes the electrical information of the PWM. The PWM can be programmed to select one
of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before
being input to the counter. The output is available at the pulse-width modulator output (PWMO) external

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Freescale Semiconductor 109
pin. The modulated signal of the module is observed at this pin. It can be viewed as a clock signal whose
period and duty cycle can be varied with different settings of the PWM. The smallest period is two ipg_clk
periods with duty cycle of 50 percent.

4.9.20 SJC Electrical Specifications

This section details the electrical characteristics for the SJC module. Figure 86 depicts the SJC test clock
input timing. Figure 87 depicts the SJC boundary scan timing, Figure 88 depicts the SJC test access port,
Figure 89 depicts the SJC TRST timing, and Table 76 lists the SJC timing parameters.

SJ1
SJ2 SJ2
TCK
(Input) VIH VM VM
VIL
SJ3 SJ3

Figure 86. Test Clock Input Timing Diagram

TCK
(Input) VIH
VIL

SJ4 SJ5

Data
Inputs Input Data Valid

SJ6

Data
Output Data Valid
Outputs

SJ7

Data
Outputs

SJ6

Data
Outputs Output Data Valid

Figure 87. Boundary Scan (JTAG) Timing Diagram

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 TCK
(Input) VIH
VIL
SJ8 SJ9
TDI
TMS Input Data Valid
(Input)
SJ10

TDO
(Output) Output Data Valid

SJ11

TDO
(Output)

SJ10

TDO
(Output) Output Data Valid

Figure 88. Test Access Port Timing Diagram

TCK
(Input)
SJ13
TRST
(Input)

SJ12
Figure 89. TRST Timing Diagram

Table 76. SJC Timing Parameters

All Frequencies
ID Parameter Unit
Min. Max.

SJ1 TCK cycle time 1001 — ns

SJ2 TCK clock pulse width measured at VM2 40 — ns
SJ3 TCK rise and fall times — 3 ns
SJ4 Boundary scan input data set-up time 10 — ns
SJ5 Boundary scan input data hold time 50 — ns
SJ6 TCK low to output data valid — 50 ns
SJ7 TCK low to output high impedance — 50 ns
SJ8 TMS, TDI data set-up time 10 — ns
SJ9 TMS, TDI data hold time 50 — ns
SJ10 TCK low to TDO data valid — 44 ns

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 Table 76. SJC Timing Parameters (continued)

All Frequencies
ID Parameter Unit
Min. Max.

SJ11 TCK low to TDO high impedance — 44 ns

SJ12 TRST assert time 100 — ns
SJ13 TRST set-up time to TCK low 40 — ns

1
On cases where SDMA TAP is put in the chain, the max. TCK frequency is limited by max. ratio of 1:8 of SDMA core frequency
to TCK limitation. This implies max. frequency of 8.25 MHz (or 121.2 ns) for 66 MHz IPG clock.
2
VM = mid point voltage

4.9.21 SPDIF Timing

SPDIF data is sent using bi-phase marking code. When encoding, the SPDIF data signal is modulated by
a clock that is twice the bit rate of the data signal.
Figure 90 shows SPDIF timing parameters, including the timing of the modulating Rx clock (SRCK) for
SPDIF in Rx mode and the timing of the modulating Tx clock (STCLK). for SPDIF in Tx mode.
Table 77. SPDIF Timing Parameters

Timing Parameter Range

Parameters Symbol Units
Min. Max.

SPDIFIN Skew: asynchronous inputs, no specs apply — — 0.7 ns

SPDIFOUT output (Load = 50 pf)
• Skew — — 1.5 ns
• Transition rising — — 24.2
• Transition falling — — 31.3

SPDIFOUT1 output (Load = 30 pf)

• Skew — — 1.5 ns
• Transition rising — — 13.6
• Transition falling — — 18.0

Modulating Rx clock (SRCK) period srckp 40.0 — ns

SRCK high period srckph 16.0 — ns
SRCK low period srckpl 16.0 — ns
Modulating Tx clock (STCLK) period stclkp 40.0 — ns
STCLK high period stclkph 16.0 — ns
STCLK low period stclkpl 16.0 — ns

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 srckp

srckpl srckph
VM VM
SRCK
(Output)

Figure 90. SRCK Timing

stclkp

stclkpl stclkph
VM VM
STCLK
(Input)

Figure 91. STCLK Timing

4.9.22 SSI Electrical Specifications

This section describes electrical characteristics of the SSI.
NOTE
• All of the timing for the SSI is given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables
and in the figures.
• All timing is on AUDMUX signals when SSI is being used for data
transfer.
• “Tx” and “Rx” refer to the transmit and receive sections of the SSI,
respectively.
• For internal frame sync operations using the external clock, the FS
timing will be the same as that of Tx Data (for example, during AC97
mode of operation).

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4.9.22.1 SSI Transmitter Timing with Internal Clock
Figure 92 depicts the SSI transmitter timing with internal clock, and Table 78 lists the timing parameters.

SS1
SS5 SS3
SS2 SS4

AD1_TXC
(Output)
SS6 SS8

AD1_TXFS (bl)
(Output)
SS10 SS12

AD1_TXFS (wl) SS14

(Output) SS15
SS16 SS17 SS18
AD1_TXD
(Output)
SS43
SS19
SS42
AD1_RXD
(Input)

Note: SRXD Input in Synchronous mode only

SS1
SS5 SS3

SS2 SS4

DAM1_T_CLK
(Output)
SS6 SS8

DAM1_T_FS (bl)
(Output)
SS10 SS12

DAM1_T_FS (wl) SS14

(Output) SS15
SS16 SS17 SS18

DAM1_TXD
(Output)
SS43
SS42 SS19
DAM1_RXD
(Input)

Note: SRXD Input in Synchronous mode only

Figure 92. SSI Transmitter with Internal Clock Timing Diagram

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 Table 78. SSI Transmitter with Internal Clock Timing Parameters

ID Parameter Min. Max. Unit

Internal Clock Operation

SS1 (Tx/Rx) CK clock period 81.4 — ns

SS2 (Tx/Rx) CK clock high period 36.0 — ns

SS3 (Tx/Rx) CK clock rise time — 6 ns
SS4 (Tx/Rx) CK clock low period 36.0 — ns
SS5 (Tx/Rx) CK clock fall time — 6 ns
SS6 (Tx) CK high to FS (bl) high — 15.0 ns
SS8 (Tx) CK high to FS (bl) low — 15.0 ns
SS10 (Tx) CK high to FS (wl) high — 15.0 ns
SS12 (Tx) CK high to FS (wl) low — 15.0 ns
SS14 (Tx/Rx) Internal FS rise time — 6 ns
SS15 (Tx/Rx) Internal FS fall time — 6 ns
SS16 (Tx) CK high to STXD valid from high impedance — 15.0 ns
SS17 (Tx) CK high to STXD high/low — 15.0 ns
SS18 (Tx) CK high to STXD high impedance — 15.0 ns
SS19 STXD rise/fall time — 6 ns

Synchronous Internal Clock Operation

SS42 SRXD setup before (Tx) CK falling 10.0 — ns

SS43 SRXD hold after (Tx) CK falling 0 — ns
SS52 Loading — 25 pF

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4.9.22.2 SSI Receiver Timing with Internal Clock
Figure 93 depicts the SSI receiver timing with internal clock. Table 79 lists the timing parameters shown
in Figure 93.
SS1
SS5 SS3
SS2 SS4

AD1_TXC
(Output)
SS7 SS9
AD1_TXFS (bl)
(Output)
SS11 SS13
AD1_TXFS (wl)
(Output)
SS20
SS21
AD1_RXD
(Input)
SS47 SS51
SS49
SS48 SS50

AD1_RXC
(Output)

SS1
SS5 SS3

SS2 SS4

DAM1_T_CLK
(Output)
SS7 SS9

DAM1_T_FS (bl)
(Output) SS11 SS13
DAM1_T_FS (wl)
(Output)
SS20
SS21
DAM1_RXD
(Input)

SS47
SS51
SS49
SS48 SS50

DAM1_R_CLK
(Output)

Figure 93. SSI Receiver with Internal Clock Timing Diagram

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 Table 79. SSI Receiver with Internal Clock Timing Parameters

ID Parameter Min. Max. Unit

Internal Clock Operation

SS1 (Tx/Rx) CK clock period 81.4 — ns

SS2 (Tx/Rx) CK clock high period 36.0 — ns

SS3 (Tx/Rx) CK clock rise time — 6 ns
SS4 (Tx/Rx) CK clock low period 36.0 — ns
SS5 (Tx/Rx) CK clock fall time — 6 ns
SS7 (Rx) CK high to FS (bl) high — 15.0 ns
SS9 (Rx) CK high to FS (bl) low — 15.0 ns
SS11 (Rx) CK high to FS (wl) high — 15.0 ns
SS13 (Rx) CK high to FS (wl) low — 15.0 ns
SS20 SRXD setup time before (Rx) CK low 10.0 — ns
SS21 SRXD hold time after (Rx) CK low 0 — ns

Oversampling Clock Operation

SS47 Oversampling clock period 15.04 — ns

SS48 Oversampling clock high period 6 — ns
SS49 Oversampling clock rise time — 3 ns
SS50 Oversampling clock low period 6 — ns
SS51 Oversampling clock fall time — 3 ns

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4.9.22.3 SSI Transmitter Timing with External Clock
Figure 94 depicts the SSI transmitter timing with external clock, and Table 80 lists the timing parameters.
SS22
SS23 SS25
SS26 SS24

AD1_TXC
(Input)
SS27 SS29
AD1_TXFS (bl)
(Input)
SS31 SS33
AD1_TXFS (wl)
(Input)
SS39
SS37 SS38
AD1_TXD
(Output)
SS45
SS44
AD1_RXD
(Input)

Note: SRXD Input in Synchronous mode only SS46

SS22
SS26 SS24
SS23 SS25

DAM1_T_CLK
(Input)
SS27 SS29
DAM1_T_FS (bl)
(Input)
SS31 SS33
DAM1_T_FS (wl)
(Input)
SS39
SS37 SS38
DAM1_TXD
(Output)
SS45
SS44
DAM1_RXD
(Input)

Note: SRXD Input in Synchronous mode only SS46

Figure 94. SSI Transmitter with External Clock Timing Diagram

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 Table 80. SSI Transmitter with External Clock Timing Parameters

ID Parameter Min. Max. Unit

External Clock Operation

SS22 (Tx/Rx) CK clock period 81.4 — ns

SS23 (Tx/Rx) CK clock high period 36.0 — ns

SS24 (Tx/Rx) CK clock rise time — 6.0 ns
SS25 (Tx/Rx) CK clock low period 36.0 — ns
SS26 (Tx/Rx) CK clock fall time — 6.0 ns
SS27 (Tx) CK high to FS (bl) high –10.0 15.0 ns
SS29 (Tx) CK high to FS (bl) low 10.0 — ns
SS31 (Tx) CK high to FS (wl) high –10.0 15.0 ns
SS33 (Tx) CK high to FS (wl) low 10.0 — ns
SS37 (Tx) CK high to STXD valid from high impedance — 15.0 ns
SS38 (Tx) CK high to STXD high/low — 15.0 ns
SS39 (Tx) CK high to STXD high impedance — 15.0 ns

Synchronous External Clock Operation

SS44 SRXD setup before (Tx) CK falling 10.0 — ns

SS45 SRXD hold after (Tx) CK falling 2.0 — ns
SS46 SRXD rise/fall time — 6.0 ns

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4.9.22.4 SSI Receiver Timing with External Clock
Figure 95 depicts the SSI receiver timing with external clock, and Table 81 lists the timing parameters.
SS22
SS26 SS24
SS23 SS25

AD1_TXC
(Input)
SS28 SS30
AD1_TXFS (bl)
(Input)
SS32 SS34
AD1_TXFS (wl) SS35
(Input) SS41
SS36
SS40
AD1_RXD
(Input)

SS22
SS26 SS24
SS23 SS25

DAM1_T_CLK
(Input)
SS28 SS30

DAM1_T_FS (bl)
(Input)
SS32 SS34
DAM1_T_FS (wl) SS35
(Input)
SS41 SS36
SS40
DAM1_RXD
(Input)

Figure 95. SSI Receiver with External Clock Timing Diagram

Table 81. SSI Receiver with External Clock Timing Parameters

ID Parameter Min. Max. Unit

External Clock Operation

SS22 (Tx/Rx) CK clock period 81.4 — ns

SS23 (Tx/Rx) CK clock high period 36.0 — ns
SS24 (Tx/Rx) CK clock rise time — 6.0 ns

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 Table 81. SSI Receiver with External Clock Timing Parameters (continued)

ID Parameter Min. Max. Unit

SS25 (Tx/Rx) CK clock low period 36.0 — ns

SS26 (Tx/Rx) CK clock fall time — 6.0 ns

SS28 (Rx) CK high to FS (bl) high –10.0 15.0 ns

SS30 (Rx) CK high to FS (bl) low 10.0 — ns
SS32 (Rx) CK high to FS (wl) high –10.0 15.0 ns
SS34 (Rx) CK high to FS (wl) low 10.0 — ns
SS35 (Tx/Rx) External FS rise time — 6.0 ns
SS36 (Tx/Rx) External FS fall time — 6.0 ns
SS40 SRXD setup time before (Rx) CK low 10.0 — ns
SS41 SRXD hold time after (Rx) CK low 2.0 — ns

4.9.23 UART Electrical

This section describes the electrical information of the UART module.

4.9.23.1 UART RS-232 Serial Mode Timing

The following subsections give the UART transmit and receive timings in RS-232 serial mode.

4.9.23.1.11 UART Transmitter

Figure 96 depicts the transmit timing of UART in RS-232 serial mode, with 8 data bit/1 stop bit format.
Table 82 lists the UART RS-232 serial mode transmit timing characteristics.
Possible
UA1 UA1 Parity
Bit
Next
Start Start
TXD
Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Par Bit STOP Bit
(output) BIT

UA1 UA1
Figure 96. UART RS-232 Serial Mode Transmit Timing Diagram

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 Table 82. RS-232 Serial Mode Transmit Timing Parameters

ID Parameter Symbol Min. Max. Units

UA1 Transmit Bit Time tTbit 1/Fbaud_rate1 – 1/Fbaud_rate + —

Tref_clk2 Tref_clk
1
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
2
Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).

4.9.23.1.12 UART Receiver

Figure 97 depicts the RS-232 serial mode receive timing, with 8 data bit/1 stop bit format. Table 83 lists
serial mode receive timing characteristics.
Possible
UA2 UA2 Parity
Bit
Next
RXD Start Start
Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Par Bit STOP Bit
(input)
BIT

UA2 UA2
Figure 97. UART RS-232 Serial Mode Receive Timing Diagram

Table 83. RS-232 Serial Mode Receive Timing Parameters

ID Parameter Symbol Min. Max. Units

UA2 Receive Bit Time1 tRbit 1/Fbaud_rate2 – 1/Fbaud_rate + —

1/(16 × Fbaud_rate) 1/(16 × Fbaud_rate)
1
The UART receiver can tolerate 1/(16 × Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not
exceed 3/(16 × Fbaud_rate).
2
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency) ÷ 16.

4.9.23.2 UART IrDA Mode Timing

The following subsections give the UART transmit and receive timings in IrDA mode.

4.9.23.2.13 UART IrDA Mode Transmitter

Figure 98 depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. Table 84 lists
the transmit timing characteristics.

UA3 UA3 UA4

UA3 UA3

TXD
(output)

Start Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Possible STOP
Bit Parity BIT
Bit
Figure 98. UART IrDA Mode Transmit Timing Diagram

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 Table 84. IrDA Mode Transmit Timing Parameters

ID Parameter Symbol Min. Max. Units

UA3 Transmit bit time in IrDA mode tTIRbit 1/Fbaud_rate1 – 1/Fbaud_rate + Tref_clk —
Tref_clk2
UA4 Transmit IR pulse duration tTIRpulse (3/16) × (1/Fbaud_rate) (3/16) × (1/Fbaud_rate) —
– Tref_clk + Tref_clk
1
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
2
Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).

4.9.23.2.14 UART IrDA Mode Receiver

Figure 99 depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format. Table 85 lists the
receive timing characteristics.
UA5 UA5 UA6
UA5 UA5

RXD
(input)

Start Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Possible STOP
Bit Parity BIT
Bit
Figure 99. UART IrDA Mode Receive Timing Diagram

Table 85. IrDA Mode Receive Timing Parameters

ID Parameter Symbol Min. Max. Units

UA5 Receive bit time1 in IrDA mode tRIRbit 1/Fbaud_rate2 – 1/Fbaud_rate + —

1/(16 × Fbaud_rate) 1/(16 × Fbaud_rate )
UA6 Receive IR pulse duration tRIRpulse 1.41 us (5/16) × (1/Fbaud_rate) —
1
The UART receiver can tolerate 1/(16 × Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not
exceed 3/(16 × Fbaud_rate).
2
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency) ÷ 16.

4.9.24 USB Electrical Specifications

In order to support four different serial interfaces, the USB serial transceiver can be configured to operate
in one of four modes:
• DAT_SE0 bidirectional, 3-wire mode
• DAT_SE0 unidirectional, 6-wire mode
• VP_VM bidirectional, 4-wire mode
• VP_VM unidirectional, 6-wire mode

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4.9.24.1 DAT_SE0 Bidirectional Mode
Table 86 defines the signals for DAT_SE0 bidirectional mode. Figure 100 and Figure 101 show the
transmit and receive waveforms respectively.
Table 86. Signal Definitions—DAT_SE0 Bidirectional Mode

Name Direction Signal Description

USB_TXOE_B Out Transmit enable, active low

Out Tx data when USB_TXOE_B is low

USB_DAT_VP In Differential Rx data when USB_TXOE_B is high

Out SE0 drive when USB_TXOE_B is low

USB_SE0_VM In SE0 Rx indicator when USB_TXOE_B is high

Transmit
US3
USB_TXOE_B

USB_DAT_VP

US1
USB_SE0_VM

US4 US2

Figure 100. USB Transmit Waveform in DAT_SE0 Bidirectional Mode

Receive

USB_TXOE_B

USB_DAT_VP

US7 US8

USB_SE0_VM

Figure 101. USB Receive Waveform in DAT_SE0 Bidirectional Mode

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Table 87 describes the port timing specification in DAT_SE0 bidirectional mode.
Table 87. Port Timing Specification in DAT_SE0 Bidirectional Mode

No. Parameter Signal Name Direction Min. Max. Unit Conditions/Reference Signal

US1 Tx rise/fall time USB_DAT_VP Out — 5.0 ns 50 pF

US2 Tx rise/fall time USB_SE0_VM Out — 5.0 ns 50 pF
US3 Tx rise/fall time USB_TXOE_B Out — 5.0 ns 50 pF
US4 Tx duty cycle USB_DAT_VP Out 49.0 51.0 % —
US7 Rx rise/fall time USB_DAT_VP In — 3.0 ns 35 pF
US8 Rx rise/fall time USB_SE0_VM In — 3.0 ns 35 pF

4.9.24.2 DAT_SE0 Unidirectional Mode

Table 88 defines the signals for DAT_SE0 unidirectional mode. Figure 102 and Figure 103 show the
transmit and receive waveforms respectively.
Table 88. Signal Definitions—DAT_SE0 Unidirectional Mode

Name Direction Signal Description

USB_TXOE_B Out Transmit enable, active low

USB_DAT_VP Out Tx data when USB_TXOE_B is low
USB_SE0_VM Out SE0 drive when USB_TXOE_B is low
USB_VP1 In Buffered data on DP when USB_TXOE_B is high
USB_VM1 In Buffered data on DM when USB_TXOE_B is high
USB_RCV In Differential Rx data when USB_TXOE_B is high

Transmit

US11

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM US9

US12 US10

Figure 102. USB Transmit Waveform in DAT_SE0 Unidirectional Mode

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 Receive

USB_TXOE_B

USB_VP1
USB_RCV

US15/US17 US16

USB_VM1

Figure 103. USB Receive Waveform in DAT_SE0 Unidirectional Mode

Table 89 describes the port timing specification in DAT_SE0 unidirectional mode.

Table 89. USB Port Timing Specification in DAT_SE0 Unidirectional Mode

Signal Condition/
No. Parameter Signal Name Min. Max. Unit
Source Reference Signal

US9 Tx rise/fall time USB_DAT_VP Out — 5.0 ns 50 pF

US10 Tx rise/fall time USB_SE0_VM Out — 5.0 ns 50 pF
US11 Tx rise/fall time USB_TXOE_B Out — 5.0 ns 50 pF
US12 Tx duty cycle USB_DAT_VP Out 49.0 51.0 % —
US15 Rx rise/fall time USB_VP1 In — 3.0 ns 35 pF
US16 Rx rise/fall time USB_VM1 In — 3.0 ns 35 pF
US17 Rx rise/fall time USB_RCV In — 3.0 ns 35 pF

4.9.24.3 VP_VM Bidirectional Mode

Table 90 defines the signals for VP_VM bidirectional mode. Figure 104 and Figure 105 show the transmit
and receive waveforms respectively.
Table 90. Signal Definitions—VP_VM Bidirectional Mode

Name Direction Signal Description

USB_TXOE_B Out Transmit enable, active low

USB_DAT_VP Out (Tx) Tx VP data when USB_TXOE_B is low
In (Rx) Rx VP data when USB_TXOE_B is high
USB_SE0_VM Out (Tx) Tx VM data when USB_TXOE_B low
In (Rx) Rx VM data when USB_TXOE_B high
USB_RCV In Differential Rx data

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 Transmit
US20
USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

US18

US21 US19

US22 US22

Figure 104. USB Transmit Waveform in VP_VM Bidirectional Mode

Receive US26

USB_DAT_VP

USB_SE0_VM US28 US27

USB_RCV
US29

Figure 105. USB Receive Waveform in VP_VM Bidirectional Mode

Table 91 describes the port timing specification in VP_VM bidirectional mode.

Table 91. USB Port Timing Specification in VP_VM Bidirectional Mode

Condition/
No. Parameter Signal Name Direction Min. Max. Unit
Reference Signal

US18 Tx rise/fall time USB_DAT_VP Out — 5.0 ns 50 pF

US19 Tx rise/fall time USB_SE0_VM Out — 5.0 ns 50 pF
US20 Tx rise/fall time USB_TXOE_B Out — 5.0 ns 50 pF
US21 Tx duty cycle USB_DAT_VP Out 49.0 51.0 % —
US22 Tx overlap USB_SE0_VM Out –3.0 +3.0 ns USB_DAT_VP
US26 Rx rise/fall time USB_DAT_VP In — 3.0 ns 35 pF
US27 Rx rise/fall time USB_SE0_VM In — 3.0 ns 35 pF

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 Table 91. USB Port Timing Specification in VP_VM Bidirectional Mode (continued)

Condition/
No. Parameter Signal Name Direction Min. Max. Unit
Reference Signal

US28 Rx skew USB_DAT_VP In –4.0 +4.0 ns USB_SE0_VM

US29 Rx skew USB_RCV In –6.0 +2.0 ns USB_DAT_VP

4.9.24.4 VP_VM Unidirectional Mode

Table 92 defines the signals for VP_VM unidirectional mode. Figure 106 and Figure 107 show the
transmit and receive waveforms respectively.
Table 92. Signal Definitions—VP_VM Unidirectional Mode

Name Direction Signal Description

USB_TXOE_B Out Transmit enable, active low

USB_DAT_VP Out Tx VP data when USB_TXOE_B is low
USB_SE0_VM Out Tx VM data when USB_TXOE_B is low
USB_VP1 In Rx VP data when USB_TXOE_B is high
USB_VM1 In Rx VM data when USB_TXOE_B is high
USB_RCV In Differential Rx data

Transmit
US32
USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

US30

US33 US31

US34 US34

Figure 106. USB Transmit Waveform in VP_VM Unidirectional Mode

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128 Freescale Semiconductor
 Receive

USB_TXOE_B

USB_VP1

US38

USB_VM1

US40

US39
USB_RCV

US41

Figure 107. USB Receive Waveform in VP_VM Unidirectional Mode

Table 93 describes the port timing specification in VP_VM unidirectional mode.

Table 93. USB Timing Specification in VP_VM Unidirectional Mode

No. Parameter Signal Direction Min. Max. Unit Conditions/Reference Signal

US30 Tx rise/fall time USB_DAT_VP Out — 5.0 ns 50 pF

US31 Tx rise/fall time USB_SE0_VM Out — 5.0 ns 50 pF

US32 Tx rise/fall time USB_TXOE_B Out — 5.0 ns 50 pF

US33 Tx duty cycle USB_DAT_VP Out 49.0 51.0 % —

US34 Tx overlap USB_SE0_VM Out –3.0 +3.0 ns USB_DAT_VP

US38 Rx rise/fall time USB_VP1 In — 3.0 ns 35 pF

US39 Rx rise/fall time USB_VM1 In — 3.0 ns 35 pF

US40 Rx skew USB_VP1 In –4.0 +4.0 ns USB_VM1

US41 Rx skew USB_RCV In –6.0 +2.0 ns USB_VP1

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5 Package Information and Pinout
This section includes the following:
• Mechanical package drawing
• Pin/contact assignment information

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130 Freescale Semiconductor
5.1 MAPBGA Production Package 1568-01, 17 × 17 mm, 0.8 Pitch
See Figure 108 for the package drawing and dimensions of the production package.

Figure 108. Production Package: Mechanical Drawing

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Freescale Semiconductor 131
5.2 MAPBGA Signal Assignments
Table 94 and Table 95 list MAPBGA signals, alphabetized by signal name, for silicon revisions 2.0 and
2.1, respectively. Table 96 and Table 97 show the signal assignment on the i.MX35 ball map for silicon
revisions 2.0 and 2.1, respectively. The ball map for silicon revision 2.1 is different than the ballmap for
silicon revision 2.0. The layout for each revision is not compatible, so it is important that the correct
ballmap be used to implement the layout.

Table 94. Silicon Revision 2.0 Signal Ball Map Locations

Signal ID Ball Location Signal ID Ball Location

1
A0 A5 ATA_DATA7 Y3
A1 D7 ATA_DATA81 U4
A10 F15 ATA_DATA91 W3
A11 D5 ATA_DIOR1 Y6
A12 F6 ATA_DIOW1 W6
A13 B3 ATA_DMACK1 V6
A14 D14 ATA_DMARQ1 T3
A15 D15 ATA_INTRQ1 V2
A16 D13 ATA_IORDY1 U6
A17 D12 ATA_RESET_B1 T6
A18 E11 BCLK E14
A19 D11 BOOT_MODE0 W10
A2 E7 BOOT_MODE1 U9
A20 D10 CAPTURE V12
A21 E10 CAS E16
A22 D9 CLK_MODE0 Y10
A23 E9 CLK_MODE1 T10
A24 D8 CLKO V10
A25 E8 COMPARE T12
A3 C6 CONTRAST1 L16
A4 D6 CS0 F17
A5 B5 CS1 E19
A6 C5 CS2 B20
A7 A4 CS3 C19
A8 B4 CS4 E18
A9 A3 CS5 F19
ATA_BUFF_EN1 T5 CSI_D101 V16
ATA_CS01 V7 CSI_D111 T15
ATA_CS11 T7 CSI_D121 W16
ATA_DA01 R4 CSI_D131 V15
ATA_DA11 V1 CSI_D141 U14
ATA_DA21 R5 CSI_D151 Y16
ATA_DATA01 Y5 CSI_D81 U15
ATA_DATA11 W5 CSI_D91 W17
ATA_DATA101 V3 CSI_HSYNC1 V14
ATA_DATA111 Y2 CSI_MCLK1 W15
ATA_DATA121 U3 CSI_PIXCLK1 Y15

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 Table 94. Silicon Revision 2.0 Signal Ball Map Locations (continued)

Signal ID Ball Location Signal ID Ball Location

ATA_DATA131 W2 CSI_VSYNC 1
T14
ATA_DATA141 W1 CSPI1_MISO V9
ATA_DATA151 T4 CSPI1_MOSI W9
ATA_DATA21 V5 CSPI1_SCLK W8
ATA_DATA3 U5 CSPI1_SPI_RDY T8
ATA_DATA4 Y4 CSPI1_SS0 Y8
ATA_DATA5 W4 CSPI1_SS1 U8
ATA_DATA6 V4 CTS1 R3
CTS2 G5 FEC_TDATA0 P5
D0 A2 FEC_TDATA1 M4
D1 D4 FEC_TDATA2 M5
D10 D2 FEC_TDATA3 L6
D11 E6 FEC_TX_CLK P4
D12 E3 FEC_TX_EN T1
D13 F5 FEC_TX_ERR N4
D14 D1 FSR K5
D15 E2 FST J1
D2 B2 FUSE_VDD P13
D3 E5 FUSE_VSS M11
D3_CLS1 L17 GPIO1_0 T11
D3_DRDY1 L20 GPIO1_1 Y11
D3_FPSHIFT1 L15 GPIO2_0 U11
D3_HSYNC1 L18 GPIO3_0 V11
D3_REV1 M17 HCKR K2
D3_SPL1 M18 HCKT J5
D3_VSYNC1 M19 I2C1_CLK M20
D4 C3 I2C1_DAT N17
D5 B1 I2C2_CLK L3
D6 D3 I2C2_DAT M1
D7 C2 LBA D20
D8 C1 LD01 F20
D9 E4 LD11 G18
DE_B W19 LD101 H20
DQM0 B19 LD111 J18
DQM1 D17 LD121 J16
DQM2 D16 LD131 J19
DQM3 C18 LD141 J17
EB0 F18 LD151 J20
EB1 F16 LD161 K14
ECB D19 LD171 K19
EXT_ARMCLK V8 LD181 K18
EXTAL_AUDIO W20 LD191 K20
EXTAL24M T20 LD21 G17
FEC_COL P3 LD201 K16
FEC_CRS N5 LD211 K17
FEC_MDC R1 LD221 K15

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 Table 94. Silicon Revision 2.0 Signal Ball Map Locations (continued)

Signal ID Ball Location Signal ID Ball Location

FEC_MDIO P1 LD231 L19
FEC_RDATA0 P2 LD31 G16
FEC_RDATA1 N2 LD41 G19
FEC_RDATA2 M3 LD51 H16
FEC_RDATA3 N1 LD61 H18
FEC_RX_CLK R2 LD71 G20
FEC_RX_DV T2 LD81 H17
FEC_RX_ERR N3 LD91 H19
MA10 C4 NVCC_EMI2 G12
MGND N11 NVCC_EMI2 F13
MLB_CLK W13 NVCC_EMI2 F14
MLB_DAT Y13 NVCC_EMI3 G14
MLB_SIG W12 NVCC_JTAG P16
MVDD P11 NVCC_LCDC H14
NF_CE0 G3 NVCC_LCDC J14
NFALE F2 NVCC_LCDC L14
NFCLE E1 NVCC_LCDC M14
NFRB F3 NVCC_MISC K6
NFRE_B F1 NVCC_MISC K7
NFWE_B G2 NVCC_MISC L8
NFWP_B F4 NVCC_MLB R10
NGND_ATA M9 NVCC_NFC G6
NGND_ATA P9 NVCC_NFC H6
NGND_ATA L10 NVCC_NFC H7
NGND_CRM L11 NVCC_SDIO P14
NGND_CSI N10 OE E20
NGND_EMI1 H8 OSC_AUDIO_VDD V20
NGND_EMI1 H10 OSC_AUDIO_VSS U19
NGND_EMI1 J10 OSC24M_VDD T19
NGND_EMI2 J11 OSC24M_VSS T18
NGND_EMI3 J12 PGND M12
NGND_EMI3 K12 PHY1_VDDA M15
NGND_JTAG M13 PHY1_VDDA N20
NGND_LCDC K11 PHY1_VSSA N16
NGND_LCDC L12 PHY1_VSSA P20
NGND_MISC M7 PHY2_VDD R13
NGND_MISC K8 PHY2_VSS P12
NGND_MLB M10 POR_B W11
NGND_NFC K9 POWER_FAIL Y9
NGND_SDIO N12 PVDD N13
NVCC_ATA N6 RAS E15
NVCC_ATA P6 RESET_IN_B U10
NVCC_ATA P7 RTCK U18
NVCC_ATA P8 RTS1 U1
NVCC_CRM R9 RTS2 G1
NVCC_CSI R11 RW C20

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 Table 94. Silicon Revision 2.0 Signal Ball Map Locations (continued)

Signal ID Ball Location Signal ID Ball Location

NVCC_EMI1 G7 RXD1 U2
NVCC_EMI1 G8 RXD2 H3
NVCC_EMI1 G9 SCK4 L4
NVCC_EMI1 H9 SCK5 L5
NVCC_EMI1 F10 SCKR K3
NVCC_EMI1 G10 SCKT J4
NVCC_EMI1 F11 SD0 C17
NVCC_EMI1 G11 SD1 A19
SD1_CLK V18 SDCLK E12
SD1_CMD Y19 SDCLK_B E13
SD1_DATA0 R14 SDQS0 B17
SD1_DATA1 U16 SDQS1 A13
SD1_DATA2 W18 SDQS2 A10
SD1_DATA3 V17 SDQS3 C7
SD10 A15 SDWE G15
SD11 B15 SJC_MOD U17
SD12 C13 SRXD4 L1
SD13 B14 SRXD5 K4
SD14 A14 STXD4 M2
SD15 B13 STXD5 K1
SD16 C12 STXFS4 L2
SD17 C11 STXFS5 J6
SD18 A12 TCK R17
SD19 B12 TDI P15
SD2 B18 TDO R15
SD2_CLK W14 TEST_MODE Y7
SD2_CMD U13 TMS R16
SD2_DATA0 V13 TRSTB T16
SD2_DATA1 T13 TTM_PIN M16
SD2_DATA2 Y14 TX0 G4
SD2_DATA3 U12 TX1 H1
SD20 B11 TX2_RX3 H5
SD21 A11 TX3_RX2 J2
SD22 C10 TX4_RX1 H4
SD23 B10 TX5_RX0 J3
SD24 A9 TXD1 R6
SD25 C9 TXD2 H2
SD26 B9 USBOTG_OC U7
SD27 A8 USBOTG_PWR W7
SD28 B8 USBPHY1_DM N19
SD29 C8 USBPHY1_DP P19
SD3 C16 USBPHY1_RREF R19
SD30 A7 USBPHY1_UID N18
SD31 B7 USBPHY1_UPLLGND N14
SD4 A18 USBPHY1_UPLLVDD N15
SD5 C15 USBPHY1_UPLLVDD P17

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 Table 94. Silicon Revision 2.0 Signal Ball Map Locations (continued)

Signal ID Ball Location Signal ID Ball Location

SD6 A17 USBPHY1_VBUS P18
SD7 B16 USBPHY1_VDDA_BIAS R20
SD8 C14 USBPHY1_VSSA_BIAS R18
SD9 A16 USBPHY2_DM Y17
SDBA0 A6 USBPHY2_DP Y18
SDBA1 B6 VDD M6
SDCKE0 D18 VDD F7
SDCKE1 E17 VDD J7
VDD L7 VSS L9
VDD N7 VSS N9
VDD R7 VSS K10
VDD F8 VSS P10
VDD R8 VSS H11
VDD F9 VSS H12
VDD F12 VSS H13
VDD R12 VSS J13
VDD G13 VSS K13
VDD H15 VSS L13
VDD J15 VSS T17
VSS A1 VSS A20
VSS Y1 VSS Y20
VSS J8 VSTBY T9
VSS M8 WDOG_RST Y12
VSS N8 XTAL_AUDIO V19
VSS J9 XTAL24M U20
1 Not available for the MCIMX351.

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 Table 95. Silicon Revision 2.1 Signal Ball Map Locations

Signal ID Ball Location Signal ID Ball Location

A0 A5 ATA_DATA7 Y3
A1 D7 ATA_DATA8 U4
A10 F15 ATA_DATA9 W3
A11 D5 ATA_DIOR Y6
A12 F6 ATA_DIOW W6
A13 B3 ATA_DMACK V6
A14 D14 ATA_DMARQ T3
A15 D15 ATA_INTRQ V2
A16 D13 ATA_IORDY U6
A18 D12 ATA_RESET_B T6
SDQS1 E11 SDQS0 E14
A19 D11 BOOT_MODE0 W10
A2 E7 BOOT_MODE1 U9
A21 D10 CAPTURE V12
SDQS2 E10 RAS E16
A22 D9 CLK_MODE0 Y10
SDQS3 E9 CLK_MODE1 T10
A24 D8 CLKO V10
A25 E8 COMPARE T12
A3 C6 CONTRAST L16
A4 D6 CS0 F17
A5 B5 CS1 E19
A6 C5 CS2 B20
A7 A4 CS3 C19
A8 B4 CS4 E18
A9 A3 CS5 F19
ATA_BUFF_EN1 T5 CSI_D10 V16
ATA_CS0 V7 CSI_D11 T15
ATA_CS1 T7 CSI_D12 W16
ATA_DA0 R4 CSI_D13 V15
ATA_DA1 V1 CSI_D14 U14
ATA_DA2 R5 CSI_D15 Y16
ATA_DATA0 Y5 CSI_D8 U15
ATA_DATA1 W5 CSI_D9 W17
ATA_DATA10 V3 CSI_HSYNC V14
ATA_DATA11 Y2 CSI_MCLK W15
ATA_DATA12 U3 CSI_PIXCLK Y15
ATA_DATA13 W2 CSI_VSYNC T14
ATA_DATA14 W1 CSPI1_MISO V9
ATA_DATA15 T4 CSPI1_MOSI W9
ATA_DATA2 V5 CSPI1_SCLK W8
ATA_DATA3 U5 CSPI1_SPI_RDY T8
ATA_DATA4 Y4 CSPI1_SS0 Y8
ATA_DATA5 W4 CSPI1_SS1 U8
ATA_DATA6 V4 CTS1 R3

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 Table 95. Silicon Revision 2.1 Signal Ball Map Locations (continued)

Signal ID Ball Location Signal ID Ball Location

CTS2 G5 FEC_TDATA0 P5
D0 A2 FEC_TDATA1 M4
D1 D4 FEC_TDATA2 M5
D10 D2 FEC_TDATA3 L6
D11 E6 FEC_TX_CLK P4
D12 E3 FEC_TX_EN T1
D13 F5 FEC_TX_ERR N4
D14 D1 FSR K5
D15 E2 FST J1
D2 B2 FUSE_VDD P13
D3 E5 FUSE_VSS M11
D3_CLS L17 GPIO1_0 T11
D3_DRDY L20 GPIO1_1 Y11
D3_FPSHIFT L15 GPIO2_0 U11
D3_HSYNC L18 GPIO3_0 V11
D3_REV M17 HCKR K2
D3_SPL M18 HCKT J5
D3_VSYNC M19 I2C1_CLK M20
D4 C3 I2C1_DAT N17
D5 B1 I2C2_CLK L3
D6 D3 I2C2_DAT M1
D7 C2 LBA D20
D8 C1 LD0 F20
D9 E4 LD1 G18
DE_B W19 LD10 H20
DQM0 B19 LD11 J18
SDCKE1 D17 LD12 J16
DQM2 D16 LD13 J19
DQM3 C18 LD14 J17
EB0 F18 LD15 J20
EB1 F16 LD16 K14
ECB D19 LD17 K19
EXT_ARMCLK V8 LD18 K18
EXTAL_AUDIO W20 LD19 K20
EXTAL24M T20 LD2 G17
FEC_COL P3 LD20 K16
FEC_CRS N5 LD21 K17
FEC_MDC R1 LD22 K15
FEC_MDIO P1 LD23 L19
FEC_RDATA0 P2 LD3 G16
FEC_RDATA1 N2 LD4 G19
FEC_RDATA2 M3 LD5 H16
FEC_RDATA3 N1 LD6 H18
FEC_RX_CLK R2 LD7 G20
FEC_RX_DV T2 LD8 H17
FEC_RX_ERR N3 LD9 H19

i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10

138 Freescale Semiconductor
 Table 95. Silicon Revision 2.1 Signal Ball Map Locations (continued)

Signal ID Ball Location Signal ID Ball Location

MA10 C4 NVCC_EMI2 G12
MGND N11 NVCC_EMI2 F13
MLB_CLK W13 VSS F14
MLB_DAT Y13 NVCC_EMI3 G14
MLB_SIG W12 NVCC_JTAG P16
MVDD P11 NVCC_LCDC H14
NF_CE0 G3 NVCC_LCDC J14
NFALE F2 NVCC_LCDC L14
NFCLE E1 NVCC_LCDC M14
NFRB F3 NVCC_MISC K6
NFRE_B F1 NVCC_MISC K7
NFWE_B G2 NVCC_MISC L8
NFWP_B F4 NVCC_MLB R10
NGND_ATA M9 NVCC_NFC G6
NGND_ATA P9 NVCC_NFC H6
NGND_ATA L10 NVCC_NFC H7
NGND_CRM L11 NVCC_SDIO P14
NGND_CSI N10 OE E20
NGND_EMI1 H8 OSC_AUDIO_VDD V20
NVCC_EMI1 H10 OSC_AUDIO_VSS U19
NGND_EMI1 J10 OSC24M_VDD T19
NGND_EMI2 J11 OSC24M_VSS T18
NGND_EMI3 J12 PGND M12
NGND_EMI3 K12 PHY1_VDDA M15
NGND_JTAG M13 PHY1_VDDA N20
NGND_LCDC K11 PHY1_VSSA N16
NGND_LCDC L12 PHY1_VSSA P20
NGND_MISC M7 PHY2_VDD R13
NGND_MISC K8 PHY2_VSS P12
NGND_MLB M10 POR_B W11
NGND_NFC K9 POWER_FAIL Y9
NGND_SDIO N12 PVDD N13
NVCC_ATA N6 BCLK E15
NVCC_ATA P6 RESET_IN_B U10
NVCC_ATA P7 RTCK U18
NVCC_ATA P8 RTS1 U1
NVCC_CRM R9 RTS2 G1
NVCC_CSI R11 RW C20
NVCC_EMI1 G7 RXD1 U2
NVCC_EMI1 G8 RXD2 H3
NVCC_EMI1 G9 SCK4 L4
NVCC_EMI1 H9 SCK5 L5
NGND_EMI1 F10 SCKR K3
NVCC_EMI1 G10 SCKT J4
NVCC_EMI1 F11 DQM1 C17
NVCC_EMI1 G11 SD1 A19

i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10

Freescale Semiconductor 139
 Table 95. Silicon Revision 2.1 Signal Ball Map Locations (continued)

Signal ID Ball Location Signal ID Ball Location

SD1_CLK V18 SDCLK E12
SD1_CMD Y19 SDCLK_B E13
SD1_DATA0 R14 SD0 B17
SD1_DATA1 U16 SD15 A13
SD1_DATA2 W18 SD23 A10
SD1_DATA3 V17 A23 C7
SD10 A15 SDWE G15
SD11 B15 SJC_MOD U17
A17 C13 SRXD4 L1
SD13 B14 SRXD5 K4
SD14 A14 STXD4 M2
SD12 B13 STXD5 K1
SD16 C12 STXFS4 L2
SD17 C11 STXFS5 J6
SD18 A12 TCK R17
SD19 B12 TDI P15
SD2 B18 TDO R15
SD2_CLK W14 TEST_MODE Y7
SD2_CMD U13 TMS R16
SD2_DATA0 V13 TRSTB T16
SD2_DATA1 T13 TTM_PIN M16
SD2_DATA2 Y14 TX0 G4
SD2_DATA3 U12 TX1 H1
SD20 B11 TX2_RX3 H5
SD21 A11 TX3_RX2 J2
A20 C10 TX4_RX1 H4
SD22 B10 TX5_RX0 J3
SD24 A9 TXD1 R6
SD25 C9 TXD2 H2
SD26 B9 USBOTG_OC U7
SD27 A8 USBOTG_PWR W7
SD28 B8 USBPHY1_DM N19
SD29 C8 USBPHY1_DP P19
SD3 C16 USBPHY1_RREF R19
SD30 A7 USBPHY1_UID N18
SD31 B7 USBPHY1_UPLLGND N14
SD4 A18 USBPHY1_UPLLVDD N15
SD5 C15 USBPHY1_UPLLVDD P17
SD6 A17 USBPHY1_VBUS P18
SD7 B16 USBPHY1_VDDA_BIAS R20
SD8 C14 USBPHY1_VSSA_BIAS R18
SD9 A16 USBPHY2_DM Y17
SDBA0 A6 USBPHY2_DP Y18
SDBA1 B6 VDD M6
SDCKE0 D18 VDD F7
CAS E17 VDD J7

i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10

140 Freescale Semiconductor
 Table 95. Silicon Revision 2.1 Signal Ball Map Locations (continued)

Signal ID Ball Location Signal ID Ball Location

VDD L7 VSS L9
VDD N7 VSS N9
VDD R7 VSS K10
VDD F8 VSS P10
VDD R8 VSS H11
VDD F9 VSS H12
VDD F12 NVCC_EMI2 H13
VDD R12 VSS J13
VDD G13 VSS K13
VDD H15 VSS L13
VDD J15 VSS T17
VSS A1 VSS A20
VSS Y1 VSS Y20
VSS J8 VSTBY T9
VSS M8 WDOG_RST Y12
VSS N8 XTAL_AUDIO V19
VSS J9 XTAL24M U20
1
Not available for the MCIMX351.

i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10

Freescale Semiconductor 141
 Table 96. Silicon Revision 2.0 Ball Map—17 x 17, 0.8 mm Pitch1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

A VSS D0 A9 A7 A0 SDB SD3 SD2 SD2 SDQ SD2 SD1 SDQ SD1 SD1 SD9 SD6 SD4 SD1 VSS A
A0 0 7 4 S2 1 8 S1 4 0

B D5 D2 A13 A8 A5 SDB SD3 SD2 SD2 SD2 SD2 SD1 SD1 SD1 SD1 SD7 SDQ SD2 DQM CS2 B
A1 1 8 6 3 0 9 5 3 1 S0 0

C D8 D7 D4 MA1 A6 A3 SDQ SD2 SD2 SD2 SD1 SD1 SD1 SD8 SD5 SD3 SD0 DQM CS3 RW C
0 S3 9 5 2 7 6 2 3

D D14 D10 D6 D1 A11 A4 A1 A24 A22 A20 A19 A17 A16 A14 A15 DQM DQM SDC ECB LBA D
2 1 KE0

E NFC D15 D12 D9 D3 D11 A2 A25 A23 A21 A18 SDC SDC BCL RAS CAS SDC CS4 CS1 OE E
LE LK LK_ K KE1
B

F NFR NFA NFR NFW D13 A12 VDD VDD VDD NVC NVC VDD NVC NVC A10 EB1 CS0 EB0 CS5 LD0 F
E_B LE B P_B C_E C_E C_E C_E
MI1 MI1 MI2 MI2

G RTS NFW NF_ TX0 CTS NVC NVC NVC NVC NVC NVC NVC VDD NVC SDW LD3 LD2 LD1 LD4 LD7 G
2 E_B CE0 2 C_N C_E C_E C_E C_E C_E C_E C_E E
FC MI1 MI1 MI1 MI1 MI1 MI2 MI3

H TX1 TXD RXD TX4_ TX2_ NVC NVC NGN NVC NGN VSS VSS VSS NVC VDD LD5 LD8 LD6 LD9 LD10 H
2 2 RX1 RX3 C_N C_N D_E C_E D_E C_L
FC FC MI1 MI1 MI1 CDC

J FST TX3_ TX5_ SCK HCK STX VDD VSS VSS NGN NGN NGN VSS NVC VDD LD12 LD14 LD11 LD13 LD15 J
RX2 RX0 T T FS5 D_E D_E D_E C_L
MI1 MI2 MI3 CDC

K STX HCK SCK SRX FSR NVC NVC NGN NGN VSS NGN NGN VSS LD16 LD22 LD20 LD21 LD18 LD17 LD19 K
D5 R R D5 C_MI C_MI D_MI D_N D_L D_E
SC SC SC FC CDC MI3

L SRX STX I2C2 SCK SCK FEC VDD NVC VSS NGN NGN NGN VSS NVC D3_ CON D3_ D3_ LD23 D3_ L
D4 FS4 _CL 4 5 _TD C_MI D_A D_C D_L C_L FPS TRA CLS HSY DRD
K ATA3 SC TA RM CDC CDC HIFT ST NC Y

M I2C2 STX FEC FEC FEC VDD NGN VSS NGN NGN FUS PGN NGN NVC PHY TTM D3_ D3_ D3_ I2C1 M
_DAT D4 _RD _TD _TD D_MI D_A D_M E_V D D_JT C_L 1_V _PIN REV SPL VSY _CL
ATA2 ATA1 ATA2 SC TA LB SS AG CDC DDA NC K

N FEC FEC FEC FEC FEC NVC VDD VSS VSS NGN MGN NGN PVD USB USB PHY I2C1 USB USB PHY N
_RD _RD _RX _TX_ _CR C_A D_C D D_S D PHY PHY 1_V _DAT PHY PHY 1_V
ATA3 ATA1 _ER ERR S TA SI DIO 1_U 1_U SSA 1_UI 1_D DDA
R PLL PLLV D M
GND DD

P FEC FEC FEC FEC FEC NVC NVC NVC NGN VSS MVD PHY FUS NVC TDI NVC USB USB USB PHY P
_MDI _RD _CO _TX_ _TD C_A C_A C_A D_A D 2_V E_V C_S C_JT PHY PHY PHY 1_V
O ATA0 L CLK ATA0 TA TA TA TA SS DD DIO AG 1_U 1_V 1_D SSA
PLLV BUS P
DD

R FEC FEC CTS ATA_ ATA_ TXD VDD VDD NVC NVC NVC VDD PHY SD1 TDO TMS TCK USB USB USB R
_MD _RX 1 DA0 DA2 1 C_C C_M C_C 2_V _DAT PHY PHY PHY
C _CL RM LB SI DD A0 1_V 1_R 1_V
K SSA REF DDA
_BIA _BIA
S S

T FEC FEC ATA_ ATA_ ATA_ ATA_ ATA_ CSPI VST CLK GPI COM SD2 CSI_ CSI_ TRS VSS OSC OSC EXT T
_TX_ _RX DMA DATA BUF RES CS1 1_S BY _MO O1_ PAR _DAT VSY D11 TB 24M 24M AL24
EN _DV RQ 15 F_E ET_ PI_R DE1 0 E A1 NC _VS _VD M
N B DY S D

U RTS RXD ATA_ ATA_ ATA_ ATA_ USB CSPI BOO RES GPI SD2 SD2 CSI_ CSI_ SD1 SJC RTC OSC XTAL U
1 1 DATA DATA DATA IOR OTG 1_S T_M ET_I O2_ _DAT _CM D14 D8 _DAT _MO K _AU 24M
12 8 3 DY _OC S1 ODE N_B 0 A3 D A1 D DIO_
1 VSS

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142 Freescale Semiconductor
 Table 96. Silicon Revision 2.0 Ball Map—17 x 17, 0.8 mm Pitch1 (continued)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

V ATA_ ATA_ ATA_ ATA_ ATA_ ATA_ ATA_ EXT CSPI CLK GPI CAP SD2 CSI_ CSI_ CSI_ SD1 SD1 XTAL OSC V
DA1 INTR DATA DATA DATA DMA CS0 _AR 1_MI O O3_ TUR _DAT HSY D13 D10 _DAT _CL _AU _AU
Q 10 6 2 CK MCL SO 0 E A0 NC A3 K DIO DIO_
K VDD

W ATA_ ATA_ ATA_ ATA_ ATA_ ATA_ USB CSPI CSPI BOO POR MLB MLB SD2 CSI_ CSI_ CSI_ SD1 DE_ EXT W
DATA DATA DATA DATA DATA DIO OTG 1_S 1_M T_M _B _SIG _CL _CL MCL D12 D9 _DAT B AL_
14 13 9 5 1 W _PW CLK OSI ODE K K K A2 AUDI
R 0 O

Y VSS ATA_ ATA_ ATA_ ATA_ ATA_ TES CSPI POW CLK GPI WD MLB SD2 CSI_ CSI_ USB USB SD1 VSS Y
DATA DATA DATA DATA DIO T_M 1_S ER_ _MO O1_ OG_ _DAT _DAT PIXC D15 PHY PHY _CM
11 7 4 0 R ODE S0 FAIL DE0 1 RST A2 LK 2_D 2_D D
M P
1
See Table 95 for pins unavailable in the MCIMX351 SoC.

Table 97. Silicon Revision 2.1 Ball Map—17 x 17, 0.8 mm Pitch
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

A GND D0 A9 A7 A0 SDB SD30 SD27 SD24 SD23 SD21 SD18 SD15 SD14 SD10 SD9 SD6 SD4 SD1 GND A
A0

B D5 D2 A13 A8 A5 SDB SD31 SD28 SD26 SD22 SD20 SD19 SD12 SD13 SD11 SD7 SD0 SD2 DQM CS2 B
A1 0

C D8 D7 D4 MA1 A6 A3 A23 SD29 SD25 A20 SD17 SD16 A17 SD8 SD5 SD3 DQM DQM CS3 RW C
0 1 3

D D14 D10 D6 D1 A11 A4 A1 A24 A22 A21 A19 A18 A16 A14 A15 DQM SDC SDC ECB LBA D
2 KE1 KE0

E NFC D15 D12 D9 D3 D11 A2 A25 SDQ SDQ SDQ SDC SDC SDQ BCL RAS CAS CS4 CS1 OE E
LE S3 S2 S1 LK LK_B S0 K

F NFR NFAL NFR NFW D13 A12 VDD VDD VDD GND NVC VDD NVC GND A10 EB1 CS0 EB0 CS5 LD0 F
E_B E B P_B 7 7 7 C_E 7 C_E
MI1 MI2

G RTS NFW NF_ TX0 CTS NVC NVC NVC NVC NVC NVC NVC VDD NVC SDW LD3 LD2 LD1 LD4 LD7 G
2 E_B CE0 2 C_N C_E C_E C_E C_E C_E C_E 6 C_E E
FC MI1 MI1 MI1 MI1 MI1 MI2 MI3

H TX1 TXD RXD TX4_ TX2_ NVC NVC GND NVC NVC GND GND NVC NVC VDD LD5 LD8 LD6 LD9 LD10 H
2 2 RX1 RX3 C_N C_N C_E C_E C_E C_L 5
FC FC MI1 MI1 MI2 CDC

J FST TX3_ TX5_ SCK HCK STX VDD GND GND GND GND GND GND NVC VDD LD12 LD14 LD11 LD13 LD15 J
RX2 RX0 T T FS5 1 C_L 5
CDC

K STX HCK SCK SRX FSR NVC NVC GND GND GND GND GND GND LD16 LD22 LD20 LD21 LD18 LD17 LD19 K
D5 R R D5 C_MI C_MI
SC SC

L SRX STX I2C2 SCK SCK FEC VDD NVC GND GND GND GND GND NVC D3_F CON D3_ D3_ LD23 D3_ L
D4 FS4 _CLK 4 5 _TDA 2 C_MI C_L PSHI TRA CLS HSY DRD
TA3 SC CDC FT ST NC Y

M I2C2 STX FEC FEC FEC VDD GND GND GND GND FUS PGN GND NVC PHY TTM D3_ D3_S D3_V I2C1 M
_DAT D4 _RD _TDA _TDA 2 E_V D C_L 1_VD _PAD REV PL SYN _CLK
ATA2 TA1 TA2 SS CDC DA C

N FEC FEC FEC FEC FEC NVC VDD GND GND GND MGN GND PVD USB USB PHY I2C1 USB USB PHY N
_RD _RD _RX_ _TX_ _CR C_AT 3 D D PHY PHY 1_VS _DAT PHY PHY 1_VD
ATA3 ATA1 ERR ERR S A 1_UP 1_UP SA 1_UI 1_D DA
LLG LLVD D M
ND D

i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10

Freescale Semiconductor 143
 Table 97. Silicon Revision 2.1 Ball Map—17 x 17, 0.8 mm Pitch (continued)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

P FEC FEC FEC FEC FEC NVC NVC NVC GND GND MVD PHY FUS NVC TDI NVC USB USB USB PHY P
_MDI _RD _CO _TX_ _TDA C_AT C_AT C_AT D 2_VS E_V C_S C_JT PHY PHY PHY 1_VS
O ATA0 L CLK TA0 A A A S DD DIO AG 1_UP 1_VB 1_DP SA
LLVD US
D

R FEC FEC CTS ATA_ ATA_ TXD VDD VDD NVC NVC NVC VDD PHY SD1_ TDO TMS TCK USB USB USB R
_MD _RX_ 1 DA0 DA2 1 3 3 C_C C_M C_C 4 2_VD DATA PHY PHY PHY
C CLK RM LB SI D 0 1_VS 1_R 1_VD
SA_ REF DA_
BIAS BIAS

T FEC FEC ATA_ ATA_ ATA_ ATA_ ATA_ CSPI VST CLK_ GPIO COM SD2_ CSI_ CSI_ TRS GND OSC OSC EXTA T
_TX_ _RX_ DMA DATA BUF RES CS1 1_SP BY MOD 1_0 PAR DATA VSY D11 TB 24M_ 24M_ L24M
EN DV RQ 15 F_E ET_B I_RD E1 E 1 NC VSS VDD
N Y

U RTS RXD ATA_ ATA_ ATA_ ATA_ USB CSPI BOO RES GPIO SD2_ SD2_ CSI_ CSI_ SD1_ SJC_ RTC OSC XTAL U
1 1 DATA DATA DATA IORD OTG 1_SS T_M ET_I 2_0 DATA CMD D14 D8 DATA MOD K _AU 24M
12 8 3 Y _OC 1 ODE N_B 3 1 DIO_
1 VSS

V ATA_ ATA_ ATA_ ATA_ ATA_ ATA_ ATA_ EXT_ CSPI CLK GPIO CAP SD2_ CSI_ CSI_ CSI_ SD1_ SD1_ XTAL OSC V
DA1 INTR DATA DATA DATA DMA CS0 ARM 1_MI O 3_0 TUR DATA HSY D13 D10 DATA CLK _AU _AU
Q 10 6 2 CK CLK SO E 0 NC 3 DIO DIO_
VDD

W ATA_ ATA_ ATA_ ATA_ ATA_ ATA_ USB CSPI CSPI BOO POR MLB MLB SD2_ CSI_ CSI_ CSI_ SD1_ DE_ EXTA W
DATA DATA DATA DATA DATA DIO OTG 1_SC 1_M T_M _B _SIG _CLK CLK MCL D12 D9 DATA B L_AU
14 13 9 5 1 W _PW LK OSI ODE K 2 DIO
R 0

Y GND ATA_ ATA_ ATA_ ATA_ ATA_ TES CSPI POW CLK_ GPIO WDO MLB SD2_ CSI_ CSI_ USB USB SD1_ GND Y
DATA DATA DATA DATA DIOR T_M 1_SS ER_ MOD 1_1 G_R _DAT DATA PIXC D15 PHY PHY CMD
11 7 4 0 ODE 0 FAIL E0 ST 2 LK 2_D 2_DP
M

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

6 Product Documentation
All related product documentation for the i.MX35 processor is located at http://www.freescale.com/imx.

i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10

144 Freescale Semiconductor
7 Revision History
Table 98 shows the revision history of this document. Note: There were no revisions of this document
between revision 1 and revision 4 or between revision 6 and revision 7.
Table 98. i.MX35 Data Sheet Revision History

Revision
Date Substantive Change(s)
Number

10 06/2012 • In Table 2, "Functional Differences in the i.MX35 Parts," on page 3, added two columns for part
numbers MCIMX353 and MCIMX357.
• Added Table 29, "Clock Input Tolerance," on page 31 in Section 4.9.3, “DPLL Electrical
Specifications.”
• Updated Table 39, "DDR2 SDRAM Timing Parameter Table," on page 50 for DDR2-400 values.
• Updated Table 41, "DDR2 SDRAM Write Cycle Parameters," on page 52 for DDR2-400 values.
• Added Table 15, "AC Requirements of I/O Pins," on page 24.
• Updated WE4 parameter in Table 33, "WEIM Bus Timing Parameters," on page 37.
9 08/2010 • Updated Table 32, “NFC Timing Parameters.”
• Updated Table 33, “WEIM Bus Timing Parameters.”
8 04/2010 • Updated Table 14, “I/O Pin DC Electrical Characteristics.”
7 12/18/2009 • Updated Table 1, “Ordering Information.”
6 10/21/2009 • Added information for silicon rev. 2.1
• Updated Table 1, “Ordering Information.”
• Added Table 95, “Silicon Revision 2.1 Signal Ball Map Locations.”
• Added Table 97, “Silicon Revision 2.1 Ball Map—17 x 17, 0.8 mm Pitch.”
5 08/06/2009 • Added a line for TA = –40 to 85 oC in Table 14, “I/O Pin DC Electrical Characteristics”
• Filled in TBDs in Table 14.
• Revised Figure 15 and Table 33 by removing FCE = 0 and FCE = 1. Added footnote 3 to the table.
• Added Table 26, “AC Electrical Characteristics of DDR Type IO Pins in SDRAM Mode Max Drive
(1.8 V).”
4 04/30/2009 Note: There were no revisions of this document between revision 1 and revision 4.
• In Section 4.3.1, “Powering Up,” reverse positions of steps 5 and 6.
• Updated values in Table 10, “i.MX35 Power Modes.”
• Added Section 4.4, “Reset Timing.”
• In Section 4.8.2, “AC Electrical Characteristics for DDR Pins (DDR2, Mobile DDR, and SDRAM
Modes),” removed Slow Slew rate tables, relabeled Table 24, “AC Electrical Characteristics of DDR
Type IO Pins in mDDR Mode,” and Table 25, “AC Electrical Characteristics of DDR Type IO Pins in
SDRAM Mode,” to exclude mention of slew rate.
• In Section 4.9.5.2, “Wireless External Interface Module (WEIM),” modified Figure 16, “Synchronous
Memory Timing Diagram for Read Access—WSC = 1,” through Figure 21, “Muxed A/D Mode Timing
Diagram for Synchronous Read Access— WSC = 7, LBA = 1, LBN = 1, LAH = 1, OEA = 7.”
• In Section 4.9.6, “Enhanced Serial Audio Interface (ESAI) Timing Specifications,” modified
Figure 36, “ESAI Transmitter Timing,” and Figure 37, “ESAI Receiver Timing,” to remove extraneous
signals. Removed a note from Figure 36, “ESAI Transmitter Timing.”
3 03/2009 • In Section 4.3.1, “Powering Up,” reverse positions of steps 5 and 6.
2 02/2009 • Added the following parts to Table 1, “Ordering Information”: PCIMX357CVM5B,
MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Throughout
consumer data sheet: Removed or updated information related to Media Local Bus
interface.Updated Section 4.3.1, “Powering Up.”
• Updated values in Table 10, “i.MX35 Power Modes.”

i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10

Freescale Semiconductor 145
 Table 98. i.MX35 Data Sheet Revision History (continued)

Revision
Date Substantive Change(s)
Number

1 12/2008 • Updated Section 4.3.1, “Powering Up.”

• Section 4.7, “Module-Level AC Electrical Specifications”: Updated NFC, SDRAM and mDDR
SDRAM timing. Inserted DDR2 SDRAM timing.

0 10/2008 Initial public release

i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10

146 Freescale Semiconductor
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Document Number: MCIMX35SR2CEC

Rev. 10
06/2012