8086 Pin Configuration

MIN
MAX MODE
GND 1 VCC MODE
40
AD14 2 39 AD15
AD13 3 38 A16/S3
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE / S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 8086 31 RQ / GT0 (HOLD)
AD5 11 30 RQ / GT1 (HLDA)
AD4 12 CPU 29 LOCK (WR)
AD3 13 28 S2 (M/IO)
AD2 14 27 S1 (DT/R)
AD1 15 26 S0 (DEN)
AD0 16 25 QS0 (ALE)
NMI 17 24 QS1 (INTA)
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
Interrupt Interface of 8086 µP
Interrupts provide a mechanism for quickly
changing program environment.
Transfer of program control is initiated by the
occurrence of either an event to the µP or an
event in its external hardware
The section of the program to which control
is transferred is called Interrupt Service
Routine (ISR).
 Interrupt Interface of 8086 µP
Interrupt program context switching mechanism
Interrupt occurs
Main Program
during the execution
of Nth instruction
Instruction N
Instruction N+1
Program control
Return of program is transferred to
control from the 1st line of ISR
end of ISR to the Main Program End
instruction N+1 of
the main program First instruction Interrupt
Service
Return Routine
 Interrupts
The 8088 and 8086 microcomputers are
capable of implementing any
combination of up to 256 interrupts.
They are divided into five groups:
External hardware interrupts
Non maskable interrupts
Software interrupts
Internal interrupts
Reset
 Interrupt Priority
The hardware, software and internal
interrupts are serviced on a priority basis
Reset
Internal interrupts and exceptions
Software interrupts
Nonmaskable interrupts
External hardware interrupts
 Interrupt Priority
Each interrupts are given different
priority level by assigning it a type
number.
Type 0 identifies the highest priority
interrupt, and type 255 identifies the
lowest priority interrupt
 Interrupt Vectors
An interrupt vector contains the address of
the interrupt service routine.
The interrupt vector table is located in the
first 1,024 bytes of memory at address
00000H-003FFH.
It contains 256 different 4-byte interrupt
vectors.
The first 32 interrupt vectors either have
dedicated functions or are reserved.
The last 224 vectors are available as user
interrupt vectors
 Interrupt Vector Table
Memory Address
3FFH Type 255 Vector 255
User
available

80H Type 32 Vector 32

7CH Type 31 Vector 31
Reserved
14H Type 5 Vector 5
10H Type 4 Vector 4-Overflow
0CH Type 3 Vector 3-Break Point
08H Type 2 Vector 2-NMI
04H Type 1 Vector 1-Single Step
00H Type 0 Vector 0-Divide Error
 Interrupt Vector
Example 1
At what address are CS50 and IP50 stored in memory?
Ans: Each vector requires 4 consecutive bytes of
memory for storage.
Hence the address can be found by multiplying the
type no by 4.
The CS50 and IP50 represents the type 50 interrupt
vector.
Address = 4 x 50 = 200 =C8H
Therefore, IP50 stored at C8H and CS50 stored at CAH
 External hardware interrupt
interface signals
Minimum mode interrupt interface
IO/M INT 32
RD INT 33
WR INT 34

ALE
External h/w
AD0 - AD7 Interrupt
8086 µP
Interface
A8-A15
circuitry
INTR
INTA
Vcc DT/R
MN/MX
DEN INT255
 External Hardware Interrupt
Sequence

COMPLETE CURRENT
INSTRUCTION

INTERNAL Y
INTERRUPT?
N
NMI Y
N
Y Y ACK READ
INTR IF
INTERRUPT TYPE NO
N N
Y
TF PUSH
N A FLAGS
EXECUTE NEXT INSTRN B
External Hardware Interrupt
Sequence
B
A
CLEAR IF & TF

PUSH CS & IP

CALL ISR

EXECUTE USER
INTERRUPT PROCEDURE
POP IP & CS

POP FLAGS

RETURN TO MAIN
PROGRAM
 Interrupt Acknowledge Bus Cycle
1ST INTA BUS CYCLE 2nd INTA BUS CYCLE
T1 T2 T3 T4 T1 T2 T3 T4
CLK

ALE

INTA

AD0-AD7
VECTOR TYPE
 82C59A PROGRAMMABLE
INTERRUPT CONTROLLER (PIC)
The 8259A is an LSI peripheral IC designed to
simplify the implementation of the interrupt
interface in 8086µP.
The PIC IC can be configured for a wide
variety of applications.
It can detect level sensitive and edge
sensitive interrupts.
The PIC IC can be easily cascaded to expand
from 8 to 64 interrupt inputs.
Interface between 8086 &
8259

IR0
D0 – D7
IR1
8 8
0 A1 2
A0
8 INTR 5
INT 9
6 INTA
INTA IR7
CS
 Internal Architecture of 8259A
INTA INT
DATA
BUS CONTROL LOGIC
D0-D7 BUFFER

RD READ/
WR WRITE IN INTRRUPT
PRIORITY
A0 LOGIC SERVICE REQUEST
RESOLVER
CS REG REG
(ISR) (IRR)

CAS0 CASCADE
CAS1 BUFFER/
INTERRUPT MASK REG (IMR)
CAS2 COMP

SP/EN
 PIC 82C59A
The interrupt-request reg, in-service reg,
priority resolver, and interrupt-mask reg are
the key internal blocks of the 8259A.
The internal-mask reg can be used to enable
or mask out individually the interrupt request
inputs.
The IMR contains 8 bits, identified by M0
through M7.
The bits M0 to M7 correspond to interrupt
request inputs IR0 through IR7 respectively.
 PIC 82C59A
The Interrupt request register (IRR) stores
the current status of the interrupt request
inputs.
The values in these bit positions reflect
whether the interrupt inputs are active or
inactive.
The priority resolver determines which of the
active interrupt inputs has the highest
priority.
 PIC 82C59A
A single 8259A provides 8 vectored
interrupts.
If more interrupts are required, the
8259A is used in the cascade mode.
In the cascaded mode, up to 64
interrupt lines can be provided.
 Command Words of 8259A
Command Words of 8259A are divided
into two groups:
Initialization Command words (ICWs)
Operational Command words (OCWs)
 Initialization Sequence of 8259A
ICW1 A

ICW2
No (IC4 = 0) Is ICW4
Needed ?
No (Single = 1) In Cascade
Mode ? Yes (IC4 = 1)
ICW4
Yes (Single = 0)
ICW3
Ready to accept
Interrupt request
A
Initialization Command Word 1(ICW1)
A0 D7 D6 D5 D4 D3 D2 D1 D0

0 A7 A6 A5 1 LTIM ADI SNGL IC4

1=ICW4 Needed
Don’t care to 0=ICW4 Not
8086 µP Needed

1-Level triggered
0-Edge triggered 1-Single
0-Cascaded
Call address interval
0 for 8086 system
 PIC 8259A ICWs
Example 1
What value should be written into ICW1 in order
to configure the 8259A so that ICW4 is needed in
the initialization sequence, the system is going to
use multiple 8259As, and its inputs are to be level
sensitive? Assume that all unused bits are to be
logic 0.
Ans.
A0 D7 D6 D5 D4 D3 D2 D1 D0

0 A7 A6 A5 1 LTIM ADI SNGL IC4 =19H

0 0 0 1 1 0 0 1
Initialization Command Word 2(ICW2)
A0 D7 D6 D5 D4 D3 D2 D1 D0

1 T7 T6 T5 T4 T3 T2 T1 T0

For 8086 system T3 – T7 are

filled by most significant 5 bits
of interrupt type and the LSB 3-
bits are 0, for IR0
 PIC 8259A ICWs
Example 2
What should be the initialization command
word, if the type numbers output on the
bus by the device are to range from 70H to
77H ?
Ans
A0 D7 D6 D5 D4 D3 D2 D1 D0

1 T7 T6 T5 T4 T3 T2 T1 T0 =70H

0 1 1 1 0 0 0 0
Initialization Command Word 3(ICW3)
Master Mode ICW3

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 S7 S6 S5 S4 S3 S2 S1 S0

Sn = 1 IRn input has a slave

Sn = 0 IRn input does not have a slave
Initialization Command Word 3(ICW3)
Slave Mode ICW3
A0 D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 0 0 0 ID2 ID1 ID0

The ICW3 for a slave is used to load the

device with a 3-bit identification code ID0-ID2
This number must correspond to the IR
input of the master to which the slave’s INT
output is wired.
 PIC 8259A ICWs
Example 3
Assume that a master PIC is to be
configured so that its IR0 through IR3
inputs are to accept inputs directly from
external devices, but IR4 through IR7 are
to be supplied by the INT outputs of
slaves. What code should be used for the
initialization command word ICW3 ?
 PIC 8259A ICWs
Ans
Master Mode ICW3

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 S7 S6 S5 S4 S3 S2 S1 S0 =F0H
1 1 1 1 0 0 0 0
 Initialization Command Word 4(ICW4)
A0 D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 0 SFNM BUF M/S AEOI µPM

1=Special fully nested mode

1=MCS86 88 MODE
0=Not SFNM
0=MCS8085 MODE

BUF M/S Operation 1=Auto EOI

0 X Non buffered mode 0=Normal EOI

1 0 Buffered mode slave

1 1 Buffered mode master
8259A Operation Command Word
After appropriate ICWs are issued to 8259A,
it is ready to accept the interrupts.
Three operational command words are also
provided for controlling the operation of the
8259A.
These command words permit further
modifications to be made to the operation of
the interrupt controller.
8259A Operation Command Word
The Operational command word, OCW1
is used to access the contents of the
interrupt-mask register (IMR).
A write operation can be performed to
set or reset its bits.
This permits selective masking of the
interrupt inputs.
Operational Command Word 1(OCW1)

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 M7 M6 M5 M4 M3 M2 M1 M0

Interrupt
mask
1=Mask set
0=Mask reset
 8259A OCWs
Example 4
What should be the OCW1 code if interrupt
inputs IR0 through IR3, are to be masked
and IR4 through IR7 are to be unmasked?
Ans
A0 D7 D6 D5 D4 D3 D2 D1 D0

1 M7 M6 M5 M4 M3 M2 M1 M0 =0FH
0 0 0 0 1 1 1 1
Operational Command Word 2 &3
(OCW2 and OCW3)
The second operational command word,
OCW2, selects the appropriate priority scheme
and assigns an IR level.
The three LSB bits define the interrupt level.
The other 3 bits of the word,D7,D6,and D5
are called rotation (R), specific level (SL), and
End of Interrupt (EOI) respectively.
The OCW3 permits reading of the contents of
the ISR or IRR registers through s/w, issue of
poll command, and enable/disable of special
mask mode.