The Technology behind

PlayStation®2

Paul Holman
Sony Computer
Entertainment Europe
VP of Technology
 In this presentation

¾ Sony Computer Entertainment Overview

¾ Technical aspects of PlayStation 2

¾ The Future for PlayStation ….

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 Who Am I ?

SCEI R&D Group HQ

(Japan)

SCEI SCEA SCEE SCEA SCEI

R&D Business & Technology Group R&D BB Business Div.
(Japan) Technology (UK) (USA)

Architecture Tech. Technology

Dev. Environment Strategy Planning
Information Development

OS and Library Network Network Computer Graphics Network Business

Development Technology

Dev. Support Dev. Support Dev. Support

Man Machine I/F System Dev.
(Japan) (USA) (UK)

Simulation

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 Sony Computer Entertainment “Europe”

Launch - Apr 96 May 96 - Apr 97 May 97 - Apr 98 May 98-Apr 99 May 99- Jan 02
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 PlayStation 2

European Launched 24 November 2000

 Where are we now ?

September 2002 – 40 million PS2s shipped

worldwide (12+ million to SCEE region)

BUT … sales are seasonal – vast majority in

Christmas season

Sales are running at 2.4x original PlayStation at

the same point of lifecycle

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 Manufacturing Technology

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 A peek inside the factory ….

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 EE (Main Processor) – Joint Fab with
Toshiba in Ohita (0.18µ)

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 SCE Nagasaki - 0.18µ process for GS (Graphics Chip)

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Technology Group 11
 And what about the software ?

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 Disc manufacturing (CD and DVD)

¾ All Disc manufacturing carried out by Sony

DADC in Salzburg, Austria
¾ Includes proprietary copy control solutions
¾ PS2 discs are serialized
¾ “Just-in-time” ordering

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 The Technology inside the machine …

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 Technical Aspects of PlayStation 2

¾ The PlayStation 2 Development Environment

¾ System Architecture
¾ The Emotion Engine (EE)
¾ The Graphics Synthesiser (GS)
¾ The IO Processor (IOP)

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 Professional Development Environment
The TOOL

¾ Use the Linux-based tools

TV
TV that come with the TOOL
Controllers
Controllers ¾ With a Linux box you can
either:
Linux
Linux ¾ develop and compile on the
Box
Box Linux Box
¾ use the Linux Box purely for
LAN
LAN compilation and develop in
your favourite Windows Editor

PC
PC

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 Developing at home – PS2 Linux

¾ PlayStation 2 branded USB keyboard & mouse

¾ 10/100 Ethernet Adapter
¾ 40GB Hard Disk
¾ Monitor cable
¾ 2 x install DVD’s
¾ Linux
¾ Hardware Manuals
¾ Tools, Examples
¾ Simple EULA
¾ Launched: 22 May ’02
¾ € 249 (excl. VAT and Shipping) from http://www.linuxplay.com/
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 Here comes the science bit ...

System Architecture

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 PlayStation2

¾ 128-bit CPU core “Emotion Engine”

¾ GS “Graphics Synthesizer”
¾ SPU2 “Dynamic Sound Processor”
¾ I/O Processor (USB, i.Link)
¾ DVD/CD ROM disc system

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 The Emotion Engine - Specs

¾ CPU Core 128 bit CPU

¾ System Clock 300MHz
¾ Bus Bandwidth 3.2GB/sec
¾ Main Memory 32MB (Direct Rambus)
¾ Floating Point Calculation 6.2 GFLOPS
¾ 3D Geometry Performance 66 Million
polygons/sec
¾ Image Processor Unit MPEG2

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 Floating Point Vector Performance …

160
Geometry & Perspective Transformation
140
1/Distance
120 Distance
M vector/sec

100 Geometry Transformation

80
60
40
20
0
P2 (400 Mhz) P3 (500 Mhz) EE (300 Mhz)

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 Pixel Fill Rate

GS
2.4
Infinite Reality 2 0.9

Voodoo 3 (3500) 0.37 36x

Riva TNT 0.25

Octane 0.24

Power VR2 0.2

PlayStation 0.07

0 0.5 1 1.5 2 2.5

G pix/sec

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 System Architecture

VIDEO
RAM Emotion
Emotion Graphic
Graphic OUT
RAM
Engine
Engine Synthesiser
Synthesiser
(EE)
(EE) (GS)
(GS)

RAM
RAM I/O
I/O Sound
Sound AUDIO
OUT
Processor
Processor Processor
Processor
EXTERNAL
DEVICES
(IOP)
(IOP) (SPU2)
(SPU2)

ROM
ROM CD/DVD
CD/DVD
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 Emotion Engine architecture
Overview

FPU
FPU
COP1 VU0
VU0 VU1
VU1
COP1 CPU
CPU GIF GS
Core GIF
Core COP2
COP2 EFU
INTC
INTC
128bit
Main
Bus

Timer
Timer DMAC
DMAC IPU
IPU DRAMC
DRAMC SIF
SIF

DRAM IOP
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 Emotion Engine architecture
CPU Core

FPU ¾ 128
¾ 128bit
bitCPU
CPU
FPU VU1
COP1
COP1 CPU ¾
¾VU0
300
VU0
300 MHz
MHz clock
VU1frequency
clock frequency
CPU GIF
GIF
GS
Core
Core ¾ 32
32Mb
¾COP2 Mbmain
main memory
memory
COP2 EFU
INTC
INTC ¾ MIPS
¾ MIPSIII IIIwith
withsome
someMIPSMIPSIVIVand
and
multimedia
multimediaextensions
extensions 128bit
¾ 64
¾ 64bit
bitinstructions,
instructions,22-way
-wayMain
Bus
superscalar
superscalar
Timer
Timer DMAC
DMAC¾ IPU
¾ 128IPUbit
128 DRAMC
bitmultimedia SIF
DRAMC instructions
multimedia SIF
instructions

DRAM IOP
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 Emotion Engine architecture
CPU Core

FPU ¾ 16Kb
¾ 16KbII-Cache
-Cache
FPU VU1
COP1
COP1 CPU ¾
¾VU0
8Kb
8KbDD-Cache
VU0 -Cache
VU1
CPU GIF
GIF
GS
Core
Core ¾ 16Kb
16Kbscratchpad
¾COP2 scratchpad
COP2 EFU
INTC
INTC
128bit
Main
Bus

Timer
Timer DMAC
DMAC IPU
IPU DRAMC
DRAMC SIF
SIF

DRAM IOP
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 Emotion Engine architecture
Floating Point Unit (FPU)

FPU
FPU
COP1 VU0
VU0 VU1
VU1
COP1 CPU
CPU GIF GS
Core GIF
Core COP2
COP2 EFU
INTC
INTC
128bit
Main
COP1
COP1for
forthe
theCPU
CPU Bus

Timer
Timer DMAC
DMAC IPU
IPU DRAMC
DRAMC SIF
SIF

DRAM IOP
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 Emotion Engine architecture
Timer

FPU
FPU
COP1 VU0
VU0 VU1
VU1
COP1 CPU
CPU GIF GS
Core GIF
Core COP2
COP2 EFU
INTC
INTC ¾ 44independent
¾ independenttimers
timers
¾ Driven
¾ Driveneither
either 128bit
Main
¾¾ by the bus clock (1/16 or 1/256
by the bus clock (1/16 or 1/256
Bus
intervals)
intervals)
Timer
Timer DMAC
DMAC ¾
¾ external
IPUexternal
IPU HH-BLNK
DRAMC-BLNK
DRAMC SIF
SIF

DRAM IOP
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 Emotion Engine architecture
DMA Controller (DMAC)

FPU
FPU¾ Vital to maximising the EE’s
VU0 VU1
VU1performance
COP1 ¾ Vital
COP1 CPU
CPU
to maximising
VU0 the EE’s performance
¾ Handles data transfers between GIF
mainGIF
GS
¾ Handles
Core
Core data transfers between main
memory COP2 EFU
memoryand each
eachprocessor/scratchpad
andCOP2 processor/scratchpad
INTC
INTC
128bit
Main
Bus

Timer
Timer DMAC
DMAC IPU
IPU DRAMC
DRAMC SIF
SIF

DRAM IOP
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 Emotion Engine architecture
Vector Units (VU0 & VU1)

FPU
FPU
COP1 VU0
VU0 VU1
VU1
COP1 CPU
CPU GIF GS
Core GIF
Core COP2
COP2 EFU
INTC
INTC
128bit
¾ Used
¾ Usedfor formathematical
mathematicaloperations
operations Main
Bus
¾ FMACs
¾ FMACsfor foraddition
additionand
andmultiplication
multiplication
¾ Timer
¾ FDIV
FDIV for
Timer DMAC
fordivision
DMAC
division and IPU
andsquare
IPU root
square DRAMC
root SIF
operations
DRAMC SIF
operations
¾ Built
¾ -in memory
Built-in memoryfor formicroprograms
microprograms
¾ VIFs
¾ VIFslinklinkthe
theVUs
VUs to
to the
the rest
rest of
ofthe
thesystem
system
DRAM IOP
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 Emotion Engine architecture
Vector Unit 0 (VU0)

FPU
FPU
COP1 VU0
VU0 VU1
VU1
COP1 CPU
CPU GIF GS
Core GIF
Core COP2
COP2 EFU
INTC
INTC
128bit
¾ 44FMACs
¾ FMACs, , 11FDIV
FDIV Main
Bus
¾ COP2
¾ COP2for
forthe
theCPU,
CPU,executing
executingmacroinstructions
macroinstructions
¾ Timer
¾ 44Kb VUMem
Timer
Kb VUMem DMAC
(data),
DMAC IPU
(data),44Kb
Kb DRAMC
IPUMicroMem
DRAMC
MicroMem SIF
(instructions)
SIF
(instructions)
¾ Useful
¾ Usefulfor
forcomplex
complexoperations
operationslike
likephysics
physicsetc.
etc.

DRAM IOP
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 Emotion Engine architecture
Vector Unit 1 (VU1)

FPU
FPU
COP1 VU0
VU0 VU1
VU1
COP1 CPU
CPU GIF GS
Core GIF
Core COP2
COP2 EFU
INTC
INTC
128bit
¾ No
¾ Nodirect
directpath
pathto
toCPU
CPUcore,
core,but
butdirect
directpath
pathto
toGIF
GIF Main
Bus
¾ 16
¾ 16Kb
KbVUMem
VUMem(data),
(data),16
16KbKbMicroMem
MicroMem(instructions)
(instructions)
¾ Timer
¾ Useful for
Timer
Useful DMAC
DMAC IPU
fortransformationsIPU DRAMC
transformations DRAMC SIF SIF

DRAM IOP
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 Emotion Engine architecture
Image Processing Unit (IPU)

¾ Image
¾ Imagedata
datadecompression
decompressionprocessor
processor
FPU
FPU
¾
¾ Decodes
Decodes
COP1 MPEG2
MPEG2VU0 streams
streams VU1
VU0 VU1
COP1 CPU
CPU GIF GS
¾ MacroBlock
¾ MacroBlock Decode GIF
Core Decode
Core COP2
COP2 EFU
¾ Vector Quantization
¾ Vector Quantization
INTC
INTC
¾ Transparency
¾ TransparencyControl
Control 128bit
Main
Bus

Timer
Timer DMAC
DMAC IPU
IPU DRAMC
DRAMC SIF
SIF

DRAM IOP
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 System Architecture

VIDEO
RAM Emotion
Emotion Graphic
Graphic OUT
RAM
Engine
Engine Synthesiser
Synthesiser
(EE)
(EE) (GS)
(GS)

RAM
RAM I/O
I/O Sound
Sound AUDIO
OUT
Processor
Processor Processor
Processor
EXTERNAL
DEVICES
(IOP)
(IOP) (SPU2)
(SPU2)

ROM
ROM CD/DVD
CD/DVD
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 GS specifications

¾ Clock Frequency 150 Mhz

¾ Embedded DRAM 4MB
¾ Total memory bandwidth 1.2Gb/sec
¾ Pixel fill rate 2.4GPixel/sec

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 System Architecture

VIDEO
RAM Emotion
Emotion Graphic
Graphic OUT
RAM
Engine
Engine Synthesiser
Synthesiser
(EE)
(EE) (GS)
(GS)

RAM
RAM I/O
I/O Sound
Sound AUDIO
OUT
Processor
Processor Processor
Processor
EXTERNAL
DEVICES
(IOP)
(IOP) (SPU2)
(SPU2)

ROM
ROM Disc
CD/DVD
Disc Drive
CD/DVD
Drive
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 IOP

¾ Contains an R3000 (PlayStation CPU+)

¾ 2 clock frequencies
¾ 2 Mb IOP memory
¾ Interfaces to the EE for
¾ controllers
¾ memory devices
¾ SPU 2
¾ CD/DVD unit
¾ USB/IEEE1394

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 System Architecture

VIDEO
RAM Emotion
Emotion Graphic
Graphic OUT
RAM
Engine
Engine Synthesiser
Synthesiser
(EE)
(EE) (GS)
(GS)

RAM
RAM I/O
I/O Sound
Sound AUDIO
OUT
Processor
Processor Processor
Processor
EXTERNAL
DEVICES
(IOP)
(IOP) (SPU2)
(SPU2)

ROM
ROM CD/DVD
CD/DVD
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 SPU 2

¾ 2 DSP cores, 48 Channels

¾ 2Mb sound memory
¾ Output to DAC or Optical digital output

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 Standard Peripherals

¾ PS one peripherals compatible (most)

¾ “DualShock2” as standard controller
¾ Large capacity “memory card” (8Mb)
¾ USB and i.Link (aka IEEE 1394) devices (non
proprietary interfaces)
¾ “broadband unit” (40GB HDD and network
adaptor)

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 USB Applications

¾ Digital Camera (e.g. via “Picture Paradise”

software or “eyetoy” game )
¾ Microphone (e.g. speech recognition and
communication software in “SOCOM: US
Navy Seals”)
¾ Scanner, Printer (Japan titles)
¾ Keyboards, Mouse (Yabasic, PS2 Linux)

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 And what happens next …

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 Products based upon the “Cell Processor”

¾ A chip triumvirate of IBM, Sony and Toshiba

has pledged $400 million to the project and
sent engineers to a joint development centre in
Austin, Texas

¾ “We are working for the third-generation

(PlayStation) with this very aggressive and
crazy goal… Moore's Law is too slow for us."
Shin’ichi Okamoto (SCE CTO)

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 Questions?

On the web:
http://www.technology.scee.net/

E-mail:
[email protected]

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