Ece 2003

Course Code Course Title LT P J C
ECE2003 DIGITAL LOGIC DESIGN 2 0 2 0 3

Prerequisite: ECE1002 – Semiconductor Devices and Circuits Syllabus version
v1.0
Course Objectives:
The course is aimed at,
1. To represent logical functions in canonical form and standard forms
2. To design and analyse the combinational logic circuits
3. To design and analyse the sequential logic circuits
4. To implement the combinational and sequential logic circuits using Verilog HDL
Expected Course Outcome:

At the end of the course the student should be able to
1. Understanding the number systems and IC characteristics
2. Understanding the Boolean algebra and its properties
3. Optimizing the logic functions using K-map
4. Design and analyse the combinational logic circuits
5. Understanding Verilog HDL syntax
6. Design and analyse the sequential logic circuits
7. Implement and simulate the combinational logic circuits using Verilog HDL
Student Learning Outcomes (SLO): 2, 5

2. Having a clear understanding of the subject related concepts and of contemporary issues
3. Having design thinking capability
Module:1 Number systems and Logic Families: 3 hours CO: 1

Brief review of Number Systems, Digital Logic Gates and its electrical characteristics, Review
of RTL, DTL, TTL, ECL, CMOS families.
Module:2 Boolean algebra: 2 hours CO: 2

Basic Definitions, Axiomatic Definition of Boolean Algebra, Basic Theorems and Properties of
Boolean Algebra, Boolean Functions, Canonical and Standard Forms.
Module:3 Gate-Level Minimization: 3 hours CO: 3

The Map Method - K-map, Product of Sums and Sum of Products Simplification, NAND and
NOR Implementation
Module:4 Design of Combinational Logic Circuits: 5 hours CO: 4

Design Procedure, Binary Adder-Subtractor, Parallel Adder, Binary Multiplier,
MagnitudeComparator-4 bit, Decoders, Encoders, Multiplexers, De-multiplexer, Parity generator
and checker. Application of Mux and Demux.
Module:5 Verilog HDL Coding Style: 4 hours CO: 5

Lexical Conventions, Ports and Modules, Gate Level Modeling, Operators, Data Flow Modeling,
Behavioral level Modeling, Testbench.
Module:6 Design of Sequential Logic Circuits: 6 hours CO: 6
Latches, Flip-Flops-SR, D, JK & T, Shift Registers-SISO, SIPO, PISO,PIPO, Design of
synchronous sequential circuits- State table and state diagrams, Design of counters-Modulo-n,
Johnson, Ring, Up/Down, Design of Mealy and Moore FSM -Sequence detection.
Module:7 Modeling of Logic Circuits: 5 hours CO: 7

Modeling of Combinational and Sequential Logic Circuits using Verilog HDL.
Module:8 Contemporary Issues 2 hours
Total Lecture Hours: 30 hours

Text Books:
1. M. Morris R. Mano and Michael D. Ciletti , “Digital Design With an Introduction to the
Verilog HDL”, 2014, 6th Edition, Prentice Hall of India, India..
Reference Books:
1. Charles H. Roth, Jr., "Fundamentals of Logic Design", 2014, 7th Edition Reprint,
Brooks/Cole, Pacific Grove, US.
2. Michael D. Ciletti, 2011, “Advanced Digital Design with the Verilog HDL, 2nd Edition”,
Pearson Pvt. Ltd, Noida, India.
3. Stephen Brown and ZvonkoVranesic, 2013, “Fundamentals of Digital Logic with Verilog
Design”, Third Edition, McGraw-Hill Higher Education, New Delhi, India.
Mode of Evaluation: Continuous Assessment Test –I (CAT-I), Continuous Assessment Test –II
(CAT-II), Digital Assignments/ Quiz / Completion of MOOC, Final Assessment Test (FAT).
Sl.No. List of Challenging Experiments (Indicative) CO: 7

1 Characteristics of Digital ICs (Hardware) 4 hours
2 Implementation of Combinational Logic Design using 4 hours
MUX/Decoder ICs (Hardware)
3 Design and Implementation of various data path elements 4 hours
Adders/Multipliers (Hardware)
4 Design and Implementation of various data path elements like 6 hours
Adders/Multipliers and combinational Logic circuits like Multipliers
(Mandatory: Verilog Modeling, Simulation and Synthesis. FPGA
implementation (optional)
5 Design and implementation of simple synchronous sequential 2 hours
circuits like Counters / Shift registers (Hardware)
6 Complex state machine design (Simulation and Synthesis) 4 hours
7 Simple processor design (Simulation and Synthesis) 6 hours
Total Laboratory Hours: 30 hours
Mode of Evaluation: Continuous Assessment of Challenging experiments / Final Assessment
Test (FAT).
CO – SLO mapping
Module CO SLO
1 CO_01 2
2 CO_02 5
3 CO_03 5
4 CO_04 5
5 CO_05 5
6 CO_06 5
7 CO_07 5

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Course Code Course Title LT P J C

ECE2003 DIGITAL LOGIC DESIGN 2 0 2 0 3

Expected Course Outcome:

Student Learning Outcomes (SLO): 2, 5

Module:1 Number systems and Logic Families: 3 hours CO: 1

Module:2 Boolean algebra: 2 hours CO: 2

Module:3 Gate-Level Minimization: 3 hours CO: 3

Module:4 Design of Combinational Logic Circuits: 5 hours CO: 4

Module:5 Verilog HDL Coding Style: 4 hours CO: 5

Module:7 Modeling of Logic Circuits: 5 hours CO: 7

Module:8 Contemporary Issues 2 hours

Total Lecture Hours: 30 hours

Sl.No. List of Challenging Experiments (Indicative) CO: 7

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