Design and implementation of

various components of a high

speed Flash ADC
A REPORT SUBMITTED
By

BIKASH KUMAR MOHARANA

Roll No: 113EI0295
to
Department of Electronics and Communication Engineering

Under the guidance of

Prof. KAMALAKANTA MAHAPATRA

NATIONAL INSTITUTE OF TECHNOLOGY ROURKELA

ROURKELA, ORISSA
Abstract:
The real world signals are analog. Due to the processing complexity of the analog signal, it is
converted to digital form so that processing becomes easier. Therefore, analog-to -digital
converter acts as an interface in between analog signal and digital signal processing systems. In
this project we are designing the various components of a high speed five-bit Flash ADC which
can be used in radar application for data acquisition, wireless signal processing circuits and also
in home automation systems. We have designed a resistor ladder for the five-bit Flash ADC
taking 1.2v as the input voltage and the resistance as 100 ohms to get equally distributed
reference voltages to give input to comparator. We have also designed a pair of comparator, with
1.2volts supply voltage in UMC_90nm and GPDK_90nm Technology. Static and dynamic
characteristics of the designed comparators are calculated and are given in the report. The
speed of the comparator in designed in UMC_90nm is found to be 9.26GHz with slew rate
5.54v/ns and total power dissipation of 156µWatt. The speed of the comparator in designed in
GPDK_90nm is found to be 11.19GHz with slew rate 6.71v/ns and total power dissipation of
201.5µWatt. The design of the encoder for thermometer to binary conversion is in developement.

Flash ADC:
Flash ADCs utilize massive parallelism in its architectures and hence the name parallel ADC.
The results of the conversion are available at the end of one clock cycle. Due to the parallel
structural design it is the fastest ADC among all the other types and is appropriate for large
bandwidth applications such as radar processing data acquisition, high density disk drives,
satellite communication, data communications and real time oscilloscopes. It is also highly used
in other types of ADCs such as pipeline ADCs and multi bit sigma delta ADCs. Flash ADC is
limited to a resolution of six to eight bits because the numbers of comparators utilized in these
ADCs are doubled if the resolution is enhanced by one bit. Due to this, it consumes a lot of power
and becomes costly, as the resolution increases.

Comparator Design:
The comparator is a crucial part of almost all kind of analog-to-digital (ADC) converters. Speed,
gain, power dissipation, offset and resolution are the important parameters of any type of
comparators. The type and architecture of the comparator is having a considerable impact on the
performance of the target application. The fundamental aim of the comparator is to compare an
input signal (Vin) with a reference signal (Vref) and to produce an output logic low or logic high
depending on whether the input signal is greater or smaller than reference. Comparator can be
considered as a decision making circuit because it makes a decision based on the value of input
signal and reference signal.
Previous design and modification:
Two comparators such as: clocked and non-clocked were designed previously in UMC 90nm
Technology with low-leakage nmos and pmos transistors, which gave low power dissipation due
to low leakage but high propagation delay. Leakage power dissipation increases with increase in
temperature, supply voltage and aspect ratio. However, it works opposite for propagation delay.
Therefore, the clocked or Regenerative latch comparator was designed again with standard
performance (SP) transistors, which gave significantly less delay but moderate power dissipation.
But as the SP transistors were of supply voltage 1v, so we had to go for other design techniques.
In GPDK (Generic Product Design Kit) 90nm technology , the comparator was again designed
with 1.2v supply voltage, and the results from this design is much better than the desired result in
context of delay, but the power dissipation is increased slightly. Both the comparators were
simulated for both square and sine wave and the results were obtained and the propagation
delay, power dissipation and the slew rates were compared.

Comparator in UMC 90nm:

Fig-1 Circuit of the comparator in UMC 90nm

 Comparator in GPDK 90nm:

Fig-2 Circuit of the comparator in GPDK 90nm

Results:
Comparator in UMC 90nm:

Fig-3 Dc analysis of the comparator in UMC 90nm

1. Pulse input:
Vin=1.2V with period= 2ns and tr=tf=100ps
Vref=600mV dc

Fig-4 Output waveform for pulse input (Transient analysis)

Parameters:
1. Propagation delay: (Transient analysis for 10ns)
Trising= (159 - 50) ps = 109 ps
Tfalling= (1.257-1.15) ns = 107.42 ps
Tpd= propagation delay= Average (Trising + Tfalling) = 108.212 ps
2. Speed
Speed= (Tpd)-1 = 9.26 GHz
3. Total power dissipation
Vin=1.2 V with period= 2ns and tr=tf=100ps

Vref=600mV dc and CLK=1.2V with period 125p s and tr=tf=1ps

Ptotal= 156 µwatt
4. Offset voltage
11.9979mV (From the DC analysis)
5. Slew rate
Output span/(2 * Tpd ) = (1.2 – 0) / (2 * 108.212) = 5.54 V/ns
Comparator in GPDK 90nm:
DC analysis:

Fig-5 Dc analysis output

Pulse input:

Vin=1.2V with period= 2ns and tr=tf=100ps

Vref=600mV dc

Fig-6 Output waveform for pulse input (Transient analysis)

 Parameters:
1. Propagation delay: (Transient analysis for 10ns)
Trising= (136.09 - 50) ps = 86.09 ps
Tfalling= (1.2427-1.15) ns = 92.7 ps
Tpd= propagation delay= Average (Trising + Tfalling) = 89.395 ps
2. Speed
Speed= (Tpd)-1 =11.17 GHz
3. Total power dissipation
Vin=1.2V with period= 2ns and tr=tf=100ps

Vref=600mV dc and CLK=1.2V with period 125ps and tr=tf=1ps

Pdynamic= 201.5µwatt
4. Offset voltage
12.0014mV (From the DC analysis)
5. Slew rate
Output span/(2 * Tpd ) = (1.2 – 0) / (2 * 89.395) = 6.71 V/ns

Resistor Ladder:

 A resistor ladder is designed to provide a stable reference voltage to the comparators. The resistor
ladder network is formed by 2N resistors, which divide the main reference voltage into 2N equally
spaced voltages. In the proposed five-bit flash ADC implementation, Vref1= 1.2 V and Vref2 = 0 V.
 One of the major problems associated with resistor ladder is the signal feed through of the input
signal to the resistor ladder. The parasitic capacitances are present between the source and gate of
the comparator inputs. The gate source capacitance couples the reference voltage (Vref) into input
voltage (Vin). This causes a deviation in the reference voltage generated by the resistor ladder.
 In order to overcome this problem a series of decoupled capacitors are used in the resistor ladder.
But with this the power dissipation increases, so optimized value of the resistances to be taken for the
resistor ladder.
As a 5 bit Flash ADC is to be designed, so the no of resistor used here is 25 = 32.
With the help of de-coupling, Rladder,max can be calculated as
2
Rladder,max= where µ𝑑= decoupling number = 4,
𝜋∗ µ𝑑∗𝑓𝑖𝑛∗𝐶𝑖𝑛,𝑡𝑜𝑡𝑎𝑙

= 3200 Ω (100 Ω each) Cin,total = 90 fF (assumption) and

fin = 546.875 MHz
 Fig-7 Resistor ladder in GPDK 90nm technology:

Conclusion:
Modern communication systems necessitate higher data rates which have increased the demand
for the high speed transceivers. For a system to work efficiently, all blocks of that system should be
fast. It can be seen that the analog interfaces are main bottleneck in the whole system in terms of
speed and power. This fact has led researchers to develop and implement high-speed analog-to-
digital converters (ADCs) with low power consumption.
The work till now demonstrates the design of the comparator in UMC 90nm technology gives more
delay than the GPDK 90nm technology, so the speed of the comparator in GPDK 90nm is higher
than the former. So the comparator in GPDK 90nm technology will be adopted for the encoder
design. The resistor ladder and the comparator design is almost complete and the comparator
needs optimization for power dissipation. The design of the encoder for thermometer to binary
conversion is in development.

References:
[1] Philip E. Allen and Douglas R. Holberg, CMOS Analog Circuit Design, 2nd ed., Oxford Indian
Edition, 2006
[2] G. T. Verghese, K,K Mhapatra, “Design AND IMPLEMENTATION OF a Novel flash adc for ultra
wide band applications,” Ph. D Report for NIT Rourkela, India,May 2014.
[3] Prasun Bhattacharyya, K,K Mhapatra , "Design of a novel high speed dynamic comparator with
low power dissipation for high speed ADCs," M. Tech Report for NIT Rourkela, India, May, 2011
[4] M. Miyahara, Y. Asada, P. Daehwa and A. Matsuzawa, “A Low-Noise Self- Calibrating Dynamic
Comparator for High-Speed ADCs,” IEEE Asian solid state conference, pp. 269-272, Nov. 2008
[5] K. Uyttenhove and M. Steyaert “Design of high‐speed analog‐to‐digital interface in digital
technologies”, 8th IEEE International Conference on Electronics, Circuits and Systems, vol.1,
pp. 493‐496, Sep 2001
[6] N Jain, M.N. Islam, “Low power dynamic comparator design using variable resistor”, M. Tech
Report for NIT Rourkela, India, April, 2015